Senior Dft Engineer Job in Caliber Interconnect Solutions

Senior DFT Engineer

Location: Coimbatore

Job Type: Full Time

Experience: Minimum 4 8 Years

About the Role:

We are seeking a Senior DFT Engineer with strong experience in Design-for-Test implementation for complex SoC/ASIC designs. The ideal candidate will be responsible for developing and integrating DFT architectures to ensure optimal test coverage, manufacturability, and debug capability of silicon designs.

Key Responsibilities:

• Define and implement DFT architecture for SoCs and ASICs, including scan insertion, boundary scan (JTAG/IEEE 1149.1), MBIST (Memory BIST), and logic BIST.
• Work with RTL designers to integrate scan chains and test logic into the design while maintaining timing and area constraints.
• Generate and simulate ATPG (Automatic Test Pattern Generation) vectors for scan and stuck-at/fault models.
• Develop MBIST controllers and work with memory compilers/IP vendors to ensure BIST compatibility.
• Collaborate with physical design teams for DFT-related floorplanning, synthesis, and timing closure.
• Support silicon bring-up, test vector validation, and ATE (Automated Test Equipment) support during production testing.
• Run DFT verification flows, identify issues, and work cross-functionally to resolve them.
• Ensure compliance with test coverage goals and generate detailed reports using tools like Tetramax, TestKompress, or Mentor Tessent.

Required Skills & Experience:

• Bachelor s or Master s degree in Electronics, Electrical Engineering, or related field.
• 4 8 years of hands-on experience in DFT implementation for ASIC/SoC designs.
• Strong experience with:
  • Scan insertion and ATPG
  • MBIST/logic BIST
  • JTAG and boundary scan (IEEE 1149.x standards)
• Proficiency in DFT tools such as:
  • Synopsys Tetramax/DCT
  • Cadence Modus
  • Mentor Tessent
• Scripting skills in TCL, Perl, or Python for DFT automation.
• Good understanding of digital design, RTL (Verilog/VHDL), synthesis, and timing analysis (STA).
• Experience in DFT sign-off and handling silicon test/debug is a strong plus.

Nice to Have:

• Experience in low power DFT and DFT for hierarchical designs.
• Familiarity with industry standard ATEs (Advantest, Teradyne).
• Exposure to ISO26262 (for automotive) or other quality standards.
• Experience working with chip bring-up teams or foundry interfaces.

Soft Skills:

• Strong problem-solving and debugging skills.
• Good communication and collaboration abilities.
• Ability to work independently and in cross-functional teams.
• Detail-oriented with strong documentation skills.