Asic Engineer, Implementation Job in Meta Careers

ASIC Engineer, Implementation

Location: Bangalore, India Full Time

Company: Meta

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location.

ASIC Engineer, Implementation Responsibilities:

• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power.
• Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them.
• Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities.
• Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures.
• Perform RTL Lint and work with designers to create necessary waivers.
• Perform RTL DFT Analysis and improve coverage for Stuck-at faults.
• Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off.
• Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams.
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs.
• Analyze inter-block timing and generate IO budgets for partition blocks.
• Develop Power Intent Specification in UPF for multi-Vdd designs.
• Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power.
• Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks.
• Collaborate with Physical Design Engineers to provide timing and congestion feedback.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.
• 5+ years of experience in Design Integration and Front-End Implementation.
• Experience with RTL Synthesis and design optimization for Power, Performance, and Area.
• Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs.
• Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues.
• Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows.
• Experience communicating and collaborating with internal teams and vendors.

Preferred Qualifications:

• Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC.
• Background in Synthesis, Timing Constraints Development, Floorplanning, and STA.
• Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories.
• Experience with Power, Performance, Area analysis techniques for power reduction.
• Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools.
• Strong programming and scripting skills using Perl/Python, TCL, and Make.

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology.

Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics.

Equal Employment Opportunity:

Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics.