Physical Design Job in Spectrum Consultants India Pvt Ltd
Physical Design
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Bengaluru, Bangalore Urban, Karnataka
- Not Disclosed
- Permanent
Job Summary
In your new role, you will be responsible for:
1. Leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets
2. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond)
3. Ownership of constraints development for functional/test modes at pre and post layout stage
4. Opportunity to work on IO timing closure for critical interfaces like Serial Peripheral and External Memory Interfaces
5. Timing analysis and convergence of large hierarchical design across multiple modes and corners
6. Interact with RTL and DFT teams on timing feasibility and performance assessment
Work closely with physical design team for timing/SI closure
You are best equipped for this task if:
B.Tech or M.Tech with 10+ years of relevant work experience and specialization in VLSI design
Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs
Experience in low-power synthesis and equivalence checks will be a plus
Expert user of industry standard tools for timing signoff
Experience in scripting languages (shell, perl, tcl) and Make flow
Must be well organized, methodical and detail oriented
Strong commitment and determination in area of expertise
Takes initiatives and overcomes challenges through creativity and innovation
Coordinates with colleagues and actively shares expertise with others
Shares information comprehensively and effectively
Cooperates across boundaries and appreciates the contributions of other people
1. Leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets
2. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond)
3. Ownership of constraints development for functional/test modes at pre and post layout stage
4. Opportunity to work on IO timing closure for critical interfaces like Serial Peripheral and External Memory Interfaces
5. Timing analysis and convergence of large hierarchical design across multiple modes and corners
6. Interact with RTL and DFT teams on timing feasibility and performance assessment
Work closely with physical design team for timing/SI closure
You are best equipped for this task if:
B.Tech or M.Tech with 10+ years of relevant work experience and specialization in VLSI design
Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs
Experience in low-power synthesis and equivalence checks will be a plus
Expert user of industry standard tools for timing signoff
Experience in scripting languages (shell, perl, tcl) and Make flow
Must be well organized, methodical and detail oriented
Strong commitment and determination in area of expertise
Takes initiatives and overcomes challenges through creativity and innovation
Coordinates with colleagues and actively shares expertise with others
Shares information comprehensively and effectively
Cooperates across boundaries and appreciates the contributions of other people
Experience Required :
15 to 20 Years
Vacancy :
2 - 4 Hires
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