Asic Development Jobs in Bengaluru

Business Development Manager Oleo Chemicals Location: Bangalore Experience: 2+ years Work Type: Full-Time About Scimplify Scimplify is a specialty chemicals manufacturing company offering end-to-end solutions from R&D and custom synthesis to large-scale manufacturing and doorstep delivery. Headquartered in Bengaluru, we serve multiple industries including pharmaceuticals, agrochemicals, industrial chemicals, personal care, and fragrances. We enable 500+ businesses across 20+ countries to scale innovative chemicals from lab to commercial production. With over $54 million raised from investors like Accel and Bertelsmann, Scimplify has global operations in India, Japan, USA, UAE, and Indonesia, and a growing team of 250+ professionals. Learn why Forbes recognizes us as one of the top 100 startups in Asia to watch. Role Overview We are seeking a Business Development Manager to drive growth in the Oleo Chemicals segment. The ideal candidate will have a deep understanding of oleo chemical products and applications across personal care, home care, pharmaceuticals, food, lubricants, and industrial chemicals, while building strong client relationships and expanding Scimplify s market presence. Key Responsibilities Identify, develop, and manage new business opportunities in the Oleo Chemicals segment. Build and maintain long-term relationships with key customers, distributors, and channel partners. Conduct market research to analyze trends, competitor activities, and customer needs. Develop sales strategies, pricing models, and business plans to achieve revenue targets. Collaborate with supply chain, R&D, and operations teams to ensure smooth delivery and customer satisfaction. Represent Scimplify in trade shows, exhibitions, and industry networking events. Provide market intelligence and customer feedback to inform product portfolio and strategy. Track and report sales performance, pipeline, and forecasts to leadership. Qualifications & Skills Bachelor s degree in Chemistry, Chemical Engineering, or related field (MBA preferred). 3 years of proven experience in Business Development/Sales in Oleo Chemicals or Specialty Chemicals. Strong understanding of oleo chemical products (fatty acids, fatty alcohols, esters, glycerine, etc.) and their end-use industries. Established network of clients and distributors in the sector is highly desirable. Excellent negotiation, communication, and presentation skills. Strong analytical mindset, able to convert insights into actionable business plans. Self-motivated, target-driven, and comfortable in a fast-paced startup environment. Benefits & Perks Travel & Mobility: Corporate Uber/MMT, relocation & transfer support, travel policy. Insurance & Wellness: Family health coverage (up to 5 members, 5 L), Employee Assistance Program, onsite medical, emergency support, online doctor consultation. Lifestyle & Engagement: Monthly outings, corporate dinners, parties, trips, parental support (maternity/paternity, daycare). Retirement & Financial: Employee PF contribution, flexible PF, NPS, car lease, salary advance policy. Qualification : Bachelors degree in Chemistry, Chemical Engineering or related field (MBA preferred)

Position: Catalog Head Location: Bengaluru Company: Ace Turtle Employment Type: Full-Time About Ace Turtle: Ace Turtle is India s leading tech-native retail company, driving the next phase of transformation in the retail industry. Vertically integrated from design to local manufacturing, marketing, and direct consumer engagement, Ace Turtle leverages proprietary technology and data science to meet the ever-evolving needs of today s consumer. Based in Bengaluru and Singapore, Ace Turtle is the exclusive licensee for iconic global brands such as Lee , Wrangler , Toys R Us , Babies R Us , and Dockers in India and South Asia. Role Overview: As the Catalog Head at Ace Turtle, you will oversee the development, organization, and management of our product catalog, ensuring it aligns with business goals and customer needs. You will work closely with cross-functional teams to maintain an accurate, up-to-date, and engaging catalog that drives sales and enhances the online shopping experience. Key Responsibilities: 1. Catalog Development & Management: Collaborate with product managers, marketing teams, and suppliers to gather comprehensive product data, including specifications, images, and pricing, to build an accurate and dynamic catalog. Regularly update and maintain the catalog, adding new products, removing discontinued items, and ensuring all details such as prices and stock availability are accurate. Ensure the catalog reflects the company s brand identity and product offerings effectively. 2. Data Management & Quality Control: Organize and manage product data, ensuring consistency, accuracy, and integrity across all entries. Handle categorization, tagging, and product attributes, applying best practices in product taxonomy and merchandising techniques. Conduct regular audits to identify and resolve any data discrepancies, ensuring seamless catalog updates. 3. Content Creation & Optimization: Write clear, persuasive, and SEO-optimized product descriptions that highlight key features, benefits, and unique selling points. Optimize product titles, meta tags, and other catalog content elements to enhance search engine visibility and drive conversions. 4. Catalog Presentation & User Experience: Collaborate with design and creative teams to present the catalog in an attractive, intuitive, and user-friendly format. Focus on improving catalog layout, navigation, and visual elements to enhance user experience and drive product discovery. Work with UX/UI teams to ensure an easy and seamless shopping experience, including effective filtering, sorting, and search functionalities. 5. Cross-Functional Collaboration: Partner with internal teams (marketing, sales, e-commerce, procurement) to align catalog strategies with broader business objectives. Collaborate with suppliers and vendors to ensure accurate product listings and timely updates. 6. Performance Analysis & Continuous Improvement: Monitor key performance metrics such as conversion rates, click-through rates, and customer feedback to gauge catalog performance. Use data-driven insights to optimize the catalog s effectiveness and drive improvements in user experience and sales. 7. Project Management: Manage multiple catalog-related projects concurrently, prioritize tasks, and meet deadlines in a fast-paced eCommerce environment. Coordinate with stakeholders to ensure timely execution of catalog updates and improvements. What We re Looking For: Experience: 8+ years of relevant experience in catalog management, product data management, or eCommerce merchandising. eCommerce Expertise: Strong understanding of eCommerce platforms, online retail best practices, and industry trends. Data Management: Proficiency in managing product data in eCommerce platforms or Product Information Management (PIM) systems. Ability to use data analytics tools. Attention to Detail: High level of accuracy in managing product data, ensuring consistency and quality control across the catalog. Communication Skills: Excellent written and verbal communication skills, with the ability to create compelling product descriptions. Analytical Abilities: Strong analytical and problem-solving skills, with the ability to identify opportunities for catalog optimization based on data insights. Technical Proficiency: Familiarity with eCommerce platforms, CMS tools, and digital marketing tools. Basic knowledge of HTML, CSS, or other web development languages is a plus. Project Management: Strong organizational and multitasking skills to manage projects efficiently. Innovative Environment: Be part of a leading tech-native retail company shaping the future of the industry. Growth Opportunities: Work with iconic global brands and contribute to a high-impact, fast-growing business. Collaborative Culture: Join a dynamic, cross-functional team focused on driving results and continuous improvement. Global Reach: Play a pivotal role in managing the product catalog for an internationally recognized portfolio of brands.

Functional Safety Engineer Location: Bangalore Experience: 3 6 Years Education: B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, Computer Science, or a related field Job Summary We are seeking a skilled and motivated Functional Safety Engineer to join our automotive embedded systems team. The ideal candidate will have hands-on experience with ISO 26262, strong embedded C programming knowledge, and a solid understanding of the software development lifecycle. This role is critical in ensuring that all safety-critical systems are developed in compliance with industry safety standards and regulations. Key Responsibilities Develop and maintain the Functional Safety Management System (FSMS) in line with ISO 26262 standards. Conduct hazard analysis and risk assessments (HARA) for automotive embedded systems. Define, allocate, and manage functional and technical safety requirements across hardware and software components. Support and guide development teams in achieving ASIL (Automotive Safety Integrity Level) compliance. Collaborate with hardware and software teams to ensure safety mechanisms are implemented and validated effectively. Prepare and maintain safety-related documentation, including Safety Plans, Safety Cases, and Safety Analyses (FMEA, FTA, DFA, etc.). Ensure traceability of safety requirements throughout the SDLC, using appropriate tools and processes. Participate in reviews, audits, and assessments to ensure continuous compliance with ISO 26262. Support safety validation and verification activities. Required Skills & Experience 3 6 years of experience in Functional Safety Engineering, with a minimum of 2+ years working specifically with ISO 26262. Proficient in Embedded C programming, with exposure to real-time embedded systems. Strong understanding of the Software Development Life Cycle (SDLC) in safety-critical environments. Good analytical and problem-solving skills. Effective communication and collaboration skills to work with cross-functional teams. Preferred / Added Advantage Experience in the automotive domain (e.g., ADAS, powertrain, or body control modules). Familiarity with automotive communication protocols (CAN, LIN, FlexRay). Exposure to toolchains like DOORS, Polarion, or Jama for requirement and safety management. Knowledge of complementary standards such as ISO 21434 (Cybersecurity) or IEC 61508. Work on innovative and safety-critical projects for global automotive clients. Opportunity to deepen your expertise in functional safety and ISO 26262. Collaborate with a high-caliber team in a technically driven environment. Competitive compensation, learning opportunities, and career advancement paths. Qualification : .E / B.Tech / M.E / M.Tech in Electronics, Electrical, Computer Science, or a related field

Job Title: Backend Developer Intern (SDE) Cybersecurity | CloudSEK Location: Bengaluru, Karnataka, India About CloudSEK CloudSEK is a fast-growing AI-powered cybersecurity company that specializes in digital risk monitoring. Founded in 2015 and headquartered in Singapore, we are building the world s fastest and most reliable AI platform to identify and mitigate digital threats in real-time. We ve received multiple accolades, including: NASSCOM-DSCI Excellence Award for Security Product Company of the Year NetApp Excellerator s Best Growth Strategy Award Raised $7M Series A funding led by MassMutual Ventures At CloudSEK, we foster a culture that values curiosity, creativity, and collaboration. If you're passionate about cybersecurity and backend development, we want you on our team! What You'll Do (Internship Responsibilities) As a Backend Development Intern (SDE), you will: Work with experienced developers to design, build, and maintain scalable backend systems for our cybersecurity products Write clean and efficient code using modern programming languages like Node.js or Go Collaborate with cross-functional teams including front-end developers, data scientists, and product managers to deliver innovative features Participate in code reviews and contribute to maintaining high-quality coding standards Troubleshoot and fix bugs, performance bottlenecks, and security issues Document technical specifications and support materials Stay updated with emerging technologies in backend development and cybersecurity What We're Looking For (Intern Requirements) Pursuing or recently completed a degree in Computer Science, Software Engineering, or related field Solid understanding of backend development with skills in Node.js or Go Basic knowledge of APIs, databases (SQL), and web technologies Strong analytical and problem-solving abilities Excellent communication and teamwork skills Eagerness to learn, adapt, and grow in a dynamic environment Passion for cybersecurity and innovation Preferred Qualifications (Nice to Have) Exposure to cloud platforms like AWS, GCP, or Azure Experience with Docker, Kubernetes, or similar containerization tools Familiarity with CI/CD pipelines, Git, Jenkins, and DevOps workflows Understanding of NoSQL databases, caching, and distributed systems Hands-on experience working on real-world cybersecurity products Mentorship from a team of industry experts Flexible working hours and an open, vibrant office culture Free food, unlimited snacks, and drinks at our Bengaluru office Fun team events, games, and music we work hard and celebrate harder! Note: This is a paid internship opportunity. Duration and stipend will be discussed during the interview process. Join CloudSEK as a Backend Intern and work on cutting-edge technology that protects global digital assets. Apply now to be part of a team that s shaping the future of digital risk management. Qualification : Pursuing or recently completed a degree in Computer Science, Software Engineering, or related field

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Machine Learning Engineer 5 Location: Bangalore, Karnataka, India Employment Type: Full-Time About Adobe Adobe is transforming the world through digital experiences. From individual creators to global enterprises, our tools empower everyone to create stunning visuals, videos, applications, and more. We believe in fostering an inclusive and innovative workplace where ideas can come from anyone, anywhere and the next big breakthrough could be yours. The Opportunity Adobe Express enables users from beginners to professionals to design eye-catching content with ease, powered by advanced AI technologies. At the heart of this mission is the AI Foundations team, which is building modular, reusable AI systems and the Horizon AI Stack to supercharge the Adobe Express experience. As a founding member of this elite team, you will tackle strategic AI challenges and deliver scalable, high-impact solutions. What You ll Do Drive the vision and development of reusable, cloud-scale AI systems for Adobe Express. Collaborate with Adobe Research, Applied AI teams, and engineering stakeholders to align AI capabilities with product strategy. Lead all aspects of ML product development: data pipelines, model development, and quality evaluations. Recruit, mentor, and manage a high-performing team of ML engineers and data scientists. Balance cutting-edge research with business-critical deliverables prototyping new ideas, validating, and scaling them. Foster a culture of innovation, experimentation, and scientific rigor focused on solving customer problems. Ensure engineering excellence in architecture, development, and on-time delivery of AI solutions. Basic Qualifications Bachelor s, Master s, or Ph.D. in Computer Science, Machine Learning, Applied Math, Data Science, or related field. 8+ years of industry experience in machine learning, deep learning, or optimization algorithms. 3+ years of experience managing ML/AI teams in a product-focused environment. Preferred Qualifications Experience working in creative tools, design platforms, or imaging domains. Familiarity with LLMs, Diffusion Models, and generative AI techniques. Proven experience in building large-scale, production-grade ML systems. What You Need to Succeed Demonstrated success in building and managing top-tier ML teams that deliver high-quality solutions. Experience shipping widely adopted AI-driven features to large customer bases. Customer-obsessed with a strong product sense and ability to translate user needs into AI capabilities. Outstanding communication skills able to articulate technical ideas to both technical and non-technical audiences. Strong problem-solving, leadership, and strategic decision-making abilities. Work at the intersection of creativity and AI building technologies that empower millions of users globally. Collaborate with world-class researchers and engineers in a mission-driven, inclusive environment. Enjoy robust career growth, leadership opportunities, and excellent employee benefits. Adobe is proud to be an Equal Opportunity Employer. We believe diversity fuels innovation and we re committed to building an inclusive environment for all employees. Qualification : Bachelors, Masters, or Ph.D. in Computer Science, Machine Learning, Applied Math, Data Science, or related field.

Senior PLM Analyst Teamcenter Location: Bengaluru Experience Required: 2 5 years Company: Pratt & Whitney (Raytheon Technologies) Job Overview Pratt & Whitney is looking for an experienced Senior PLM Analyst with a strong background in Teamcenter PLM systems to support the Engineering Applications team in delivering digital transformation and Model-Based Systems Engineering solutions across the enterprise. Responsibilities Develop, implement, and support customized PLM solutions using Teamcenter. Work closely with Engineering and DevOps teams to improve system availability, performance, and integration. Participate in Agile ceremonies, code reviews, sprint planning, and backlog grooming. Consult on PLM configuration issues, digital thread integration, and MBSE alignment. Contribute to the PLM roadmap and evaluate new tools and technologies like OpenPDM. Provide support for deployment, monitoring, and optimization of PLM tools. Assist with technical documentation, project status updates, and stakeholder presentations. Basic Qualifications 2 5 years of experience in PLM Teamcenter development and integration. Proficiency in customizing, configuring, and deploying PLM platforms. Strong communication, leadership, and cross-functional collaboration skills. Familiarity with DevSecOps practices and agile development methodologies. Preferred Qualifications Hands-on experience with Teamcenter Systems Modeler and OpenPDM. Understanding of MBSE, digital twin, or digital thread concepts. Ability to drive end-to-end solutions from design to implementation. Strong analytical and organizational skills with a proactive attitude. At Pratt & Whitney, we're redefining the future of aerospace. Join us to be part of a world-class team creating innovative technologies that power modern flight and sustainable innovation. Equal Opportunity Statement We are an equal opportunity employer and consider all qualified applicants without regard to race, color, religion, sex, national origin, disability, or protected veteran status. Apply Now Explore your potential with Pratt & Whitney. Apply today and be part of the digital transformation in aerospace engineering.

Senior Lead Engineer Structural Analysis (Hybrid) Location: Bangalore, Karnataka, India Job Type: Full-time Company: Collins Aerospace (Raytheon Technologies) Experience: 5 8 years Job Overview We re looking for a Senior Lead Engineer (Stress) to join our Advanced Structures business unit. This role leads structural analysis for New Product Introduction, redesign, and technology programs. Support includes a wide range of aerospace components including ETRAS systems. Responsibilities Lead stress analysis using FEA tools (Ansys) and classical hand calculations. Prepare structural analysis documentation, stress reports, and certification data. Collaborate with design, manufacturing, and quality teams. Investigate failures and provide technical resolutions. Contribute to process improvements, automation, and tool development. Ensure on-time and quality delivery of engineering work products. Basic Qualifications Bachelor s/Master s in Mechanical or Aerospace Engineering. 5 8 years of structural analysis experience using Ansys Workbench. Strong background in fatigue, stress, and vibration analysis. Skilled in classical calculations and report writing. Preferred Qualifications Experience in hydraulic/electro-mechanical component analysis. Proficiency with Mathcad, Python, or Excel VBA. Familiarity with aerospace material properties and treatment processes. Benefits Transportation & meal vouchers Group life, health, and personal accident insurance 18 days vacation + 12 days contingency leave National Pension Scheme and car lease options Employee scholar program Equal Opportunity Collins Aerospace is an equal opportunity employer and values diversity. All qualified applicants will receive consideration without regard to race, gender, disability, or veteran status. Apply Now Be part of our aerospace revolution. Apply today and help us redefine flight for the future.

Job Title: Senior Software Development Test Engineer Location: Bengaluru, Karnataka, India About Us: Cloud Software Group is one of the world's largest cloud solution providers, serving over 100 million users globally. As part of Cloud Software Group, Citrix is a recognized leader in VDI, Desktop-as-a-Service, and application delivery solutions, enabling the secure delivery of desktops, applications, SaaS, and web apps to any device, anywhere. Our Citrix Workspace App team works on the secure delivery of virtual apps, and we re dedicated to improving the experiences of our users worldwide. About This Team: Our Citrix Workspace App team is responsible for the secure delivery of virtual apps to users across multiple platforms. We are looking for a Senior Software Development Test Engineer who is passionate about quality assurance, automation, and continuous improvement. You will play a critical role in testing and validating the Citrix Workspace App, focusing on automating tests using tools like Selenium, Python, and the Robot Framework. You'll work in a fast-paced environment, collaborating closely with developers, product managers, and other stakeholders to ensure the product meets high standards of reliability and performance. Job Description: As a Senior Software Development Test Engineer, you will be responsible for designing, developing, and maintaining automated test frameworks and scripts for web-based software applications. Your work will be central to the success of our Citrix Workspace App by improving test efficiency, coverage, and reliability. You ll ensure that the application is of the highest quality by performing various types of testing, including functional, regression, performance, security, and integration testing. Duties and Responsibilities: Automate Testing: Develop and maintain automated test frameworks and scripts using tools like Selenium, Robot Framework, Python, PowerShell, and others. Test Automation: Automate UI, API, and integration tests to improve efficiency and coverage. Champion Automation: Advocate and implement best practices for automation testing within the team. Test Planning and Execution: Design, develop, and execute comprehensive test plans and test cases for web-based software applications. Collaborate Effectively: Work with developers, product managers, and other stakeholders to deliver high-quality products in a team-oriented environment. Self-Motivation and Independence: Demonstrate strong self-motivation, with the ability to work effectively in a team environment while being able to operate independently with limited supervision. Required Experience/Skills: 5+ years of experience in Automation Testing for web-based applications, including test frameworks and scripting languages. Strong hands-on experience in test automation frameworks and tools such as Python, Shell, Selenium, Robot Framework, PowerShell, JavaScript, CSS, HTML. Familiarity with cloud platforms such as AWS, Azure, and GCP, and understanding related technologies. Basic networking knowledge, including network troubleshooting using tools like Wireshark. Experience with CI/CD tools such as GIT, Jenkins, and JIRA. Excellent communication and articulation skills to collaborate across teams and document testing efforts. Preferred Qualifications: B.E/B.Tech or M.Tech in Computer Science or a related technical field. Innovative Culture: Be part of a leading organization at the forefront of cloud technologies. Impactful Work: Your work will directly impact the performance and quality of our Citrix Workspace App, which serves millions of users. Growth Opportunities: Join a rapidly growing team where you can continue to develop and expand your technical and leadership skills. Work with Cutting-Edge Tech: Use state-of-the-art testing tools and methodologies to ensure the highest quality of cloud-based software. Equal Opportunity Employer: Cloud Software Group is an Equal Employment Opportunity (EEO) employer and complies with all federal, state, and local laws prohibiting employment discrimination. We encourage applicants of all backgrounds to apply and offer a welcoming, inclusive workplace where everyone can succeed. Qualification : B.E/B.Tech or M.Tech in Computer Science or a related technical field.

Full-Stack Developer - Windows on Snapdragon Platform Team Company Qualcomm India Private Limited Job Area Engineering Group > Software Engineering General Summary Qualcomm Technologies Inc., the maker of the industry-leading Snapdragon SoCs, is the largest provider of complete chipset solutions for Microsoft Windows on Snapdragon products. Qualcomm is committed to developing solutions for the next generation of Windows on Snapdragon devices. The ideal software engineer will act as a key member of an Agile Scrum Team and play a pivotal role in the end-to-end lifecycle of all Windows-on-Snapdragon product lines. This role requires strong software development skills to act as a hands-on contributor responsible for gathering requirements, designing, and developing improvements to the Windows-on-Snapdragon continuous integration build systems, software release process, and developer operations tools. Strong communication and collaboration skills are essential, as this platform team works closely with internal and external teams to bring up, support, triage, and resolve issues on Qualcomm chipsets. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master s degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Languages such as C, C++, Java, Python, etc. Key Responsibilities Design, develop, test, and maintain web applications using Python and C#. Implement front-end interfaces using ASP.net, HTML, CSS, and JavaScript. Design and maintain SQL databases, writing efficient SQL queries. Develop and maintain automation scripts using PowerShell, CMD, and BAT. Work within version control systems such as Git and Perforce. Contribute to embedded Windows software development with solid programming skills. Apply strong understanding of Operating System concepts, both Windows and Linux. Participate in Windows and/or Linux kernel development activities. Preferred Qualifications 2-5 years of Software Engineering or related work experience. Proficiency in Python, C/C++/C#, SQL, and Shell Scripting. Strong communication and interpersonal skills. Effective problem-solving and debugging capabilities. Experience with Windows OS internals. Experience debugging device drivers using WinDbg, JTAG, or similar tools. Basic understanding of processor architecture and cache subsystems. Experience with PC software development (System BIOS, UEFI, ACPI, Drivers, Applications). Working knowledge of Jenkins and Artifactory. Hands-on experience with Windows program/driver development. Proficiency in Visual Studio as an integrated development environment. Exposure to ARM assembly. Basic understanding of Embedded OS (Kernel architecture, OS services, heap, memory management, multi-core processing, multi-threading, and crash debugging). Strong motivation and ability to learn quickly. Equal Opportunity Employer Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email [email protected] or call Qualcomm s toll-free number listed on their careers page. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities during the hiring process. (Please note: this email address is intended solely for accommodation requests. Qualcomm will not respond to requests for application status updates or resume inquiries through this contact.) Recruitment Policy Qualcomm s Careers Site is exclusively for individuals seeking employment directly with Qualcomm. Staffing agencies and third-party recruiters are not authorized to submit profiles, applications, or resumes via this site. Any such submissions will be considered unsolicited, and Qualcomm will not be responsible for any associated fees. Compliance Notice All Qualcomm employees must adhere to applicable company policies and procedures, including but not limited to those regarding security, confidentiality, and protection of proprietary information, in compliance with applicable laws.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Minimum Qualifications: Bachelor s degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. At least 5 years of experience in software development, specifically within consumer electronics or embedded systems. A minimum of 3 years of experience in leading ASIC architecture decisions from a software perspective. Proficiency with Linux kernel, bootloaders, SoC, low-power management frameworks, or performance analysis. Preferred Qualifications: Master s degree or PhD in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or a related discipline. 10 years of experience in software design and development, particularly with software layers in ASIC (e.g., boot processes, drivers, embedded firmware, libraries, and APIs for applications). Familiarity with Android OS or similar platforms, especially in power management. Strong understanding of hardware-software interactions across various hardware blocks, including CPUs and accelerators. About the Role: Join a dynamic, diverse team that is pioneering the development of custom silicon solutions powering the future of Google's direct-to-consumer products. As part of the team, you will contribute to groundbreaking innovations in products used by millions globally, shaping the next generation of hardware experiences for optimal performance, efficiency, and integration. As the ASIC Platform Software Architect, you will be instrumental in translating software product requirements and use cases into specific hardware blocks or sub-systems. In this role, you will define the direction of the software team, guiding them in the face of complex constraints. You will work closely with hardware architects to define system architectures for hardware blocks and collaborate with the implementation team to outline solutions. You ll also help influence design decisions to ensure software requirements are met, negotiating hardware/software trade-offs for optimal results. Google's mission is to organize the world s information and make it universally accessible and useful. Our Devices & Services team integrates the best of Google AI, software, and hardware to create transformative user experiences. We focus on researching, designing, and developing new technologies and hardware to make user interaction with computing faster, more seamless, and more powerful. Whether we re innovating on form factors, advancing sensors, or redefining interaction methods, the Devices & Services team is dedicated to improving people's lives through technology. Responsibilities: Collaborate with stakeholders to identify user experience needs and map them to hardware and software solutions. Design architectures and software interfaces that empower developers to leverage hardware accelerators and other intellectual property (IP). Analyze hardware component interactions, troubleshoot issues, propose trade-off solutions, and drive to resolution. Contribute to the design and improvement of hardware from one generation to the next, applying insights from past productization efforts and reducing technical debt.

General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.

Job Function: As part of the Wireless R&D HW team in Bangalore, the candidate will contribute to the design and development of next-generation WLAN and micro-Wi-Fi subsystems for connectivity solutions in IoT, hearables, and wearables. This includes: Architecture and micro-architecture development. RTL design and integration. Collaboration with cross-functional teams for design convergence. Responsibilities: Develop micro-architecture and implement design using Verilog/SystemVerilog. Execute digital design (RTL) for complex WLAN subsystems involving multiple clock domains and low-power designs. Integrate and deliver WLAN subsystems to SoC-level designs. Collaborate with verification, SoC design, validation, synthesis, and physical design (PD) teams. Perform tasks such as linting (Spyglass), CDC analysis, synthesis, and simulation. Conduct RTL integration and work closely with DFT and PD teams for design-to-GDS convergence. Analyze tool reports (RDC, CLP, CDC, PrimeTime) and ensure compliance with design standards. Contribute to post-silicon debug and validation, when required. Maintain effective communication with global multi-site teams (US, UK, and India). Create and maintain documentation for design and development processes. Skills and Experience: ASIC Front-End Design: 8+ years of experience in digital ASIC design, with expertise in RTL coding using Verilog, VHDL, or SystemVerilog. Clock Domain Crossing (CDC): Strong experience in handling multiple clock domains and low-power design methodologies. Tool Proficiency: Hands-on experience with Spyglass Lint/CDC checks, DC-Compiler, PrimeTime, synthesis, simulation, etc. Protocols: Familiarity with AHB, AXI, and other standard bus protocols. WLAN/Wireless IP Expertise: Experience in 802.11/Wi-Fi subsystems is a plus. Debugging: Exposure to post-silicon debug and validation is desirable. Collaboration: Ability to work closely with multi-disciplinary teams for holistic design and development. Documentation: Strong documentation and communication skills. Minimum Qualifications: Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related fields and 3+ years of relevant experience. OR Master s degree in the same fields and 2+ years of experience. OR Ph.D. and 1+ year of experience. Experience Requirements: Strong background in ASIC front-end design, architecture, and RTL integration. Prior experience in WLAN IP/Sub-system design is a significant advantage. Why Join Qualcomm? Work on cutting-edge technologies like Wi-Fi 6/7/8 and next-gen connectivity solutions. Collaborate with diverse teams across geographies. Opportunity to contribute to groundbreaking innovations shaping the future of connectivity. Be part of an inclusive and forward-thinking culture. Qualification : Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communcations or related field.