Asic LOW Power Design Engineer Jobs in Bengaluru

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Electrical Principal Engineer FPGA Team Location: Bengaluru, India Team: Electrical Engineering Company: Dell Technologies Role Overview As a Principal Electrical Engineer, you will contribute to the architecture, design, and validation of FPGA-based hardware systems for Dell s next-generation enterprise servers. This role involves working across global teams to deliver robust, scalable, and efficient PCBA (Printed Circuit Board Assembly) and logic solutions that align with industry standards and internal requirements. Key Responsibilities Architect and design next-gen hardware features in collaboration with front-end teams and partners. Analyze and recommend trade-offs in design features and costs. Guide global teams with best practices in electronic hardware design. Own and deliver system interfaces and support cross-functional development efforts. Create comprehensive documentation for testing and validation. Essential Requirements 8 12 years of experience in FPGA hardware verification using Verilog, SystemVerilog, VHDL. Expertise in UVM, ABV (Assertion-Based Verification), code coverage, and unit-level simulation. Knowledge in digital design methodologies: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Static timing analysis Experience with x86 or ARM architectures. Familiarity with peripheral protocols: I2C, I3C, SMBus, IPMI, IPMB. Strong background in both analog and digital design. Understanding of hardware/software co-design and debugging complex systems. Desirable Qualifications Experience with Intel/AMD x86 and ARM-based systems. Hands-on with FPGA tools: Xilinx, Lattice, Altera Quartus, ModelSim/QuestaSim. Passion for mentoring and knowledge sharing. Dell Technologies offers a collaborative and innovative environment where hardware engineers work at the forefront of industry advancements. You'll be empowered to lead cutting-edge hardware projects, influence product design, and make a lasting impact on the future of enterprise technology.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

We are looking for a System Software Architect Programmable Vision Accelerator. As the market leader in deep learning and parallel computing, NVIDIA is seeking an expert system software architect to lead the design and implementation of firmware and driver stack for NVIDIA's Programmable Vision Accelerator (PVA) engine in the Tegra SoC platform. As a Software Architect, you will join a team of software engineers to create and evolve an essential part of the software stack responsible for scheduling and execution of highly optimized computer vision and machine learning kernels for specialized DSP hardware. You will use your design abilities, coding expertise, and creativity to help deliver innovative real-time firmware and kernel mode drivers for a low power, high performance computer vision accelerator engine. You will be architecting and developing new features and improvements to realize the groundbreaking potential of NVIDIA mobile systems, ranging from self-driving cars, intelligent video analytics and autonomous mobile robotics. You will need to demonstrate excellent technical leadership, communication, interpersonal, and analytical skills as well as a real passion for performance-oriented software engineering. If this sounds like a fun challenge, we want to hear from you! What you will be doing: Evolve and define software architecture for future NVIDIA's Programmable Vision Accelerator (PVA) chips and enhance the functionality of currently shipping products. Design and write custom embedded software for PVA engine to meet product and hardware requirements at the SoC level. Help defining forward-looking strategy and improvements to the PVA algorithms and system architecture. Review hardware specifications and map algorithms to the architecture. Participate in the bring-up of the new generation of the world's most advanced SoC. Collaborate closely with other teams and software/hardware architects across NVIDIA to support the architecture, design, creation, integration, and validation of PVA software under a common SoC umbrella. Provide technical support and guidance for internal and external customers. Mentor and guide technical development of the less experienced team members What we need to see: College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience 10+ years of working experience in embedded industry, including 5+ years in technical leadership role Deep understanding of SoC principles, general systems architectures, operating systems, device drivers, memory management, multithreading, and real-time scheduling. Deep understanding and working experience with embedded technologies including DSP, computer vision and image/signal processing. Excellent software development skills (C, C++) and outstanding problem-solving capabilities. Proven expertise in architecting embedded software and development of highly optimized code for DSP, SIMD and/or VLIW processors Experience with embedded Linux and/or QNX. Outstanding interpersonal skills with ability to work in a global and diverse team operating in a fast-paced environment. Good understanding of safety-critical software principles with experience in automotive or other highly regulated industries Ways to stand out from the crowd: Experience with ISO 26262 and IEC 61508 or equivalent quality/safety processes. Understanding of software safety and safety development processes is a major plus. Consistent record to effectively guide and influence in a technically strong dynamic environment. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking people in the world working for us. If you're creative and autonomous, we want to hear from you. NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. NVIDIA is looking for great people like you to help us accelerate the next wave of artificial intelligence. Qualification : College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology and amazing people. We seek a Senior Power and Thermal Engineer to join our dynamic and fast-paced Silicon Solution Group. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers a unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working, and creative individual to architect and productize next generation power and performance controllers. What You Will Be Doing: Responsible for architecting, developing, characterization of next generation power and thermal management features and solutions working with multi-functional teams across the company. Drive methodologies for deployment of features into products. Drive initiatives for power and thermal optimizations spanning across silicon, platform, software, manufacturing, and product systems; for products ranging from largescale datacenters to low-power client devices. Debug and architect solutions for issues seen by customers in the field across a wide range of industries. Influence next generation SW, chip, board, and platform design of products across SOC, GPU and CPUs in Laptops, Servers, and Datacenters Work alongside system architects, designers, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations, in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market. What We Need to See: B. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience) 4+ years of experience in silicon bring-up, validation, and productization. Experience with power and thermal controllers and management. Expertise and deep understanding in the areas of silicon power, transistor/device physics, power modeling and measurement, active power management is a plus Proficiency in Python, Perl or C programming languages. Self-starter with strong skills in multi-tasking, influencing, communication, presentation, and consensus-building Enthusiastic, responsive, and keen on process improvement With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Qualification : B. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience)

About the Job Join a diverse team that pushes boundaries by developing custom silicon solutions powering the future of Google's direct-to-consumer products. Contribute to the innovation behind products loved by millions worldwide and help shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team blends the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies to make computing faster, seamless, and more powerful, ultimately improving people s lives through technology. Responsibilities Define ASIC power management architecture for an SoC, including image compute, CPU/GPU functions, ensuring maximum performance under power and thermal constraints. Prototype firmware and validate the next-generation SoC power management system at various design stages. Analyze implementation and models, and test the performance of power management solutions. Produce detailed documentation on the proposed power management implementation and conduct trade-off analyses for engineering reviews and product roadmap decisions. Collaborate with software teams and the power architecture team to build system-level designs and methods for optimized power management. Minimum Qualifications Bachelor s degree in Electrical Engineering or equivalent practical experience. 8 years of experience in power management or post-silicon measurements and validation. 3 years of experience with power management validation. Preferred Qualifications Master s degree or PhD in Electronics, Computer Engineering, or Computer Science, with an emphasis on computer architecture and performance/power analysis. Solid knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation strategies. Strong understanding of how software and architectural design decisions affect the power and thermal behavior of systems, including thermal mitigation, scheduling, and cross-layer policy design.

General Summary: Qualcomm is the industry leader in integrated chipsets that power advanced mobile devices. We are expanding our expertise in wireless technologies and advanced multimedia capabilities to continue delivering high-performance multimedia systems with low power consumption and competitive cost, while maintaining strong feature differentiation. Join Qualcomm India s Multimedia Systems Team and work at the cutting edge of performance modeling, system architecture, and evaluation of camera, video, and computer vision hardware IPs. This role offers the chance to collaborate on image signal processors (ISP), video codec hardware, and advanced algorithms for computer vision and image/video processing. Key Responsibilities: As part of the Systems and R&D team, your responsibilities may include the following: Design and maintain transaction-accurate/static models for multimedia IPs. Perform performance validation and debugging for pre- and post-silicon platforms. Conduct architecture analysis for system performance optimization. Define use-case flows for multimedia applications. Understand product features and assess their impact on system performance. Collaborate with the product marketing team to recommend feature support configurations for specific system setups. Minimum Qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or a related field with 4+ years of relevant experience, or Master s degree with 3+ years of experience. Strong analytical and problem-solving skills with implementation experience. Solid understanding of SoC infrastructure (NoC, Memory Controller, DDR, QoS, MMU). Systems mindset with a focus on power and performance optimization. Experience in performance modeling/verification and debugging system performance issues. Proficiency in C, SystemC, and familiarity with UNIX/Win/Linux computing platforms. Preferred Qualifications: Background in system architecture, hardware IP micro-architecture, or embedded software/firmware. Experience in image/video signal processing. Knowledge of image sensor technology and codec standards. Educational Requirements: Required: Bachelor s degree in Computer Science or Electrical & Computer Engineering. Preferred: Master s degree in a related field. Qualification : Bachelors in Computer science or Electrica

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs Participates in the definition of architecture and microarchitecture features of the block being designed Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features Supports SoC customers to ensure high quality integration and verification of the IP block Drives quality assurance compliance for smooth IP SoC handoff Qualifications Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components Knowledge of Power management is preferred. Experience with formal apps would be good. Expertise in Verilog and System Verilog-based logic design. Expertise in Verilog and System Verilog-based logic design Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must Knowledge of considerations for performance, power, and cost optimization is desirable. Knowledge of formal property verification using Jasper is preferred Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills Set aggressive goals and meet/beat the commitments Flexible enough to work in a dynamic environment and multitask seamlessly. Ability to work independently and in a team Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience

Job Description The Client DDRPHY team is looking for an energetic and passionate Logic Methodology Engineer who conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the logic/RTL design of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Defines methodologies that produce enhancements in power, performance, and area for designs on the new architectures and process technology nodes and aids high-speed digital design targeted towards low power optimized IP implementations. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing logic/RTL related TFM. Works closely with the logic design teams to create and enhance logic design methodologies that enable fast design convergence and facilitate seamless integration. You will be responsible for setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams. The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.Objectives of the position Own and deliver TFM flows which aid in the logic design of Mixed Signal IP Continuously drive the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements Drive area/power of IPs and come up with improvements on IP Area/Power metrics Critical Decision making on Technical issues. Qualifications The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience. Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation. Experience in the following areas/ skills are desired: Strong communicator Self-starter with a penchant for creative problem solving through quick thinking Good aptitude for automation Git/Perforce/CVS know how Perl/Python/TCL Spyglass Lint, CDC, DFT, VCLP, Open Latch Multiple clock domain design Synthesis and speed path debug Below experience is desirable, but not a must: Logic design using System Verilog Low-power design using UPF and clock gating State machine design Simulation and debug experience using VCS/Verdi Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience.

Job Description Develops and executes strategies for connection and purchase of energy and utilities services, as well as identify business opportunity to cut down cost and mitigate risks through innovation and collaboration. Maintains an advanced knowledge of the energy industry and regulatory practices to obtain reliable supply solutions and develop competitive pricing structure and rate mechanism. Leverages and applies strong understanding of contracting and negotiating, tariff design, risk mitigation, renewables, regulatory policy and market rules and supplier relationship management particularly with monopoly utilities, regulatory agencies including energy services and solutions provider to manage relationships and provide predictable cost, quality, availability, and sustainable supply chain technology solutions with adherence to procurement policies. Owns relationships and coordinates purchasing activities with cross functional teams to secure capacities in a cost effective and timely manner. Ensures that supply strategies meets the business demand, quality and cost expectations. Works closely with internal and external stakeholders to advocate rate design structure, supply configuration designs to meet desired capability for serving the demand and fulfil the business objective. Works with internal teams for creation of supply chain solutions to influence cost and provide insight on future trends and potential risk impacts. Conducts periodic executive reviews of energy sourcing strategy in partnership with internal teams and suppliers to shape strategic business objectives and influence investment decision through aligned roadmaps. Leads energy sustainability and build strategies to assess market opportunities that will help corporate to achieve renewable energy goal across global operations. Work with consultants and market research agencies to mitigate pricing risks for qualification and selection of renewable PPAs. Collaborate with cross functional team to drive capacity needs, understand energy market, regulatory process and define cost reduction roadmaps and decarbonization solutions through detailed understanding of financial targets, business objectives, and margins. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Bachelor or post graduate degree in the Engineering, Science or Supply Chain Management or professional experience in energy or utility industry. Minimum 5 years of relevant procurement experience in energy related business and utility industry experience in the Asia regions covering Malaysia, China and Vietnam is essential. Experience in category strategy management and managing complex contract and execution strategies to achieve cost advantage. Indepth, understanding of the regulatory policy and market rules across the region for the generation and supply of energy and water services. Collaborate with internal team for site selection support and gap assessment activities for infrastructure capacity development. Ability to adapt to market dynamics and drive complex energy transactions. A self-starter with strong leadership skills, making decision that shape the path to success. Preferred Qualifications: Experience interacting with relevant state/federal government agencies, officials and representatives from utilities in Asian countries to build unique strategies for delivering results. Understanding of technology evolution, market trends and data analytics is desired. Experience in delivering advanced sustainability program and framework through efficient and low emission technology solutions. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Qualification : Bachelor or post graduate degree in the Engineering, Science or Supply Chain Management or professional experience in energy or utility industry.