Asic Verification Engineer Jobs in Bengaluru

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience in micro architecture and requirements/implementation for automotive designs (focused on functional safety) and their Safety Analysis work products like concept FMEDA, DFA, DFMEA, FTA, FMEDA, etc. including FuSa compliant IP development and third-party IP compliance/deliverables/DIA. Responsibilities shall include the following: Developing a system level safety concepts and requirements for ADAS and IVI use cases with customer implementations in mind and to integrate Qualcomm s hardware in leading Automotive OEM and Tier 1 safety critical systems. Work in collaboration with 3rd party, Customer, and Automotive Stack suppliers, Hardware component suppliers (PMIC, DRAM, Sensor, etc) to ensure all aligned customer system level requirements are met Work with IP and SoC teams on the implementation of Technical Safety Concepts (TSCs) on Qualcomm s Snapdragon automotive hardware. Work with various technology teams on architectural features that would enable targeted safety levels (ASIL B to ASIL D, depending upon the technology team and system level requirements) to meet customer targets Conducting safety analyses, both quantitative and qualitative, fault campaigns on automotive hardware designs and identify areas of improvement. Responsibilities will include leading functional safety related activities for SoC development and ensure ISO 26262 compliance with respect to SoC architecture, development processes and work products. Work closely with SoC Design and IP teams, Software team, Quality teams, the functional safety manager(s) as well as customers to ensure the functional safety process is executed and documented. Working with vendors and partners to ensure functional safety requirements are fulfilled by the components that they provide Work with internal and external functional safety assessors to ensure compliance with ISO 26262 Create functional safety collateral for customers viz. Functional Safety Manual, Safety Analyses Reports, dedicated application notes etc. Supporting customer assessments of our safety features and recommending HW and SW based solutions that meet overall system targets. Working closely with customers and supporting them on various functional safety related aspects Minimum Qualifications Bachelor s degree in engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering, SoC Integration, Verification, or related work experience. Collaborative work experience with good communication skills involving customers, vendors, and internal development teams. Structured problem-solving capability and ability to work with teams on root cause analyses. Preferred Qualifications 5+ years Automotive experience and familiarity with Safety work products, experience with Functional Safety Hardware and/or Software development in semiconductor industry meeting IS0 26262/ IEC 61508 standards. Prior automotive experience in ADAS and self-driving systems preferred. System level Functional safety analysis experience on Hardware/Software components integration preferred SoC/IP integration or verification with good understanding of SoC Architecture and IP design experience preferred Requirements Management Tools and establishing traceability for functional safety requirements e.g. DOORS, etc. Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) is required experience using tools to perform FMEA, FTA preferred Familiarity with hardware failure rate calculation (FMEDA) experience using Siemens 29500 and/or IEC 62380 preferred Relevant Safety Certification is desired e.g. CFSE, CFSP Qualification : Bachelors degree in engineering, Information Systems, Computer Science, or related field.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Emulation Engineer Company Arm Location Bengaluru, India Job Overview Arm s Central Emulation team is excited to welcome experienced Emulation experts to join the team in Bengaluru. You will collaborate with design and verification engineers across the UK, US, India, and France to support advanced Compute Subsystems and SoC projects. Arm is building a team to develop exceptional silicon demonstrators based on Arm s IP compute sub-system solutions, targeting premium mobile, infrastructure, and automotive markets. Using the latest technology nodes (e.g., 3nm) and new 3D packaging innovations, Arm s goal is to demonstrate industry-leading performance by architecting, designing, implementing, and fabricating cutting-edge silicon test chips. This initiative brings together innovative talent and expertise from across the semiconductor industry to shape the next generation of compute on Arm devices. Responsibilities Collaborate with end users to understand system use cases and guide validation efforts. Ensure tight integration between hardware qualification and final application use models. Work in an exciting emulation environment using hybrid and virtual solutions, integrating industry-standard high/low-speed IO IPs into subsystems and SoCs. Engage from early architecture and design phases to pre-silicon validation and post-silicon validation on emulation platforms. Drive pre-silicon emulation across all SoC teams. Ensure design quality and debuggability by collaborating closely with the design team. Support architecture, verification, system validation, performance, power, and DFT teams with insights from performance and power characterization. Develop comprehensive pre and post-silicon test plans in collaboration with verification teams. Develop tests, create bare-metal drivers for industry-standard IO IPs, and build frameworks to enable scalable testing across multiple ASIC projects. Required Skills and Experience Bachelor s degree (BE/BTech) in Electronics Engineering. 8+ years of experience in Pre-Silicon Validation and Emulation/FPGA-based platforms. Experience developing C/C++/SystemC tests for HDL-HVL co-emulation platforms. Proficiency in IO bus protocols such as I2C, SPI, USB, and/or PCIe. Experience with SoC debugging tools such as JTAG and Trace32. Nice-to-Have Skills and Experience Knowledge of ASIC design and prototyping flows. Experience with SystemC/C/C++ and UVM/SystemVerilog (SV) verification languages. Familiarity with domains such as PCIe, Flash, Memory, CPU, GPU, and DRAM. Hands-on experience with emulation toolchains such as Zebu, Veloce, or Palladium. What Arm Offers Arm is committed to global talent acquisition, offering an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace where everyone can thrive, Arm encourages its people to make exceptional contributions to its global success. #LI-KR2 Qualification : Bachelors degree (BE/BTech) in Electronics Engineering.

Job Overview: The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arm s future architecture roadmap. In ATG, we are developing world-leading Secure CPU and System architectures and associated technologies; enabling our ecosystem to build compelling products. Along with the architecture definition, ATG develops products to confirm compliance to the architecture. The ATG team located in Bangalore develops a product called Architecture Compliance Kits (ACK) that are delivered to multiple internal and external CPU design teams to validate that Arm architecture CPU implementations are compliant with the Arm architecture. You will learn Arm Architecture and apply it along with hardware and software verification skills to develop products for verifying the Architecture. You will develop good engineering and technical skills, and a fair understanding of CPU architecture and microarchitecture. You will connect with a wide range of teams within ATG, architects, and with our external partners. In this role, you will also develop solutions for future Arm architecture developments and influence the product offering. Responsibilities: Technical expertise, understanding architecture definitions, carrying out investigations and feasibility studies, defining and developing verification strategies, and contributing to the development of compliance products. Design verification test plans and test cases in assembly, C, HVL, and higher abstraction languages using automation techniques as needed. Strong and continuous communication on deliveries and risks, ensuring that all engineering commitments are delivered successfully. Drive efficiency improvements through adoption of the right development flows and methodologies. Excellent verbal and written communication skills. Required Skills and Experience: B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering. 8+ years of verification experience (CPU/complex IP verification is a plus). Strong understanding of computer architecture. Proficiency in logical programming using C/C++/Assembly with experience in adopting software engineering best practices. Nice To Have Skills and Experience: Experience in CPU verification would be a plus. Knowledge of x86 or Arm processor architecture. We are guided by our core beliefs that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and craft outstanding products and careers. In Return: We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to complex core implementation to full custom physical IPs, here you'll have our backing to push limits in vital areas. #LI-KR2 Qualification : B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering.

Job Title: Pre-Silicon Validation Engineer SoC/IP Job Description: Join the Devices Development Group (DDG), one of Intel s premier System-on-Chip (SoC) design teams, driving innovation in future Intel SoCs and IPs. As a Pre-Silicon Validation Engineer, you will be part of a dynamic team responsible for ensuring the functionality, performance, and reliability of Intel s cutting-edge designs. Key Responsibilities: Validate IP blocks or features at the SoC level, ensuring compliance with design specifications. Develop validation plans and test strategies based on architectural specifications, RTL code, and existing test methodologies. Analyze microarchitecture and debug failures to identify root causes and improve design quality. Develop and utilize various debugging and validation tools to implement validation plans effectively. Participate in silicon debugging, identifying issues and enhancing testing methodologies for future RTL models. Collaborate with IP providers and internal customers to define, develop, and deliver essential infrastructure while addressing issues identified during execution. Qualifications & Requirements: Educational Qualifications: Bachelor s (B.Tech/BS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 5+ years of experience, OR Master s (M.Tech/MS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 3+ years of experience. Technical Skills & Experience: Minimum 2 years of experience in IP or SoC development, verification, or integration using SystemVerilog and UVM (Universal Verification Methodology). Minimum 2 years of experience in writing validation plans and developing software to execute those plans. Minimum 2 years of experience with object-oriented programming languages. Minimum 2 years of experience working with SystemVerilog and UVM. Minimum 1 year of experience with UNIX/Linux environments. Exposure to Graphics Verification and/or Security Verification is a plus. Preferred Qualifications: Minimum 1 year of experience with computer architecture. Minimum 2 years of experience in validation or testing, particularly in silicon design teams. About the Client Computing Group (CCG): The Client Computing Group (CCG) is at the forefront of Intel s PC product and platform development, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. Through strategic partnerships across the industry, CCG delivers innovative computing experiences that empower users to create, connect, and collaborate. As Intel s largest business unit, CCG drives innovation, scalability, and IP development, helping the company fulfill its mission of enriching lives through technology. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, which includes: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development opportunities to support career growth.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Job Description: We are seeking a highly skilled and experienced CPU Verification Engineer with a focus on ARM and NCC-based ARM architecture. This role requires a deep understanding of CPU microarchitecture, SOC integration, and verification methodologies. The ideal candidate will lead verification efforts, collaborate with cross-functional teams, and mentor junior engineers to ensure high-quality CPU design verification. Key Responsibilities: Lead and execute verification plans for CPU designs based on ARM and NCC-based ARM architecture. Develop and enhance testbenches and verification environments using advanced automation techniques. Collaborate with design and architecture teams to identify and resolve specification gaps, ensuring comprehensive verification coverage. Perform SOC-level verification, including integration and validation of CPU subsystems. Utilize industry-standard verification tools and methodologies such as UVM, SystemVerilog, and simulation/emulation platforms. Mentor and guide junior verification engineers, providing technical leadership and support. Continuously improve verification processes and methodologies to enhance efficiency and effectiveness. Qualifications: Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 8 14 years of experience in CPU verification, with a focus on ARM and NCC-based ARM architecture. Proficiency in verification languages and methodologies, including SystemVerilog, UVM, and scripting languages (Python, Perl, etc.). Strong understanding of CPU microarchitecture, memory hierarchy, and SOC integration. Experience with simulation, emulation, and formal verification tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills, with the ability to work in a collaborative environment. Preferred Qualifications: Experience with low-power design verification and performance verification. Knowledge of hardware security verification techniques. Familiarity with machine learning and AI-based verification approaches. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of hardware engineering or related work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or related field and 1+ year of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Job Description: Arm has excellent opportunities in the Solution Engineering group - which has a charter to develop best-in-class SoCs and compute subsystems using industry-leading Arm IP products. These solutions target different market segments like premium mobile, servers, automotive, and IoT. The pre-silicon verification team in Bangalore is looking for highly-skilled engineers with experience in system validation of SoCs on Emulation platform. Responsibilities: Be part of the verification team, and define the emulation-based stress validation methodology & build verification plans. This will involve closely interacting with multiple cross-site & co-located collaborators like the SoC architects, designers, & DV engineers to come up with the extended stress validation plans for the product. Work on multiple industry-standard emulation platforms from EDA vendors, and closely collaborate with technology teams to resolve issues with porting the design on these platforms, and to improve Arm's validation methodology on emulation Take up the responsibility to identify & enable transactors, traffic exercisers, virtual host devices, and monitors on the emulation platform - which will help effective validation of the SoC design. You will be accountable for planning and developing bare-metal and OS-based test content for system stress and use-case validation targeting multiple product use-cases. The team is responsible to find bugs by enabling validation content on high-speed subsystems like PCIe, Ethernet, USB, etc. and other subsystems like DDR, HBM, UFS, HDMI, MIPI devices, LSIO, etc. on emulation Mentor junior engineers and work as a team to deliver on validation goals. Skills and experience required: 5 to 15 years of proven hands-on experience in SoC/subsystem validation. Emulation-based verification experience is a big plus. Prior knowledge of at least one of the blocks like CPU, PCIe, DDR, Ethernet, DDR, USB, etc. Experience working on industry-standard emulators, and validation using transactors or virtual devices will be a plus C/C++ skills with strong understanding of how software interacts with the SoC, firmware, and hardware components is a requirement. Understanding of OS/Linux, drivers and kernel modules is desired. Expertise on hardware behavioral language (Verilog, SystemVerilog) Knowledge of scripting (e.g. Tcl, Perl, Python etc.) In return: Our offices are amazing places to collaborate. If you are interested, but unsure whether you tick all the boxes, we still would love you to reach out! We are keen to welcome people with versatile skills and experience into Arm! Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Job Overview As a Tools Support & Infrastructure Engineer at Qualcomm, you'll play a vital role in supporting and enhancing the design flows and infrastructure for Qualcomm's Digital Signal Processing (DSP) team. The DSP design team delivers high-performance DSP cores that are integral to Qualcomm's multi-tier SoC roadmap, particularly for mobile applications. This position involves managing DSP design databases, developing automation tools to streamline the verification process, and collaborating with global teams to optimize design efficiency and quality. Key Responsibilities Manage DSP Design Database: Oversee the DSP design database, supporting design and verification teams with infrastructure needs. Build Automation: Create new automation tools to enhance the productivity of design verification teams, making it easier to debug simulation failures. Collaborate with Global Teams: Work with Qualcomm s global DSP design teams (architecture, implementation, post-silicon, and back-end teams) to enhance DSP IP infrastructure. Improve Tool Methodologies: Design and deploy new tool methodologies to continuously improve the quality, efficiency, and effectiveness of design and verification processes. Support Design Flows: Contribute to and improve design flows, ensuring the seamless integration of tools and resources used by design teams. Minimum Qualifications Educational Requirements: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 5+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant work experience. Skills & Experience Programming & Tools Support: 3-10 years of experience in programming, database management, and providing tools support for complex DSP IP designs. Automation Expertise: Extensive experience in building automation tools that improve design and verification processes. Programming Languages: Expertise in C++ and Java. Scripting & Automation: Proficiency with scripting languages and tools such as Perl, Python, Shell, Makefiles, and TCI. Analytical Skills: Strong analytic, programming, and debugging abilities. Object-Oriented Programming (OOP): Deep understanding of OOP concepts. Web Programming: Familiarity with Java for web programming is a plus. Unix Environment: Solid understanding of the Unix environment. Digital Design Flows: Knowledge of digital design flows is a plus. Communication: Excellent interpersonal and communication skills, with the ability to work collaboratively with global teams.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Overview: In this role the Associate Engineer will actively participate in the development of test software and create test engineering artifacts. Position: Associate Engineer (P1)- C-sharp Primary Responsibilities: Developing C-sharp .NET solutions to support test engineering applications. Good understanding of driver development, DLLs creation and handling managed and un-managed code. Integrating individual software modules into workable test systems. Revising, Refactoring, Debugging and Maintaining software projects using C-sharp and other .Net libraries. Develop verification and validation procedures for test software to ensure system will perform as specified to meet customer and system requirements. Skill Sets: A minimum of 2 years of experience as a software programmer or developer Skill for writing reusable C-sharp / C++ / CVI libraries using Microsoft Visual studio or similar IDE s. Knowledge in communication protocols like Serial, Ethernet and ARINC Experience in usage of tools for configuration control, MS OFFICE Hands on experience on various test and measurement equipment like NI hardware, third party Data Acquisition Systems, DSO, DMM, Analyzer, signal generators etc is an added advantage. Hand on experience with NI TestStand /NI LabVIEW and /or Certification is an added advantage. Very good communications skills. Basic Qualifications: Qualification: - BE / B-Tech / ME / M-Tech Electrical/ Electronics/Instrumentation Engineering Desired Experience: 2-4 Years Collins Aerospace, a Raytheon Technologies company, is a leader in technologically advanced and intelligent solutions for the global aerospace and defense industry. Collins Aerospace has the capabilities, comprehensive portfolio, and expertise to solve customers toughest challenges and to meet the demands of a rapidly evolving global market. Our Advanced Structures team leverages advanced materials and additive manufacturing to develop complex interior and exterior solutions. These solutions ensure structural integrity of the aircraft, help aircraft take off and land, stay trim in the air, move forward, carry cargo and conduct rescues. We delight our customers with superior products and best-in-class service. Our global team is committed to continuous improvement we work hard to make our solutions lighter-weight, stronger and more technically advanced, so that plane travel can be safer, more affordable and more sustainable in the years to come. We are looking for the best and brightest to fly and land with us! Please ensure the role type (defined below) is appropriate for your needs before applying to this role. (Select One) Onsite: Employees who are working in Onsite roles will work primarily onsite. This includes all production and maintenance employees, as they are essential to the development of our products. Hybrid: Employees who are working in Hybrid roles will work regularly both onsite and offsite. Ratio of time working onsite will be determined in partnership with your leader. Remote: Employees who are working in Remote roles will work primarily offsite (from home). An employee may be expected to travel to the site location as needed. Qualification : BE / B-Tech / ME / M-Tech Electrical/ Electronics/Instrumentation Engineering

Overview: Collins Aerospace is looking for a talented Software Verification Lead Engineer to join the Navigation and Advanced Technology team. In this role, you will be responsible for performing validation and verification for critical avionics systems, focusing on protocols and applications like Maintenance, OMS, and Dataload. You will collaborate with senior developers and architects to design scalable, extensible, and sustainable solutions, while ensuring the highest standards of quality and performance. Primary Responsibilities: Avionics DAL A Product Verification: Verify avionics products in the CNS (Communication, Navigation, and Surveillance) domain, ensuring compliance with industry standards and customer requirements. Tool Development & Test Design: Develop common supporting tools necessary for development and verification activities, as well as create validation tests for avionics systems. Collaboration with Cross-functional Teams: Work closely with architects and senior developers to create scalable solutions, ensuring that new technologies are effectively integrated into the system architecture. CI/CD Pipeline Management: Build CI/CD pipelines and collaborate with the DevOps team to ensure streamlined deployments. Troubleshoot and resolve build issues while supporting deployment processes. Basic Qualifications: Education: BE/B.Tech/ME/M.Tech in Engineering. Experience: 6-8 years of experience in avionics systems and software development. Technical Skills: Proficiency in Python, C/C++, and Matlab/Simulink. Strong understanding of Avionics Systems/Software Architecture, including CNS, FMS, FCS, or Displays. Familiarity with DO-178B/C software standards. Avionics Domain Knowledge: Experience in Communication, Navigation, and Surveillance systems, including protocols for voice and data communications, satellite-based navigation, weather detection, traffic awareness, and collision avoidance. About Collins Aerospace: Collins Aerospace, a Raytheon Technologies company, is a global leader in aerospace and defense solutions. We offer advanced technology and services across a wide array of civil, military, and government missions. Our products are integral to the safety and efficiency of modern aviation, from emergency power systems to reliable cabin controls and quieter engines. Joining our team means being part of a mission-driven company that innovates every day to deliver safer, smarter, and more efficient aerospace systems. Collins Aerospace Diversity & Inclusion Statement: Diversity drives innovation, and inclusion drives success. At Collins Aerospace, we foster a culture that values diversity of thought and experience, which enables us to tackle the toughest challenges in our industry. We are committed to ensuring all employees have the opportunity to share their ideas and passions, paving the way for limitless possibilities. Benefits Package: Insurance: Group Term Life Insurance, Group Health Insurance, Group Personal Accident Insurance. Leave Entitlements: 18 days of vacation and 12 days of contingency leave annually. Employee Programs & Work-life Balance: Employee Scholar Program, work-life balance initiatives, car lease program, National Pension Scheme, Leave Travel Allowance (LTA), and meal vouchers. Additional Benefits: Fuel and maintenance/driver wages, and more! Ethical & Safety Commitment: Collins Aerospace prioritizes strong ethical practices and safety. All positions in India require a background check, which may include a drug screen (for operations positions). Why Collins Aerospace? At Collins Aerospace, we are redefining aerospace. Join our team and be part of a company that plays a critical role in modern flight, providing innovative solutions that enhance safety, efficiency, and the travel experience for millions of passengers worldwide. Qualification : BE/B.Tech/ME/M.Tech with Understanding of Avionics Systems/Software Architecture CNS, FMS, FCS or Displays.

General Summary: Qualcomm is a company of inventors that has unlocked 5G, ushering in an era of rapid acceleration in connectivity and new possibilities across industries. But this is just the beginning. Qualcomm thrives on innovation and diversity, with teams made up of inventive minds from different backgrounds and cultures, all working together to transform cutting-edge technologies into world-changing products. As a GPU Functional Verification Engineer at Qualcomm, your responsibilities will involve a deep understanding of 3D Graphics hardware pipelines, feature sets, data paths, and block functionalities. You will play a key role in designing and developing verification strategies, implementing testbenches, and working on the functional verification of Qualcomm s Snapdragon SoC products. Key Responsibilities: Develop deep expertise in the 3D Graphics hardware pipeline, including feature sets, data paths, and block functionalities. Strategize, brainstorm, and propose Design Verification (DV) environments; develop testbenches and own test plans. Debug all RTL artifacts and work to achieve comprehensive signoff matrices. Collaborate with EDA vendors and explore innovative DV methodologies to push the limits of signoff quality. Partner with architecture, design, and systems teams globally to meet and exceed all project goals. Develop and execute UVM-based System Verilog testbenches for functional verification of complex GPU designs. Engage in property-based formal verification (knowledge of formal tools is a plus). Work on subsystem-level testbenches to analyze GPU workloads and ensure compliance. Utilize emulation platforms to analyze performance and identify potential pipeline bottlenecks. Perform power-aware and gate-level simulations to ensure high-quality GPU implementation. Implement Perl/Python scripts for regression management, optimizing runtimes, managing databases, and tracking bugs. Required Skills and Experience: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, or a related field, and 2+ years of relevant experience in Hardware Engineering or Design Verification. Master s degree in a related field and 1+ year of relevant work experience, OR PhD in a related field. Minimum 3 years of experience in design verification. Strong proficiency with UVM-based System Verilog testbenches. Experience with GPU pipeline design is a plus but not mandatory. Working knowledge of property-based formal verification tools is a plus. Strong communication skills (both written and verbal) with the ability to work in a collaborative team environment. Ability to learn quickly and deliver results with high quality. Desirable Skills and Aptitudes: Experience in GPU functional verification and knowledge of 3D graphics hardware pipelines. Familiarity with emulation platforms and the ability to analyze and address performance bottlenecks. Expertise in scripting with Perl and Python for automation and optimizing verification processes. Education Requirements: Bachelor s (BE/ME) or Master s (M.Sc.) degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or equivalent courses from reputed universities. Why Qualcomm? Be a part of a passionate GPU HW team dedicated to developing industry-leading Qualcomm Snapdragon SoCs. Play a pivotal role in shaping the future of mobile AR/VR by contributing to GPU solutions that drive benchmarks in the mobile computing industry. Qualification : Bachelors (BE/ME) or Masters (M.Sc.) degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or equivalent courses from reputed universities.