Atpg Automatic Test Pattern Generation Jobs in Bengaluru

Sr. Enterprise Applications Developer Location: Bengaluru Team: Tech Ops Engineering Experience Required: 5+ Years About Aviatrix: Aviatrix is a cloud network security leader trusted by 500+ global enterprises. We provide the power, control, and security needed to modernize cloud strategies, ensuring organizations are ready for the future of AI-driven cloud networking. The Role: Engineering for Business Excellence As a Sr. Enterprise Applications Developer, you will join our Tech Ops team to architect secure, scalable, and reliable internal applications. You will work with serverless architectures and LLM-powered tools to support critical business functions and solve complex technical challenges. Technical Stack & Expertise Core Technologies: Serverless Mastery: Hands-on experience with AWS Lambda and AWS Step Functions. Backend & Scripting: Proficient in Node.js and Python. Frontend & Data: Skilled in React for UI development and Postgres for database management. Multi-Cloud: Familiarity with AWS, Azure, and GCP platforms. Engineering Competencies: Architecture: Strong understanding of Distributed Systems and API Design. AI Workflow: Ability to leverage AI/LLM tools for code generation, test automation, and architecture exploration. Security: Experience with SSO integrations and secure authentication solutions. Operations: Familiarity with DevOps, CI/CD, and building IT applications for Sales, Support, or Marketing. Primary Responsibilities Scalable Development: Build internal applications using modern cloud-native patterns. Integration Management: Develop and maintain secure integrations between internal systems and external services. Operational Excellence: Lead code reviews, testing, and debugging to ensure high performance and reliability. Cross-functional Leadership: Partner with IT, Security, and Business stakeholders to align on system requirements. Mentorship: Participate in technical hiring and support the growth of the engineering team. Benefits & Why Aviatrix Total Rewards: Comprehensive pension, private medical, life assurance, and long-term disability. Wellbeing: Annual wellbeing stipend and a generous holiday allowance. Culture of Growth: We value unique career journeys if you are excited by this role, we encourage you to apply even if your background doesn't match every requirement perfectly.

Architect Bengaluru | Engineering | Full-Time About Fam (formerly FamPay) Fam is India s first payments app designed for everyone aged 11 and above. With FamApp, users can make seamless online and offline payments via UPI and FamCard. Our mission is to empower over **250 million young Indians** to start their financial journey early with confidence and awareness. Founded in 2019 by IIT Roorkee alumni, Fam is backed by top-tier investors including Elevation Capital, Y-Combinator, Peak XV (Sequoia Capital India), Venture Highway, and angels such as Kunal Shah and Amrish Rao. About This Role We re seeking a **high-impact Architect** to join Fam s engineering leadership team. In this role, you will **own and evolve the backend architecture** powering our core product experiences. You ll collaborate closely with founders, product managers, and engineering leaders to build backend systems that enable rapid innovation while ensuring **scalability, reliability, and security**. This is more than just designing services you ll **shape how Fam builds products** by establishing frameworks, patterns, and architectural decisions that empower engineers to move fast without sacrificing robustness. If you have **10+ years of experience** building and scaling backend systems for fast-growing products, and the ability to be a force multiplier across multiple teams, we want to hear from you. What You ll Do Define and continuously evolve Fam s backend architecture, including APIs, services, data models, and integrations. Partner with Product and Engineering leads to translate business goals into scalable, reliable backend solutions. Lead architecture for critical product areas like payments, onboarding, user engagement, growth, and monetization. Create frameworks and reusable patterns that accelerate developer velocity, experimentation, and feature rollouts. Make informed trade-offs balancing speed, cost, security, and user experience in system design decisions. Mentor senior engineers and foster strong architectural thinking across teams. Collaborate with infrastructure, data, and security teams to ensure compliance, observability, and cost efficiency. Stay updated on emerging backend technologies, patterns, and best practices. Drive key architecture decisions on build vs. integrate, synchronous vs. asynchronous, schema vs. event-driven models. Must-Haves 10+ years engineering experience, with 3+ years in Staff/Principal Engineer or Architect roles. Proven track record designing and scaling backend systems for high-growth, user-facing products. Deep expertise in API design, distributed systems, and service-oriented architectures. Strong command of backend stacks (Node.js, Java, Go, Python), databases (PostgreSQL, Redis), and messaging/event systems. Experience leading large technical decisions across product teams. **Systems thinker** with a product-first mindset balancing speed, robustness, and user experience. Excellent collaboration and communication skills to align product and engineering stakeholders. Experience in fintech or regulated environments is a plus. Nice to Have Experience working in early-stage or hyper-growth product companies. Familiarity with experimentation frameworks, feature flagging, and rapid iteration at scale. Knowledge of domain-driven design (DDD), event-driven and asynchronous architectures. Experience with real-time systems, payments infrastructure, or growth-focused platforms. Contributions to open source, public talks, or thought leadership in architecture. Lead strategic backend architecture powering fintech innovation for 250M+ Gen Z users. Influence technical direction and engineering culture across the organization. Work with a modern stack on meaningful scale challenges with freedom to innovate. Join a mission-driven company shaping India s first payments product specifically for teens and young adults. Collaborate directly with founders and senior leadership, including Sambhav (Co-founder) and Chirag (Head of Engineering). Backed by world-class investors and surrounded by top-tier talent. Perks That Go Beyond the Paycheck Relocation assistance for a smooth transition. Free office meals (lunch & dinner). Generous leave policies (birthday, period, parental support, and more). Salary advances and loan support programs. Quarterly rewards, recognition, and referral incentives. Access to the latest gadgets and tools. Comprehensive health insurance including mental health support. Tax benefits with food coupons, phone allowances, and leasing options. Retirement benefits: PF contribution, leave encashment, and gratuity. About FamApp FamApp is revolutionizing payments and financial inclusion for the next generation, providing UPI and card payments for users 11 years and older. Our flagship FamX Spending Account integrates UPI and card payments seamlessly, enabling users to manage, save, and learn about money with ease. With over **10 million users**, FamApp is changing how young Indians transact no more carrying cash, plus fully customizable FamX cards with personalized doodles for added fun. Join Our Dynamic Team At Fam, we prioritize people with generous leave policies, flexible work schedules, comprehensive health benefits, and free mental health sessions. You ll work alongside some of the most passionate, talented, and fun professionals in the startup ecosystem.

Principal Associate Full Stack Engineering (GenAI Observability) Location: Bangalore Company: Capital One India About Us At Capital One India, we re tackling some of the most complex problems in financial services using machine learning, advanced analytics, and cloud-first engineering. Our mission is to build cutting-edge, patentable solutions that transform customer experiences, enhance operational efficiency, and ensure robust risk and compliance standards. We re a team of makers, breakers, doers, and disruptors obsessed with turning data into real-world impact at scale. About the Team Machine Learning Experiences (MLX) The MLX team is pioneering the future of model governance, ML observability, and Generative AI infrastructure at Capital One. We re enabling teams to seamlessly deploy ML and GenAI models at scale, with full visibility into performance, health, compliance, and ethical usage. This is the platform powering the next generation of AI-driven financial products across the company. About the Role We re looking for a Principal Associate Full Stack Engineer to lead the development of observability platforms for Generative AI systems. You ll be part of a cross-functional team focused on governance automation, LLM monitoring, and intelligent diagnostics using telemetry data, metadata, and advanced analytics. You ll design systems to collect, analyze, and visualize performance data from our large-scale GenAI infrastructure, helping data scientists and engineers make faster, safer decisions. What You ll Do Lead architecture and development of observability tools and dashboards for monitoring GenAI models and platform health. Design and build core APIs and SDKs to instrument large language models (LLMs) and foundational models (training, fine-tuning, prompting stages). Integrate Generative AI to enable observability features like anomaly detection, predictive analytics, and copilot-assisted troubleshooting. Partner with platform, MLOps, and governance teams to ingest and analyze telemetry, metadata, and runtime metrics at scale. Drive development of tools to ensure compliance with AI ethics, data governance, and industry regulations. Collaborate with product, design, and research to turn complex requirements into scalable, cloud-native software solutions. Lead proof-of-concept initiatives to test and showcase how GenAI can improve platform observability and decision-making. Contribute to the open-source community and stay at the forefront of GenAI and ML infrastructure evolution. Basic Qualifications Bachelor s or Master s degree in Computer Science, Engineering, or related field 4+ years of experience building distributed, data-intensive systems using microservices architecture 4+ years of experience in backend development with Python, Go, or Java 4+ years of expertise with observability stacks (Prometheus, Grafana, ELK) and adapting them for AI systems Strong knowledge of OpenTelemetry, and experience building custom SDKs and APIs 5+ years of hands-on experience with Generative AI models, especially applied to observability, governance, or compliance 2+ years of experience with cloud platforms such as AWS, Azure, or GCP Preferred Qualifications 4+ years building and optimizing ML systems in production environments 3+ years of experience with MLOps tools like MLflow, Kubeflow, or commercial platforms Experience with GenAI frameworks and libraries like LangChain, Haystack, and vector databases (FAISS, Chroma, OpenSearch) Familiarity with emerging observability tools for LLMs such as Langfuse, Phoenix, Helicone, or OpenInference Contributor to open-source GenAI or ML infrastructure projects Author or co-author of published work in AI/ML observability, governance, or performance monitoring Experience with PyTorch, TensorFlow, Spark, or Dask Knowledge of NVIDIA GPU telemetry, CUDA programming, and performance optimization for AI workloads Understanding of AI ethics, data governance, and regulatory frameworks for machine learning systems Why Join Capital One India Work at the intersection of technology, AI, and compliance helping shape the future of responsible AI Join a team driving enterprise-wide adoption of Generative AI Collaborate with world-class engineers, data scientists, and product leaders Enjoy a high-performance culture that encourages innovation, learning, and mentorship Access to cutting-edge tools, open-source contributions, and cloud-native infrastructure Qualification : Bachelors or Masters degree in Computer Science, Engineering, or related field

Job Title: Senior Specialist Software Engineering Location: Bengaluru Type: Full-Time Level: Professional About BetaNXT BetaNXT is powering the next generation of connected wealth management infrastructure. By integrating our proven platforms Beta, Maxit, and Mediant we deliver real-time data solutions that enhance advisor productivity, streamline enterprise operations, and elevate the investor experience. Our platform helps wealth management firms transform their legacy systems into scalable, future-ready solutions that drive differentiation and growth. About the Role We are seeking a Senior Specialist Software Engineering to join our Product Engineering team. This is a key technical leadership role for someone passionate about enterprise integration, legacy modernization, and delivering high-performance, scalable systems. You will work closely with architects, product managers, and cross-functional teams to design and implement critical enhancements across our platform, playing a key role in shaping our strategic initiatives. Key Responsibilities Lead software design & development of complex enterprise components aligned with business and technical goals. Collaborate with Solution Architects to define scalable, maintainable solutions. Provide technical oversight through the software lifecycle design, development, testing, and integration. Define and execute testing strategies: unit, integration, and performance. Drive code quality and reliability through proactive issue resolution and continuous improvement. Create and maintain technical documentation to ensure long-term maintainability. Ensure adherence to development best practices, internal standards, and compliance. Serve as a technical SME and point of contact for assigned domains. Mentor junior engineers, promoting skill development and knowledge sharing. Coordinate with QA, documentation, deployment, and support teams to ensure successful delivery. Participate in project planning, provide effort estimates, and contribute to work breakdown. Communicate effectively with technical and non-technical stakeholders, including senior leadership. Contribute in Agile/SCRUM teams, supporting sprint ceremonies and cross-functional collaboration. Maintain timely updates, raise risks early, and help drive resolution. Required Qualifications & Experience 10+ years of hands-on experience in Enterprise Application Integration and Mainframe Development. Expertise in COBOL, JCL, CICS, DB2, VSAM, and environments like CICS Web Services & Transaction Server 3.1. Proficient in integration technologies: IBM Integration Bus (IIB 10) IBM App Connect Enterprise (ACE 12) MQ Series, IBM DataPower Familiar with mainframe tools: TSO, File-Aid, Syncsort, Platinum, Abend-Aid, Mainview Experience with JCL utilities, ChangeMan, and version control tools like GIT. Skilled in unit testing, code quality, and design documentation. Understanding of performance metrics: CPU usage, response time, network latency, etc. Knowledge of API modeling and annotation tools: Swagger, RAML. Familiarity with XML, XSD, XPath, XQuery, JSON. Experience working in Agile/SCRUM development environments. Strong analytical, communication, and cross-functional collaboration skills. Bachelor s degree in Computer Science, Information Science, or a related field. Master s degree or certifications (e.g., IBM, Agile) are a plus. Join a company transforming the wealth management technology landscape. Work on mission-critical systems that power financial operations at scale. Collaborate with industry leaders and technical experts in a fast-paced environment. Contribute to modernization efforts that directly impact advisor and investor experience. Thrive in a culture that values innovation, integrity, and continuous improvement. Qualification : Bachelors degree in Computer Science, Information Science, or a related field

Gen AI AWS Engineer | Bengaluru, India Experience: 8 10 Years Mandatory Skills: AWS, Generative AI About Wipro Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a global leader in consulting and technology services with over 230,000 employees across 65 countries. We provide digital transformation solutions that are innovative, sustainable, and scalable. Role Overview We are hiring a highly skilled Gen AI AWS Engineer to lead the architecture, development, and delivery of AI-driven cloud solutions. This role focuses on leveraging AWS infrastructure and Generative AI technologies to solve complex business problems at scale. Key Responsibilities Architecture and Solution Design Design and implement scalable AI/ML solutions using AWS and GenAI frameworks. Lead solution design for enterprise initiatives and RFPs. Develop architectural documentation and reusable design patterns. Evaluate current architectures and recommend improvements and modernization plans. Delivery Enablement Provide frameworks and technical direction to development teams. Monitor project risks and propose mitigation strategies. Ensure alignment with architecture principles and best practices. Client Engagement Participate in pre-sales activities and client presentations. Build trusted relationships with clients by demonstrating technical thought leadership. Coordinate with stakeholders to ensure successful delivery of AI solutions. Innovation & Competency Building Create PoCs, whitepapers, and solution demos in GenAI and AWS domains. Represent Wipro s capabilities at industry events and internal forums. Mentor junior architects and contribute to internal upskilling initiatives. Team Management Recruit, train, and retain high-performing AI/ML engineers. Conduct performance reviews and set goals for team members. Drive employee engagement and diversity across the architecture team. Be part of a company that thrives on innovation, reinvention, and purpose. Work with cutting-edge Generative AI solutions and lead impactful transformations for global clients. Applications from individuals with disabilities are explicitly welcome.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Job Title: Test Specialist - Middleware Testing Practitioner Introduction: As part of our IBM Consulting Client Innovation Centers (Delivery Centers), you will play a crucial role in delivering deep technical and industry expertise to a wide range of public and private sector clients across the globe. These centers provide locally-based skills to help drive innovation and adoption of new technologies. As a Test Specialist at IBM, your analytical and technical abilities will directly contribute to the quality of the software we deliver. In an agile environment, you ll help elevate each iteration through your testing expertise, ensuring the best possible outcomes for IBM and its clients. Whether the testing is manual, automated, or cognitive, you ll be at the forefront of delivering high-quality software solutions. Your Role and Responsibilities: Middleware Testing Practitioner: Design, build, and deploy effective testing solutions that minimize manual effort throughout the testing process. Automated Testing: Apply automated tools to support testing activities across all phases of the Software Development Life Cycle (SDLC). Tool Recommendations: Support the test team by recommending and implementing tools and processes for automating other testing activities, including test management, reporting, test data generation, and defect management. Required Technical and Professional Expertise: Experience: 4+ years of experience in SDET (Software Development Engineer in Test) and testing. Web Technologies: Solid knowledge of Internet/Web Technologies. Testing Tools: Experience with tools like SOAP UI, CA Lisa, ParaSoft, or similar tools. Proficiency in Rest Assured or other API Test Automation Frameworks. Middleware Expertise: Knowledge of WebSphere MQ and IBM Integration Bus (IIB) (good to have). Coding Skills: Excellent coding skills in JavaScript or Java. Preferred Technical and Professional Expertise: Database Knowledge: Experience in understanding data models and writing database queries, with knowledge of NoSQL platforms. Automation Strategy: Experience designing and implementing test automation strategies for distributed systems. Production Issue Resolution: Ability to solve/debug production issues by collaborating with remote teams across different verticals (QA, Dev, PM, Operations). Stub and Mock Data: Understanding of automation testing using stub and mocked data from integrated systems. Innovation: Work at the cutting edge of technology, helping drive advancements in software testing and middleware solutions. Global Impact: Your work will have a direct impact on IBM s global success and the software quality delivered to our clients. Continuous Learning: Gain access to IBM s vast resources and opportunities for professional growth, including the latest tools and technologies in testing and software development. Collaborative Culture: Join a dynamic, inclusive team of experts where your contributions and ideas are valued. If you are passionate about software testing, eager to innovate with cutting-edge technologies, and ready to make a global impact, join us at IBM and help shape the future of software quality and middleware solutions.

Full-Stack Developer - Windows on Snapdragon Platform Team Company Qualcomm India Private Limited Job Area Engineering Group > Software Engineering General Summary Qualcomm Technologies Inc., the maker of the industry-leading Snapdragon SoCs, is the largest provider of complete chipset solutions for Microsoft Windows on Snapdragon products. Qualcomm is committed to developing solutions for the next generation of Windows on Snapdragon devices. The ideal software engineer will act as a key member of an Agile Scrum Team and play a pivotal role in the end-to-end lifecycle of all Windows-on-Snapdragon product lines. This role requires strong software development skills to act as a hands-on contributor responsible for gathering requirements, designing, and developing improvements to the Windows-on-Snapdragon continuous integration build systems, software release process, and developer operations tools. Strong communication and collaboration skills are essential, as this platform team works closely with internal and external teams to bring up, support, triage, and resolve issues on Qualcomm chipsets. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master s degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Languages such as C, C++, Java, Python, etc. Key Responsibilities Design, develop, test, and maintain web applications using Python and C#. Implement front-end interfaces using ASP.net, HTML, CSS, and JavaScript. Design and maintain SQL databases, writing efficient SQL queries. Develop and maintain automation scripts using PowerShell, CMD, and BAT. Work within version control systems such as Git and Perforce. Contribute to embedded Windows software development with solid programming skills. Apply strong understanding of Operating System concepts, both Windows and Linux. Participate in Windows and/or Linux kernel development activities. Preferred Qualifications 2-5 years of Software Engineering or related work experience. Proficiency in Python, C/C++/C#, SQL, and Shell Scripting. Strong communication and interpersonal skills. Effective problem-solving and debugging capabilities. Experience with Windows OS internals. Experience debugging device drivers using WinDbg, JTAG, or similar tools. Basic understanding of processor architecture and cache subsystems. Experience with PC software development (System BIOS, UEFI, ACPI, Drivers, Applications). Working knowledge of Jenkins and Artifactory. Hands-on experience with Windows program/driver development. Proficiency in Visual Studio as an integrated development environment. Exposure to ARM assembly. Basic understanding of Embedded OS (Kernel architecture, OS services, heap, memory management, multi-core processing, multi-threading, and crash debugging). Strong motivation and ability to learn quickly. Equal Opportunity Employer Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email [email protected] or call Qualcomm s toll-free number listed on their careers page. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities during the hiring process. (Please note: this email address is intended solely for accommodation requests. Qualcomm will not respond to requests for application status updates or resume inquiries through this contact.) Recruitment Policy Qualcomm s Careers Site is exclusively for individuals seeking employment directly with Qualcomm. Staffing agencies and third-party recruiters are not authorized to submit profiles, applications, or resumes via this site. Any such submissions will be considered unsolicited, and Qualcomm will not be responsible for any associated fees. Compliance Notice All Qualcomm employees must adhere to applicable company policies and procedures, including but not limited to those regarding security, confidentiality, and protection of proprietary information, in compliance with applicable laws.

Senior Emulation Engineer Company Arm Location Bengaluru, India Job Overview Arm s Central Emulation team is excited to welcome experienced Emulation experts to join the team in Bengaluru. You will collaborate with design and verification engineers across the UK, US, India, and France to support advanced Compute Subsystems and SoC projects. Arm is building a team to develop exceptional silicon demonstrators based on Arm s IP compute sub-system solutions, targeting premium mobile, infrastructure, and automotive markets. Using the latest technology nodes (e.g., 3nm) and new 3D packaging innovations, Arm s goal is to demonstrate industry-leading performance by architecting, designing, implementing, and fabricating cutting-edge silicon test chips. This initiative brings together innovative talent and expertise from across the semiconductor industry to shape the next generation of compute on Arm devices. Responsibilities Collaborate with end users to understand system use cases and guide validation efforts. Ensure tight integration between hardware qualification and final application use models. Work in an exciting emulation environment using hybrid and virtual solutions, integrating industry-standard high/low-speed IO IPs into subsystems and SoCs. Engage from early architecture and design phases to pre-silicon validation and post-silicon validation on emulation platforms. Drive pre-silicon emulation across all SoC teams. Ensure design quality and debuggability by collaborating closely with the design team. Support architecture, verification, system validation, performance, power, and DFT teams with insights from performance and power characterization. Develop comprehensive pre and post-silicon test plans in collaboration with verification teams. Develop tests, create bare-metal drivers for industry-standard IO IPs, and build frameworks to enable scalable testing across multiple ASIC projects. Required Skills and Experience Bachelor s degree (BE/BTech) in Electronics Engineering. 8+ years of experience in Pre-Silicon Validation and Emulation/FPGA-based platforms. Experience developing C/C++/SystemC tests for HDL-HVL co-emulation platforms. Proficiency in IO bus protocols such as I2C, SPI, USB, and/or PCIe. Experience with SoC debugging tools such as JTAG and Trace32. Nice-to-Have Skills and Experience Knowledge of ASIC design and prototyping flows. Experience with SystemC/C/C++ and UVM/SystemVerilog (SV) verification languages. Familiarity with domains such as PCIe, Flash, Memory, CPU, GPU, and DRAM. Hands-on experience with emulation toolchains such as Zebu, Veloce, or Palladium. What Arm Offers Arm is committed to global talent acquisition, offering an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace where everyone can thrive, Arm encourages its people to make exceptional contributions to its global success. #LI-KR2 Qualification : Bachelors degree (BE/BTech) in Electronics Engineering.

Job Title: L2 Support Lead Cloud Native Microservices Location: Pune, India Company: Blue Yonder Experience: 5+ years Education: Bachelor s Degree in Computer Science, Engineering, or related field About Blue Yonder Blue Yonder is a leading AI-driven Global Supply Chain Solutions provider, recognized by Glassdoor as one of the Best Places to Work. We specialize in cloud-native solutions that power intelligent supply chains and optimize commerce for some of the world s biggest brands. We are seeking a highly motivated and hands-on L2 Support Lead to oversee production support for cloud-native microservices-based commerce solutions deployed on Azure and GCP. Scope of the Role You will lead and mentor an L2 support team, responsible for triaging production issues, resolving functional and technical defects, and working closely with cross-functional engineering teams. Your focus will be on delivering best-in-class support to global customers, while ensuring the team continuously enhances its technical capabilities. Key Responsibilities Lead the L2 Support team, guiding associates in technical analysis, issue triage, and defect resolution. Act as a hands-on technical mentor, helping junior and mid-level team members grow their technical and product knowledge. Perform root cause analysis for functional and technical production issues, ensuring timely resolution. Support cloud-native microservices for Commerce customers, deployed on Azure and GCP. Participate in backlog grooming, sprint planning, stand-ups, and retrospectives, contributing to team direction and prioritization. Collaborate with product engineering teams, providing feedback and improvement recommendations from a supportability perspective. Ensure the team maintains strong documentation practices for knowledge sharing and future reference. Drive a continuous improvement mindset, identifying opportunities to enhance processes, automation, and response times. Foster a customer-first culture by ensuring timely, clear communication with internal and external stakeholders. Technical Environment Languages & Frameworks: Java, Spring Boot Architecture: Microservices, Event-Driven, Multi-Tenant, Scalable, and Resilient Cloud Platforms: Azure & GCP Other Technologies: Kubernetes, Kafka, Elasticsearch, Cassandra, MongoDB, Snowflake Version Control & Deployment: GIT, Rest API, OAuth Minimum 5+ years of experience with Spring Boot and Kafka in production support or engineering roles. Proven experience leading small to mid-sized teams for technical and product support in a cloud-native environment. Strong hands-on knowledge of microservices architecture running at scale on cloud platforms like Azure, GCP, or AWS. Solid understanding of caching frameworks (e.g., Hazelcast, RabbitMQ). Experience with cloud deployment processes and monitoring solutions. Strong troubleshooting and root cause analysis skills. Excellent communication skills to engage with global stakeholders. Understanding of product implementation processes and support best practices. Good to Have Experience in working on Commerce or Retail solutions. Exposure to log aggregation and distributed tracing tools. Ability to script/automate repetitive tasks to improve operational efficiency. Be part of a global, collaborative team working on innovative supply chain and commerce solutions. Work with the latest cloud technologies in a fast-paced, agile environment. Opportunity to mentor and shape the next generation of support engineers. Thrive in a workplace that values diversity, inclusion, and continuous learning. Diversity, Inclusion, Value & Equity (DIVE) At Blue Yonder, we embrace diverse perspectives and foster an inclusive culture where every voice is valued. We encourage applicants from all backgrounds to apply and contribute to our innovative, collaborative workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status. Qualification : Bachelors Degree in Computer Science, Engineering, or related field

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

As a Technical Lead you should have strong analytical skills, a well-rounded understanding of both front-end and back-end development, and a passion for problem-solving. Location: Bengaluru, India You will have - Bachelor s degree required. Minimum 8 years of experience. Good for you to have Excellent knowledge of architectural/design patterns, data structures and algorithms. Expertise on performance tuning and optimizations. You will definitely possess these technical skills Core skill set (must): Core Java, Multi-threading, GC, J2EE technologies, REST. Core skill set (must): RDBMS, Data Modeling, DB tuning. Working Knowledge (must): Server-side implementation for highly concurrent and responsive systems. Bird s eye view of your role The person should be highly proficient in Java and other J2EE technologies. The person must have strong programming skills and excellent computer science fundamentals on data structures and algorithms. What will you bring Ideal candidates should have solid experience in building highly concurrent, responsive and scalable systems. The role requires high proficiency on Database and expertise on RDBMS. The candidate should be having deep understanding of the various architectures, design patterns and coding techniques to address complex problems in software. The person should be highly proficient in Java and other J2EE technologies. The person must have strong programming skills and excellent computer science fundamentals on data structures and algorithms. What are your performance objectives This role comes with responsibility of building the next generation provisioning platform for Aryaka. The system aims to eliminate the manual effort involved in the tedious process of customer on-boarding. The workflows involved are complex and you can expect many more as the product becomes popular. The person needs to exhibit highest levels of architectural, design and coding skills so as to keep the platform concise, robust and futuristic. The role demands the candidate to be expert in troubleshooting, performance tuning, DB optimizations etc. This position requires passion and commitment to job and requires excellent communication skills to work with stake holders in US. Employee Value Proposition (EVP): At Aryaka, we offer a dynamic and innovative work environment where you will have the opportunity to make a significant impact in the network security industry. Our commitment to cutting-edge technology and customer satisfaction provides a platform for continuous learning and professional growth. Qualification : Bachelors degree required.

Key Responsibilities: Develop and support test generation frameworks for SoC system validation, focusing on Linux-based and Clang/LLVM-based compiler frameworks. Design and implement Linux kernel modules, device drivers, and compiler extensions to support SoC flows, including coherency, PCIe, power management, and security. Enable post-Si validation stress and shift-left validation to improve Time to Market (TTM) for Intel products. Collaborate with internal customers from validation teams to develop solutions utilizing your knowledge of computer system architecture. Design and implement solutions that simplify test content writing and reuse. Ensure the validation of SoC capabilities on pre/post-Si platforms. Participate in Agile development cycles to ensure efficient product delivery and quality. Minimum Qualifications: Bachelor's or Master's degree in Computer Science, Computer Engineering, or Electrical Engineering. Minimum of 3 years of experience (B.Tech) or 2 years (M.Tech) experience with C/C++ programming and Object-Oriented Programming (OOP). At least 2 years of experience with computer system architecture. Self-initiated and a strong team player, comfortable working in an Agile project environment. Preferred Qualifications: Experience with PC bus protocols and industry-standard I/O interfaces (PCIe, USB, DP, HDMI, etc.). Familiarity with GIT revision control systems. Experience with compilers and compiler toolchains. Experience with Linux or Windows device drivers. Knowledge of makefile build environments and scripting languages. Experience in developing or using validation tools would be highly valuable. About Intel Validation Engineering (iVE) Team: Intel Validation Engineering (iVE) plays a critical role in Intel's product leadership. Our team validates, debugs, and tunes Intel's newest designs and world-changing technologies. We are essential in completing the PRQs (Product Readiness Qualifications) for Intel products, ensuring Intel's ability to deliver the annual technology platforms in our roadmap. Equal Opportunity Employer: Intel is committed to ensuring that all qualified applicants receive consideration for employment without discrimination based on race, color, religion, creed, sex, national origin, ancestry, age, disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, sexual orientation, or any other characteristic protected by law. If you're passionate about developing cutting-edge frameworks for SoC validation and eager to contribute to world-class technology, we encourage you to apply. Qualification : Bachelors or Masters in Computer Science Computer Engineering or Electrical Engineering

Job Description You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.As a DFT engineer Direct Responsibilities of the role, but not limited to: Working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus. Qualifications Candidate must possess a master's degree in Electronics or Computer Engineering with at least 5 or more years of experience or a bachelor's degree with at least 7 years of experience of DFT experience. Strong knowledge of ATPG, various fault models, fault grading. Knowledge of memory BIST, IJTAG/TAP architecture. DFT logic generation, integration, and verification. EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring up preferably Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer. Post Silicon/ATE Bring-Up Support. Experience with RTL (Verilog, System Verilog, VHDL). Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Candidate must possess a master's degree in Electronics or Computer Engineering with at least 5 or more years of experience or a bachelor's degree with at least 7 years of experience of DFT experience.

We are seeking a highly skilled and experienced DFT Engineer to join our team. The ideal candidate will have a strong background in Design for Testability (DFT) methodologies and implementation, with a deep understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). The role will involve developing and implementing DFT strategies for complex mixed-signal integrated circuits (ICs), ensuring high fault coverage and testability. ASIC Implementation DFT Responsibilities Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test. Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns. Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement. Generate high-quality test patterns using automated test pattern generation (ATPG) tools. Verify the correctness of DFT implementation through simulation and hardware testing. Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process. Minimum Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering. 10+ years of experience in DFT for mixed-signal ICs. Understanding of DFT concepts, including scan insertion, BIST, and boundary scan. In-depth knowledge of DFT EDA tools (Siemens/Synopsys). Familiarity with IEEE standards 1149, 1500, and 1687. Experience with fault simulation and coverage analysis tools. Problem-solving and analytical skills. Strong communication skills Work independently and as part of a team. Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation. Preferred Qualifications Master's degree in Electrical Engineering or Computer Engineering. Experience with mixed-signal DFT methodologies. Knowledge of scripting languages (e.g., Perl, Python) for automation. Experience with hardware testing and debugging. Qualification : Bachelor's degree in Electrical Engineering or Computer Engineering.

Introduction As a Power Performance Tools developer your responsibilities will include creating and maintaining tools and automation required for analyses to detect performance bottlenecks, managing performance aspects, and uncovering optimization opportunities for every major release of IBM Power (IBM Power systems) This role requires expertise in OS concepts, computer system architectural design and performance analysis . The areas of work will be to develop test automation framework on different versions of the latest family of IBM Power servers utilizing several versions of PHYP, Power Firmware, AIX / VIOS, and Linux releases. Your role and responsibilities As a tools developer you will design, build, test and deploy effective testing solutions which reduce the amount of manual effort in the Performance test execution and analysis. You are responsible for developing and maintaining automated tools for system performance analysis and optimization Support the test team by recommending tools and processes To automate other test activities, such as test management, reporting, test data generation and defect management. Work closely with team members to design and develop performance testing tools and platforms. Develop acceptable performance test reporting and process tools preferably open-source/home grown. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of overall IT experience 5+ years of experience as a Tools Developer 5 years of experience in hardware system test automation domain 5+ years of experience in a software development role using Python,C, C++ Strong analytical and problem-solving skills, Ability to handle coding, testing, and debugging tasks; independently and as part of a team. Experience with other programming and scripting languages; i.e. Node.js, Perl, Linux Shell Experience developing in a Linux development environment Strong expertise in virtualization technologies, including hypervisors virtual machine management, and resource optimization. Good knowledge on Computer system architecture ,system HW , Operating System REST and JSON Good problem solving, strong analytical and logical reasoning skills Familiar with server performance management and capacity planning Familiar with performance diagnostic methods and techniques Knowledge of Agile and DevOps practices and methodologies including Continuous Integration. Preferred technical and professional experience Experience on Java,Ansible would be an added value. Knowledge of IBM PowerVM Virtualization Qualification : Required education => Bachelor's DegreePreferred education => Master's Degree

Product Marketing Specialist Experience: 3 5 Years | Location: Bangalore | Employment Type: Full-Time About SecPod SecPod is a pioneering cybersecurity technology company dedicated to a prevention-first approach. Our core portfolio, the Saner Platform, provides a comprehensive suite of solutions that protects endpoints, servers, networks, and cloud infrastructure by combining security intelligence with automation. About the Role We are looking for a Product Marketing Specialist to craft compelling narratives, sharpen product positioning, and drive adoption. You will create high-impact content across websites, blogs, ebooks, and social media to communicate product value and influence buying decisions. Key Responsibilities Content Creation: Develop and manage marketing assets including blogs, web pages, ebooks, email campaigns, and sales collateral. SEO & Optimization: Optimize content for SEO to improve organic visibility and refine content to increase engagement across channels. Go-to-Market (GTM) Strategy: Collaborate with Sales, Product, and Partner teams to develop demand-generation and GTM campaigns. Messaging & Positioning: Build compelling product stories and positioning that highlight differentiation and resonate with buyer personas. Performance Analytics: Track and analyze content performance metrics to measure effectiveness and drive improvement. Qualifications & Experience Education: MBA in Marketing or Bachelor s degree in Engineering. Professional Background: 3 5 years of experience in content writing, product marketing, or B2B SaaS marketing. Domain Expertise: Preferred experience in cybersecurity or enterprise technology. Skill Set: Strong understanding of audience targeting, content-driven demand generation, and exceptional storytelling skills. What You ll Gain Hands-on experience shaping product marketing strategy and messaging. Deep exposure to enterprise cybersecurity products and global security trends. A clear growth path toward becoming a high-impact marketing leader. Qualification : MBA in Marketing or Bachelors degree in Engineering