Block Diagram Design Jobs in Bengaluru

Job Title: General Manager Market Research Location: Bangalore Employment Type: Full-Time About the Role We are seeking a motivated, self-driven leader with a strong technical background and a passion for market research to join our Sector Research team. This is a senior role focused on driving high-quality market research across diverse sectors including FinTech, SaaS, FoodTech, Cybersecurity, Healthcare, and more. This position involves managing and mentoring a team of subject matter experts while leading the research strategy and process improvements. Note: This role is specifically for candidates with a market research or related background. It is not suitable for Investment Analysts, Associates, CAs, CFAs, or Finance Executives. Key Responsibilities Lead Sector Research Oversee multiple market research projects across sectors such as FinTech, SaaS, FoodTech, etc. Guide and mentor a team of researchers, ensuring high-quality, insightful research outputs. Define strategic direction for sector research and ensure alignment with business goals. Process Ownership & Team Management Take complete ownership of research processes within the department. Identify and resolve project bottlenecks to meet deadlines and quality standards. Organize and facilitate training programs to upskill team members as needed. Provide ongoing mentorship and constructive feedback to foster continuous improvement. Collaborate with senior stakeholders to review project status and implement course corrections. Department Blueprint & Strategy Design foundational building blocks and operational blueprints for the research department. Gather inputs from peers and secure buy-in from senior management. Develop a prioritized roadmap of actionable projects to drive impact and efficiency. Implementation & Optimization Build scalable and efficient research processes, with an emphasis on accuracy and automation. Define and track KPIs to measure project and team performance. Address team queries and integrate solutions into Standard Operating Procedures (SOPs). Monitoring & Continuous Improvement Establish protocols and MIS reports to monitor departmental health and project progress. Escalate any non-compliance or quality concerns promptly. Identify opportunities for new projects and process enhancements based on data insights. Continuously refine the department blueprint and processes to optimize outcomes. Requirements Graduated from a Tier 1 institute with top-notch academic credentials. 5+ years of experience in market research, business strategy, consulting, or related fields. Strong analytical and problem-solving skills; ability to apply first-principles thinking. Proven leadership skills with a passion for mentoring and developing team members. Collaborative mindset with the ability to work across departments. Results-driven, with a high level of ownership and commitment to excellence. Strong decision-making skills grounded in logical reasoning and openness to feedback. What You Can Expect at Tracxn A meritocracy-driven and candid culture with zero politics. Collaborative environment with intellectually curious colleagues. Fast-paced learning with continuous mentorship to help you reach your full potential. Qualification : Graduated from a Tier 1 institute with top-notch academic credentials

Job Title: System Engineer Job Type: Full-Time Location: Bangalore Experience Required: 2 3 Years Education: B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation Job Summary: We are looking for a motivated System Engineer with a foundational understanding of RF systems and hands-on experience working with electronic hardware. The ideal candidate should be capable of interpreting schematics and working with standard lab equipment to support system integration and validation tasks. Key Responsibilities: Assist in the design, testing, and validation of RF-based systems. Interpret and analyze hardware block diagrams and schematics. Support schematic reviews and perform basic schematic design activities. Operate and utilize test equipment such as spectrum analyzers, multi-meters, and oscilloscopes. Work on basic concepts of acquisition and tracking, especially in systems like GPS satellite receivers. Collaborate with the hardware and system teams to support integration, debugging, and testing activities. Required Skills & Qualifications: Educational background in ECE, EEE, or Instrumentation. Basic knowledge of RF systems and principles. Familiarity with electronic schematics and hardware block diagrams. Ability to use electronic test instruments (Spectrum Analyzer, Oscilloscope, Multi-Meter). Understanding of GPS signal acquisition and tracking is a plus. Good communication skills and willingness to learn and grow in a technical environment. Qualification : B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation

Job Title: Software Design & LabVIEW Engineer Location: Bengaluru Overview: Join CynLr s Product Design and Algorithm Team as a Software Design & LabVIEW Engineer, where you will be instrumental in developing LabVIEW code for advanced algorithms and experiments, optimizing performance, and supporting the software development lifecycle with strong architectural discipline. You will also provide critical interface and support for hardware-in-the-loop validation and customer implementation. Key Responsibilities: LabVIEW Development & Experimentation Translate concepts and algorithms from Design and Algorithm teams into well-structured LabVIEW code and experiments. Optimize LabVIEW code for timing and memory performance. Build custom data visualizations and user-friendly UI elements to accelerate experimental workflows. Enhance Lab experiment applications for usability and efficiency. Code Refactoring & Architecture Understand and apply established LabVIEW design patterns and coding standards (including STQ). Refactor legacy spaghetti code to comply with architecture and design guidelines. Document and maintain code quality and design consistency. Software Development Lifecycle Integration Implement and maintain source and version control using GIT or equivalent tools. Integrate evolving C++ DLL libraries seamlessly into LabVIEW codebases without disruption. Verification & Validation (V&V) Develop test cases and execute validation tests for C++ and LabVIEW code. Perform hardware-in-the-loop testing to validate algorithm functionality and performance. Customer Interface & Support Assist in application implementation and provide technical support to customers. Serve as a LabVIEW knowledge resource for the Algorithm and Design engineers and onboard new team members. Job Requirements: Programming Fundamentals Strong understanding of Data Flow programming paradigm and parallel programming in LabVIEW. Experience with dynamic thread management and service spawning. Software Design & Development Proven involvement in the full software development lifecycle, including distributed development with source/version control (GIT). Expertise in State Machine architecture and familiarity with other design patterns applied in LabVIEW. UI/UX Skills Proficient in building custom controls, data visualizations, and UI elements (experience with XControls is a plus). Strong knowledge of subpanels, resolution reflow, and splitter management for UI design. LabVIEW IDE Expertise Deep knowledge of VI Server (methods and attributes) and VI scripting (preferred). Mastery of LabVIEW project and environment settings, including front panel customization, function palettes, debugging, VI properties, and productivity features. Connectivity & Hardware Interface Experience integrating .dll libraries and C++ header files into LabVIEW applications. Familiarity with registry coding is advantageous. Hands-on experience with communication protocols including Ethernet (UDP, TCP), RS232/485, and industrial protocols like Modbus, CAN, etc.

Architect Infrastructure Solutions Location: Bangalore (Bengaluru) Experience: 8 to 12 Years Job Role: Infrastructure Solutions Architect Industry: IT Infrastructure & Cloud Services Job Summary: We are seeking a skilled Infrastructure Solutions Architect to design, document, and lead enterprise infrastructure projects, including virtualization, data center upgrades, migrations, and cloud integration. The ideal candidate will have hands-on experience with infrastructure technologies and the ability to deliver comprehensive design documentation and presentations. Key Responsibilities: Architect, design, and document enterprise infrastructure solutions including VMware virtualization, Nutanix, NetApp, EMC, and Windows Servers Develop high-level and low-level design diagrams, technical documentation, and detailed solution specifications Lead infrastructure upgrade, refresh, migration, and Hyper-Converged Infrastructure (HCI) projects Design and implement solutions for server, storage, backup, data center, high availability, disaster recovery, and business continuity Collaborate closely with cross-functional teams including server, network, architecture, operations, engineering, and project management Define and promote infrastructure best practices and standards Analyze existing infrastructure and recommend improvements for performance, cost efficiency, and scalability Prepare technical presentations and documentation using tools like Microsoft Visio and PowerPoint to communicate solutions, timelines, and costs Connect on-premises infrastructure with cloud technologies to enable hybrid solutions Required Skills & Qualifications: Bachelor s or Master s degree in Information Technology, Computer Science, or related field 8-12 years of experience in infrastructure architecture design, implementation, and support Minimum 5 years of experience as an infrastructure solutions architect in large enterprises Hands-on infrastructure engineering experience (5+ years) including data center design and migrations Strong expertise in virtualization platforms such as VMware and HCI technologies like Nutanix Deep knowledge of storage solutions including NetApp, EMC, and backup technologies like Rubrik and Zerto Experience managing Windows Servers and Active Directory environments Solid understanding of cloud technologies and automation tools Proficiency in creating detailed technical documentation and architecture diagrams Excellent communication, presentation, and problem-solving skills Lead impactful infrastructure transformation projects in a dynamic enterprise environment Collaborate with global teams and advance your skills in cloud and data center technologies Work on cutting-edge infrastructure solutions supporting business continuity and disaster recovery Qualification : Bachelors or Masters degree in Information Technology, Computer Science, or related field

Job Title: Consultant - UX Designer (Intern) Location: Bangalore, India Company: Glance An InMobi Group Company About Glance Join Glance, where creativity meets cutting-edge AI technology! Glance is revolutionizing mobile user experiences by combining AI and user-centered UX design directly on the lock screen. As a UX Intern, you ll work with a dynamic team creating context-driven, interactive content that delights millions of users worldwide. Position Overview As a UX Intern at Glance, you ll gain hands-on experience in UX design fundamentals while exploring emerging AI technologies and prompt engineering. This internship is ideal for individuals passionate about designing seamless, intuitive user experiences and eager to build skills in AI-driven UX and prompt engineering. Key Responsibilities Assist in UX Design: Create wireframes, layouts, and visual design elements that enhance usability and engagement on Glance s lock screen platform. Collaborate on AI-Driven UX Projects: Partner with designers, engineers, and data scientists to integrate AI for personalized and intuitive user interactions. Learn Prompt Engineering: Develop expertise in crafting prompts that help AI understand and respond effectively to user behavior, improving the overall UX. What You ll Gain Hands-On UX Design Experience: Build a strong foundation in UX principles and user-centered design workflows. Exposure to Advanced AI Technologies: Learn how AI can be harnessed to create innovative, personalized user experiences. Prompt Engineering Skills: Acquire in-demand skills in prompt engineering within AI-powered platforms. Mentorship and Professional Growth: Work alongside experienced professionals in a collaborative, supportive environment focused on your development. Qualifications Currently pursuing a degree in Design, Human-Computer Interaction (HCI), Psychology, Computer Science, or a related field. Strong interest in UX design fundamentals, AI technology, and emerging digital trends. Familiarity with UX tools such as Figma, Sketch, or similar is a plus. Creative mindset with curiosity and willingness to experiment with new ideas. Contract Duration: 6 Months Kickstart your UX career with Glance and be part of a future-forward team shaping next-gen mobile experiences. Apply now to join us in Bangalore! Qualification : Currently pursuing a degree in Design, Human-Computer Interaction (HCI), Psychology, Computer Science, or a related field.

Job Title: Lead Go-To-Market (GTM) Strategy Location: Bangalore, India Company: Glance An InMobi Group Company About Glance Founded in 2019, Glance is a pioneering consumer technology company operating disruptive digital platforms including Glance, Roposo, and Nostra. Our flagship Glance Lock Screen powers over 400 million smartphones worldwide, delivering personalized content without the need for searching or downloading apps. Roposo revolutionizes live video experiences with immersive creator-led content, while Nostra stands as the largest gaming platform across India and Southeast Asia, offering gamers engaging ways to discover, play, watch, learn, and compete. Headquartered in Singapore, Glance is an unconsolidated subsidiary of InMobi Group. At Glance, we encourage you to dream big, innovate boldly, and take ownership from day one. Work alongside highly skilled and passionate peers on mission-critical projects. Enjoy a culture that rewards autonomy, creativity, and collaboration, supported by wellness programs, tech tools, daily meals, gym access, and a family-friendly workspace welcoming your kids and pets. Role Overview As the Lead GTM Strategy, you will craft and execute monetization strategies for Glance Media offerings, serving as a Brand Solutions Specialist. You ll partner with clients to understand their business goals, challenges, and opportunities, aligning Glance s innovative media products to drive impactful marketing results. Key Responsibilities Collaborate with GTM, creative, and client solutions teams to identify mobile marketing challenges and opportunities for diverse client portfolios. Design tailored, effective solutions leveraging Glance Lock Screen Media offerings including Display, Video, Interactive Units plus Gaming and Content products, aligning with client objectives and addressing business and technical challenges. Conduct training workshops to articulate Glance Media and Content capabilities to brands and agencies. Partner closely with Sales, Marketing, and Client Services teams to ensure successful client engagements, leveraging insights and feedback loops. Develop compelling, research-driven presentations that combine data and creative storytelling. Empower Sales Managers with data-backed programs and product solutions aimed at driving business growth. Proven experience (4+ years) in content marketing, brand marketing, media planning, strategy, or digital advertising within dynamic environments. Creative, energetic self-starter with the ability to work independently and lead initiatives with minimal supervision. Proficiency in brand marketing frameworks and simplifying complex concepts into clear, actionable insights. Strong business acumen with the ability to quickly understand client needs and leverage market research effectively. Excellent communication skills both oral and written including brand storytelling and workshop facilitation. Comfortable managing projects across multiple teams, geographies, and strict timelines in a fast-paced setting. Required Qualifications 4+ years of professional experience in business solutioning, consulting, digital advertising, media planning, or pre-sales. Bachelor s degree required; MBA preferred. Location: Bangalore, India Take the lead in shaping groundbreaking GTM strategies with Glance. Apply now and join a visionary team transforming mobile consumer experiences! Qualification : Bachelors degree required; MBA preferred.

Electrical Principal Engineer FPGA Team Location: Bengaluru, India Team: Electrical Engineering Company: Dell Technologies Role Overview As a Principal Electrical Engineer, you will contribute to the architecture, design, and validation of FPGA-based hardware systems for Dell s next-generation enterprise servers. This role involves working across global teams to deliver robust, scalable, and efficient PCBA (Printed Circuit Board Assembly) and logic solutions that align with industry standards and internal requirements. Key Responsibilities Architect and design next-gen hardware features in collaboration with front-end teams and partners. Analyze and recommend trade-offs in design features and costs. Guide global teams with best practices in electronic hardware design. Own and deliver system interfaces and support cross-functional development efforts. Create comprehensive documentation for testing and validation. Essential Requirements 8 12 years of experience in FPGA hardware verification using Verilog, SystemVerilog, VHDL. Expertise in UVM, ABV (Assertion-Based Verification), code coverage, and unit-level simulation. Knowledge in digital design methodologies: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Static timing analysis Experience with x86 or ARM architectures. Familiarity with peripheral protocols: I2C, I3C, SMBus, IPMI, IPMB. Strong background in both analog and digital design. Understanding of hardware/software co-design and debugging complex systems. Desirable Qualifications Experience with Intel/AMD x86 and ARM-based systems. Hands-on with FPGA tools: Xilinx, Lattice, Altera Quartus, ModelSim/QuestaSim. Passion for mentoring and knowledge sharing. Dell Technologies offers a collaborative and innovative environment where hardware engineers work at the forefront of industry advancements. You'll be empowered to lead cutting-edge hardware projects, influence product design, and make a lasting impact on the future of enterprise technology.

Position: Application Engineer, Analog & Power Job Overview: We are seeking an Application Engineer specializing in Analog & Power to join our team. In this role, you will provide advanced engineering design services and support to the regional engineering team, with a focus on power electronics and analog engineering solutions. You will be responsible for hardware engineering support, including PCB design and review, electronic simulations, and laboratory analysis, all while ensuring compliance with industry standards and customer specifications. Key Responsibilities: Provide advanced engineering design and support for power electronics and analog systems, assisting the regional engineering team. Conduct hardware engineering tasks, including PCB reviews, electronic simulations, and using lab equipment such as PCBA rework tools and oscilloscopes for product development. Lead PCB design from initial concept (block diagrams) to part selection, schematics, layout, Gerber files, and prototype testing. Develop clear and concise technical documentation, such as whitepapers, technical reports, and internal training materials. Support the development and validation of reference designs to meet customer specifications. Ensure that all designs comply with relevant industry standards and customer specifications. Attend technical and sales training to stay up to date with current technologies and trends. Maintain accurate documentation of engineering designs and solutions for future reference. What We Are Looking For: Bachelor s Degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field. At least 7 years of experience in electronics/semiconductors, power management, and analog product design. Strong technical expertise in power conversion topologies (DC-DC, AC-DC, DC-AC). Experience working with WBG (Wide Bandgap) devices such as SiC and GaN. Solid experience with electrical instrumentation, including Op-Amps, signal conditioning, sensors, and data acquisition systems. Familiarity with industry standards and compliance (e.g., IEC, UL, ISO) for high-power systems. In-depth understanding of EMI/EMC standards and mitigation techniques for high-power designs. Experience in reference design development, validation, and component optimization. Strong communication and interpersonal skills to collaborate effectively with internal teams and customers. A passion for innovation and a commitment to delivering high-quality engineering solutions. What s In It For You: Access to training and professional development opportunities. Performance coaching and growth support. The chance to work with a fun and supportive team. Opportunity to be part of a growing and strong company. Community involvement opportunities. About Arrow: Arrow Electronics, Inc. (NYSE: ARW), a Fortune 133 company and one of Fortune Magazine s Most Admired Companies, is a global leader in technology solutions. With 2023 sales of USD $33.11 billion, Arrow develops innovative technology solutions that improve business and daily life. Our broad portfolio helps customers create, make, and manage forward-thinking products that make technology accessible to more people. Location: Bangalore, India Employment Type: Full-time Job Category: Engineering and Technology Qualification : Bachelors Degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: Qualcomm is at the forefront of technology innovation, constantly pushing the boundaries to enable next-generation experiences and drive digital transformation. As a Hardware Application Engineer at Qualcomm, you will provide technical expertise through product demonstrations, training, and support for the design, debugging, testing, and quality of customer products. You will work closely with cross-functional teams to assess and apply Qualcomm's products, ensuring they meet and exceed customer expectations. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 2+ years of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 1+ year of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR PhD in Electrical/Electronics Engineering, Computer Engineering, or a related field. Key Responsibilities: Engage with customer designs, assist with feature definition, and conduct design reviews. Provide in-depth technical responses to customer inquiries and troubleshoot customer designs. Offer necessary training and technical support to customers. Collaborate with hardware, software, RF systems, and testing teams to deliver comprehensive solutions. Provide hardware design support for customers developing wireless products. Perform block diagram, schematic, placement, and PCB design reviews on customer products. Troubleshoot technical issues and resolve problems through hands-on support. Assist customers in implementing new technology using Qualcomm chipsets and support business teams on new projects. Develop an understanding of RF systems and cellular standards, including GSM, LTE, and 5G. Conduct tests for various technologies such as GSM, C2K, TDSCDMA, WCDMA, LTE, 5G SUB6, and 5G mmW (a strong plus). Desired Skills and Experience: Strong knowledge of cellular technologies like GSM, LTE, and 5G. Understanding of RF component characteristics and behavior. Proficient in problem-solving and analytical skills. Familiarity with PCB CAD tools such as Allegro and PADS for reviewing customer layouts. Experience with digital circuit design, software programming, or power management is a plus. Strong communication skills and the ability to work effectively with cross-functional teams.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

End to End Solution Architect Location: Bangalore Role: End to End Solution Architect Experience: 15 - 25 years Number of Positions: 2 Qualifications: Job Description: Minimum of 15 years experience as an enterprise/solution architect in the telecom domain. Should have worked in telecom OSS systems. Knowledge about Enterprise products (B2B space) is needed e.g., managed broadband, managed security, etc. Telecom/Cable background is a must. Must be fluent in German. Must have experience in a multi-vendor environment. Manage Architecture deliverables; ensure understanding of Solution across all Epics and Tracks. Create and maintain end-to-end architecture artifacts including but not limited to, interface design documents, process design documents, sequence diagrams, data flow diagrams, and data models across the B/OSS ecosystem. Create and maintain the solution architecture roadmap across all Epics and produce architecture blueprints for each release iteration. Review business requirements and collaborate with development teams to identify system impacts and estimates. Conduct and represent in Joint Application Design (JAD) sessions as necessary during the design and integration phases. Follow through architecture issues and integration challenges that arise throughout the software development life cycle and provide resolution. Collaborate and drive alignment with key business stakeholders, solution development, and testing teams on architecture approach and direction. Co-ordinate with PM s, infrastructure/operations team, testing teams, and release/change control teams as needed. Defining software enterprise architecture. Demonstrating the ability to create systems architecture and solution design given a brief product requirement. Designing new features to meet new business requirements. Must have knowledge of Middleware-oriented management, Enterprise Service Bus (ESB), Enterprise Architecture tools (Visio, IBM Rational Software Architect, etc.), and Service Oriented Architecture (SOA). Workflow and business process management. System integration lifecycle for an OSS implementation. Expertise on leading COTS platforms. Office core field service management. Familiarity with Agile software development processes knowledge of the scaled agile framework is preferred. Ability to work in a multi-vendor environment.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Position: Sr. Network & Security Systems Engineer Location: Payoda, Global Regions Experience: 12 15 years of IT and business/industry work experience Education: Diploma with 10+ years or Bachelor's in Computer Science, Information Systems, or related field. Equivalent work experience considered. Shift: 24/7 Job Overview: The Sr. Network & Security Systems Engineer will design, implement, and support VMware NSX-based solutions requested by sales managers for various global clients. The role requires advanced technical expertise in NSX environments, strong troubleshooting skills, and experience with networking and security technologies. The candidate will collaborate with cross-functional teams and provide expert-level support to ensure stability and performance of NSX deployments. Key Responsibilities: Review customer High-Level Design (HLD) and Low-Level Design (LLD) documents and assess feasibility, risks, and constraints. Work closely with L1 teams to address global customer problems via virtual meetings. Create and maintain Method of Procedures (MOP) for planned activities and real-time problem resolution. Prepare Root Cause Analysis (RCA) reports and suggest workarounds by consulting OEM knowledge bases. Design hybrid and multi-cloud solutions for private and multi-cloud infrastructures. Prepare Bill of Quantity (BOQ) and Bill of Materials (BOM) by working with internal and external SMEs. Provide technical documentation, including IP schemas and technical specifications. Continuously monitor advancements in virtualization, networking, security, and cloud technologies. Train and support other team members to offload repetitive tasks and take on complex tasks with practice. Technical Skills and Responsibilities: Provide security and network support for physical networking and firewall services. Deliver and maintain network and security infrastructures using NSX/NSX-T. Implement networking and VXLAN technologies and improve network manageability and scalability. Monitor integration with other software-defined networking technologies. Maintain VMware vROps (ARIA) for capacity planning and troubleshooting. Automate network deployment and configuration with integration of compute and storage automation. Support operations and maintenance of VMware virtual infrastructure. Improve customized outlines using NSX, vRA (ARIA), and vRO (ARIA). Key Success Factors: Extensive knowledge of Cisco and VMware products and solutions. Hands-on experience with network diagram tools like Visio and Lucidchart. Ability to build High-Level Design documents independently. Strong understanding of Cisco Solution Life Cycle Prepare-Plan-Design-Implement-Operate-Optimize. Ability to lead technical workshops and explain solutions to non-SMEs. Knowledge of cloud providers like AWS, Azure, and GCP. Required Skills: NSX-T, NSX-T Edge, NSX Firewall, NSX Load Balancer VMware Cloud Foundation vCenter and ESXi vRealize Network Insight and Log Insight Automation scripting experience in Python, PowerShell, or equivalent Experience with Agile development methodologies Certifications: VMware Certified Professional (VCP) or Expert VCP-NV VCDX-NV VCP NV-Adv-Professional Join Us! We offer a collaborative environment, continuous learning opportunities, and a chance to work on advanced technologies. Let s celebrate work and grow together! Qualification : Diploma with 10+ years or Bachelor's in Computer Science, Information Systems, or related field. Equivalent work experience considered.

Job Overview As a Hardware Engineer at Qualcomm, you'll be part of a dynamic team that plans, designs, optimizes, verifies, and tests cutting-edge electronic systems, including circuits, mechanical systems, digital/analog/RF/optical systems, and more. Your role will focus on SerDes PHY Analog Design, specifically within the BDC SerDes Mixed-Signal Design team. This team is directly involved in delivering next-generation custom PHY designs for SoCs (System on Chips), with a key focus on low-power analog designs to support Qualcomm s wireless products. You ll work with cross-functional teams to meet performance requirements and help bring innovative products to market. Key Responsibilities Analog Circuit Design: Hands-on experience in analog circuit design, working on multiple analog building blocks, including LDO, high-speed TX and RX (Equalizer, Sampler, PI, Deserializer), Bias, and Reference circuits. PLL and Frequency Synthesis: Design and implement Analog and Digital PLLs for frequency synthesis and SerDes applications, including Charge Pumps, Loop Filters, VCO/DCO, PFD/TDC, and high-speed dividers. PLL Loop Dynamics: Model PLL Loop Dynamics, including sources of Jitter (RJ & DJ). Schematic to Post-Layout Verification: Take designs from initial schematic to post-layout verification, and ensure integration sign-off for post-silicon bring-up. Collaboration: Work closely with RTL, DD, PD, DV, and SoC Verification teams to integrate the PHY into SoCs. Minimum Qualifications Educational Background: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 3+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 2+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 1+ year of relevant work experience. Skills & Experience Analog Circuit Design: Hands-on experience with designing analog building blocks such as LDO, high-speed TX/RX, bias, and reference circuits. PLL Design: Strong background in Analog and Digital PLLs for frequency synthesis and SerDes applications. Charge Pump and VCO/DCO: Experience in designing charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers. Jitter and PLL Loop Dynamics: In-depth understanding of PLL loop dynamics, jitter modeling, and frequency synthesis for SerDes systems. Design Verification: Experience in taking designs from schematic through post-layout verification, integration, and post-silicon bring-up. Team Collaboration: Ability to work with cross-functional teams such as RTL, DD, PD, DV, and SoC verification teams to ensure smooth integration.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.

General Summary: Qualcomm is a company of inventors that has unlocked 5G, ushering in an era of rapid acceleration in connectivity and new possibilities across industries. But this is just the beginning. Qualcomm thrives on innovation and diversity, with teams made up of inventive minds from different backgrounds and cultures, all working together to transform cutting-edge technologies into world-changing products. As a GPU Functional Verification Engineer at Qualcomm, your responsibilities will involve a deep understanding of 3D Graphics hardware pipelines, feature sets, data paths, and block functionalities. You will play a key role in designing and developing verification strategies, implementing testbenches, and working on the functional verification of Qualcomm s Snapdragon SoC products. Key Responsibilities: Develop deep expertise in the 3D Graphics hardware pipeline, including feature sets, data paths, and block functionalities. Strategize, brainstorm, and propose Design Verification (DV) environments; develop testbenches and own test plans. Debug all RTL artifacts and work to achieve comprehensive signoff matrices. Collaborate with EDA vendors and explore innovative DV methodologies to push the limits of signoff quality. Partner with architecture, design, and systems teams globally to meet and exceed all project goals. Develop and execute UVM-based System Verilog testbenches for functional verification of complex GPU designs. Engage in property-based formal verification (knowledge of formal tools is a plus). Work on subsystem-level testbenches to analyze GPU workloads and ensure compliance. Utilize emulation platforms to analyze performance and identify potential pipeline bottlenecks. Perform power-aware and gate-level simulations to ensure high-quality GPU implementation. Implement Perl/Python scripts for regression management, optimizing runtimes, managing databases, and tracking bugs. Required Skills and Experience: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, or a related field, and 2+ years of relevant experience in Hardware Engineering or Design Verification. Master s degree in a related field and 1+ year of relevant work experience, OR PhD in a related field. Minimum 3 years of experience in design verification. Strong proficiency with UVM-based System Verilog testbenches. Experience with GPU pipeline design is a plus but not mandatory. Working knowledge of property-based formal verification tools is a plus. Strong communication skills (both written and verbal) with the ability to work in a collaborative team environment. Ability to learn quickly and deliver results with high quality. Desirable Skills and Aptitudes: Experience in GPU functional verification and knowledge of 3D graphics hardware pipelines. Familiarity with emulation platforms and the ability to analyze and address performance bottlenecks. Expertise in scripting with Perl and Python for automation and optimizing verification processes. Education Requirements: Bachelor s (BE/ME) or Master s (M.Sc.) degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or equivalent courses from reputed universities. Why Qualcomm? Be a part of a passionate GPU HW team dedicated to developing industry-leading Qualcomm Snapdragon SoCs. Play a pivotal role in shaping the future of mobile AR/VR by contributing to GPU solutions that drive benchmarks in the mobile computing industry. Qualification : Bachelors (BE/ME) or Masters (M.Sc.) degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or equivalent courses from reputed universities.

Job Function: As part of the Wireless R&D HW team in Bangalore, the candidate will contribute to the design and development of next-generation WLAN and micro-Wi-Fi subsystems for connectivity solutions in IoT, hearables, and wearables. This includes: Architecture and micro-architecture development. RTL design and integration. Collaboration with cross-functional teams for design convergence. Responsibilities: Develop micro-architecture and implement design using Verilog/SystemVerilog. Execute digital design (RTL) for complex WLAN subsystems involving multiple clock domains and low-power designs. Integrate and deliver WLAN subsystems to SoC-level designs. Collaborate with verification, SoC design, validation, synthesis, and physical design (PD) teams. Perform tasks such as linting (Spyglass), CDC analysis, synthesis, and simulation. Conduct RTL integration and work closely with DFT and PD teams for design-to-GDS convergence. Analyze tool reports (RDC, CLP, CDC, PrimeTime) and ensure compliance with design standards. Contribute to post-silicon debug and validation, when required. Maintain effective communication with global multi-site teams (US, UK, and India). Create and maintain documentation for design and development processes. Skills and Experience: ASIC Front-End Design: 8+ years of experience in digital ASIC design, with expertise in RTL coding using Verilog, VHDL, or SystemVerilog. Clock Domain Crossing (CDC): Strong experience in handling multiple clock domains and low-power design methodologies. Tool Proficiency: Hands-on experience with Spyglass Lint/CDC checks, DC-Compiler, PrimeTime, synthesis, simulation, etc. Protocols: Familiarity with AHB, AXI, and other standard bus protocols. WLAN/Wireless IP Expertise: Experience in 802.11/Wi-Fi subsystems is a plus. Debugging: Exposure to post-silicon debug and validation is desirable. Collaboration: Ability to work closely with multi-disciplinary teams for holistic design and development. Documentation: Strong documentation and communication skills. Minimum Qualifications: Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related fields and 3+ years of relevant experience. OR Master s degree in the same fields and 2+ years of experience. OR Ph.D. and 1+ year of experience. Experience Requirements: Strong background in ASIC front-end design, architecture, and RTL integration. Prior experience in WLAN IP/Sub-system design is a significant advantage. Why Join Qualcomm? Work on cutting-edge technologies like Wi-Fi 6/7/8 and next-gen connectivity solutions. Collaborate with diverse teams across geographies. Opportunity to contribute to groundbreaking innovations shaping the future of connectivity. Be part of an inclusive and forward-thinking culture. Qualification : Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communcations or related field.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.