Coverage Jobs in Bengaluru

Test Engineer (Senior QA Engineer / SDET) Department: R&D - Engineering Location: Bangalore About Acqueon: Acqueon is a leading provider of Generative AI-powered Revenue Execution Platforms. We empower customer-centric brands to orchestrate multi-channel campaigns and proactively engage consumers through voice, messaging, and email. Trusted by over 200 clients globally, we help enterprises elevate their customer experience, improve revenue recovery, increase sales, and build lasting loyalty. At the heart of Acqueon is a relentless focus on creating delightful, friction-free, and referral-worthy customer experiences using cutting-edge AI and data-driven technology. Position Overview: We are seeking a talented and experienced Senior QA Engineer / SDET to join our growing engineering team. This role focuses heavily on performance testing and test automation, ensuring our applications meet the highest standards of scalability, reliability, and usability. You will work in a collaborative environment with developers, DevOps engineers, and product teams, taking ownership of designing and executing complex test strategies using tools such as JMeter, Gatling, k6.io, and Selenium WebDriver. Key Responsibilities: Design, develop, and execute performance tests for web applications and backend APIs using JMeter, Gatling, or k6.io. Create realistic test scenarios and simulate workloads to evaluate system behavior under varying conditions. Conduct performance tuning and optimization, identify system bottlenecks, and provide recommendations for improvement. Work closely with development teams to analyze test results, diagnose issues, and drive resolutions. Build and maintain automation frameworks using Selenium WebDriver with Java, Cucumber, JUnit, TestNG, or Playwright. Contribute to the integration of performance and functional tests into CI/CD pipelines. Participate in architectural and design discussions to ensure performance considerations are included from the outset. Document test strategies, metrics, and findings, and communicate them clearly across teams. Required Qualifications: Bachelor s degree in Computer Science, Engineering, or a related field. 6 7 years of experience in performance testing and test automation. Strong hands-on experience with JMeter, Gatling, or k6.io. Expertise in building and executing performance test plans for web applications and APIs. Deep understanding of performance metrics, system tuning, and capacity planning. Proficiency in automation using Selenium WebDriver with Java, and frameworks like Cucumber, JUnit, TestNG, or Playwright. Solid knowledge of web technologies, protocols (HTTP/S), and application architecture. Strong analytical skills, attention to detail, and ability to work in dynamic, fast-paced environments. Excellent communication and collaboration skills. Preferred Experience: Experience with Agile/Scrum methodologies. Familiarity with CI/CD pipelines and tools like Jenkins, GitHub Actions, or GitLab CI. Exposure to cloud-based performance testing environments. Experience with monitoring tools (e.g., Grafana, Prometheus, New Relic) is a plus. What We Offer: A fast-paced, high-growth environment working on next-gen customer engagement products. The opportunity to work with cutting-edge technologies and global enterprise clients. A collaborative, people-first culture that values curiosity, ownership, and excellence. If you re passionate about quality, performance, and automation and love solving complex challenges we d love to hear from you. Qualification : Bachelors degree in Computer Science, Engineering, or a related field

Position: SQA/Test Automation Analyst Job Overview: We are looking for an experienced SQA/Test Automation Analyst to join our team. In this role, you will lead the end-to-end test automation process across various applications and systems. You should be proficient in test automation tools such as UFT, Selenium, or UiPath, and have hands-on experience with automation projects spanning different platforms such as Oracle EBS, SFDC, and web-based applications. Key Responsibilities: Lead end-to-end test automation efforts across applications and systems, ensuring comprehensive test coverage. Develop and execute automated test scripts using tools like UFT, Selenium, and UiPath. Collaborate with stakeholders to define test strategies, create test plans, and ensure the automation of relevant test cases. Provide test management oversight, track progress, and report key test metrics. Work on test documentation, including defect reporting, test execution results, and overall test status. Perform performance testing and actively contribute to performance test efforts across different applications. Leverage prior experience with Oracle ERP or SFDC applications to support testing initiatives. Analyze test results and work closely with development teams to identify, report, and resolve issues. Required Skills & Experience: 3-4 years of experience in test automation, covering a range of applications such as Oracle EBS, SFDC, and web-based platforms. Expertise in one or more test automation tools: UFT, Selenium, or UiPath. Familiarity with test management processes and test metrics to monitor and improve test quality. Prior exposure to Oracle ERP or SFDC applications is highly preferred. Hands-on experience with performance testing tools and techniques. Strong problem-solving skills, with the ability to work independently and as part of a collaborative team. Location: Bangalore, India (SKAV Seethalakshmi, GESC) Employment Type: Full-time Job Category: Information Technology

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Requirements: BE/BTech degree in CS/EE with 8+ years experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus. Qualification : BE/BTech degree in CS/EE

Job Title: Principal SDET Location: Bangalore (On-site; full-time) About Locus: At Locus, we are redefining logistics decision-making with deep-tech solutions that drive efficiency, consistency, and transparency across industries like retail and FMCG/CPG. Founded in 2015 by Nishith Rastogi and Geet Garg, Locus has evolved from a women s safety geo-tracking app into a globally recognized logistics optimization platform. Our technology has empowered enterprises such as Unilever and Nestl to execute over a billion deliveries across 30+ countries. Guided by our commitment to innovation and sustainable growth, we transform complex supply chains into strategic growth enablers. Join us at Locus and be part of a team shaping the future of global logistics. Job Overview: About the Role As a Principal SDET at Locus, you will play a critical role in driving the quality and reliability of our platform. This role goes beyond traditional testing; you will design, develop, and enhance automated test frameworks, ensure seamless integration of quality engineering practices, and mentor team members to establish a quality-first culture. Key Responsibilities: Automation Framework Design and Development: Architect, develop, and maintain robust test automation frameworks for backend, APIs, and frontend components. Ensure the frameworks are scalable, reusable, and aligned with the latest industry standards. Test Strategy and Planning: Collaborate with product managers, developers, and DevOps to define comprehensive test strategies for new features and system enhancements. Own the end-to-end testing lifecycle, from requirement analysis to test case creation, execution, and reporting. Drive better QA practices (In areas Like: defect creation, Capturing scope of feature, Sign offs , matrix of coverage in functional and automation etc) Quality Advocacy and Best Practices: Drive the adoption of best practices in testing, coding standards, and CI/CD processes across teams. Act as a champion of quality by fostering a quality-first mindset and instilling a culture of rigorous testing. Test Execution and Debugging: Conduct functional, performance, and security testing, ensuring the product meets the highest quality standards. Debug complex issues and work closely with developers to identify and resolve root causes. Continuous Improvement: Analyze test results and metrics to identify areas for improvement in testing processes and product quality. Contribute to the development and enhancement of monitoring and alerting systems to proactively address production issues. Mentorship and Collaboration: Mentor and guide junior SDETs and quality engineers, sharing knowledge and expertise to elevate the team s capabilities. Collaborate effectively with cross-functional teams to ensure quality is integrated into every stage of the development process. Develop a good understanding of velocity in teams and across the org and work towards removing roadblocks to improve release velocity Qualifications: 5-8 years of experience in software testing, with at least 3 years focused on test automation. Proficiency in programming languages such as Java, Python, or JavaScript. Hands-on experience with test automation tools and frameworks for Web and API automation like Selenium, Appium, TestNG, JUnit, or similar. Exp of working on any AI enabled testing tools or frameworks is a plus. Expertise in API testing and automation using tools like Postman, RestAssured, or equivalent. Familiarity with performance testing tools such as JMeter or Gatling. DevOps and CI/CD: Experience with CI/CD pipelines using tools like Jenkins, GitLab CI/CD, or GitHub Actions. Knowledge of Docker, Kubernetes, and cloud platforms (AWS, GCP, or Azure) is a plus. Strong debugging skills and the ability to identify root causes of issues quickly. Excellent communication, collaboration, and leadership skills. Experience in testing large-scale, distributed systems. Knowledge of security testing and tools like OWASP ZAP or Burp Suite. Exposure to machine learning models and their testing challenges. Join Locus and become part of a visionary team that is redefining logistics through innovation and smart distribution. We provide competitive compensation, comprehensive benefits, and a collaborative environment where your expertise will drive both your growth and that of the organization. Locus is an equal opportunity employer dedicated to creating a diverse and inclusive workplace.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Emulation Engineer Company Arm Location Bengaluru, India Job Overview Arm s Central Emulation team is excited to welcome experienced Emulation experts to join the team in Bengaluru. You will collaborate with design and verification engineers across the UK, US, India, and France to support advanced Compute Subsystems and SoC projects. Arm is building a team to develop exceptional silicon demonstrators based on Arm s IP compute sub-system solutions, targeting premium mobile, infrastructure, and automotive markets. Using the latest technology nodes (e.g., 3nm) and new 3D packaging innovations, Arm s goal is to demonstrate industry-leading performance by architecting, designing, implementing, and fabricating cutting-edge silicon test chips. This initiative brings together innovative talent and expertise from across the semiconductor industry to shape the next generation of compute on Arm devices. Responsibilities Collaborate with end users to understand system use cases and guide validation efforts. Ensure tight integration between hardware qualification and final application use models. Work in an exciting emulation environment using hybrid and virtual solutions, integrating industry-standard high/low-speed IO IPs into subsystems and SoCs. Engage from early architecture and design phases to pre-silicon validation and post-silicon validation on emulation platforms. Drive pre-silicon emulation across all SoC teams. Ensure design quality and debuggability by collaborating closely with the design team. Support architecture, verification, system validation, performance, power, and DFT teams with insights from performance and power characterization. Develop comprehensive pre and post-silicon test plans in collaboration with verification teams. Develop tests, create bare-metal drivers for industry-standard IO IPs, and build frameworks to enable scalable testing across multiple ASIC projects. Required Skills and Experience Bachelor s degree (BE/BTech) in Electronics Engineering. 8+ years of experience in Pre-Silicon Validation and Emulation/FPGA-based platforms. Experience developing C/C++/SystemC tests for HDL-HVL co-emulation platforms. Proficiency in IO bus protocols such as I2C, SPI, USB, and/or PCIe. Experience with SoC debugging tools such as JTAG and Trace32. Nice-to-Have Skills and Experience Knowledge of ASIC design and prototyping flows. Experience with SystemC/C/C++ and UVM/SystemVerilog (SV) verification languages. Familiarity with domains such as PCIe, Flash, Memory, CPU, GPU, and DRAM. Hands-on experience with emulation toolchains such as Zebu, Veloce, or Palladium. What Arm Offers Arm is committed to global talent acquisition, offering an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace where everyone can thrive, Arm encourages its people to make exceptional contributions to its global success. #LI-KR2 Qualification : Bachelors degree (BE/BTech) in Electronics Engineering.

CPU Verification Engineer Company Arm Location Bengaluru Job Overview Responsibilities Contribute technically as part of project teams to deliver high-quality ARM CPU designs. Execute comprehensive CPU design verification, focusing on improving design quality through stress testing and bug identification. Effectively plan, conduct reviews, provide status updates, and meet delivery expectations. Collaborate with design and architecture teams to ensure effective coverage and provide accurate project planning inputs. Design and develop verification testbenches and components required for effective verification. Maintain knowledge of company processes to work effectively within defined standards and methodologies. Drive efficiency improvements in verification tools and methodologies and mentor team members to support career development. Required Skills and Experience 3+ years of experience in CPU, IP, or SoC product development environments. Experience in design verification/validation, including developing test plans, testbenches, and executing measurable verification processes. Familiarity with processor verification using assembly language and C/C++. Knowledge of microprocessor and/or SoC architecture and microarchitecture, preferably ARM processors and ARM-based systems. Strong problem-solving and debugging skills, with a commitment to continuous improvement. Nice-To-Have Skills and Experience Strong understanding of CPU architecture and microarchitecture. Experience with ARM-based system designs and hierarchical memory systems. Programming languages: Verilog, Assembly, C/C++, Perl, Python. Experience with verification languages such as SystemVerilog. Familiarity with power-aware verification methodologies. What Arm Offers This is a fantastic opportunity to shape the future of CPU verification at Arm while advancing your own career. Join our CPU design verification team and play a key role in delivering Arm's strategic goals! #LI-KR2

The Cisco Security Business Group (SBG) is committed to empowering the world to reach its full potential securely. We achieve this by delivering industry-leading security solutions that protect organizations and individuals from cyber threats. The SBG Security team plays a critical role in this mission by building strong internal partnerships, aligning security strategies across the SBG portfolio, and delivering simple, effective security solutions that meet market and industry expectations. Our team enables internal development teams to securely create and deploy Cisco Secure products, including Duo, Umbrella, SecureX, Talos, Cisco Secure Connect, StealthWatch, Tetration, and more. What You ll Do Collaborate with Product Management, UX, and Development teams to define scope, estimate work, and drive automation initiatives. Contribute to proof-of-concepts (POCs) and conduct quantitative and qualitative technology comparisons. Design, develop, and maintain automation scripts for security-focused applications. Mentor and guide junior engineers, fostering best practices in automation and testing. Define the UI and API automation strategy, working closely with development, product, and QA teams. Identify test cases and scenarios based on product requirements. Develop and maintain automation test scripts to ensure seamless CI/CD integration. Execute and monitor automated test cases, reporting bugs and generating test reports. Investigate and troubleshoot software issues arising from testing. Enhance existing regression test suites for efficiency and comprehensive coverage. Implement CI/CD pipelines to integrate automation test suites with development workflows. Identify and integrate new automation tools, driving an automation-first strategy. Independently manage QA programs, ensuring robust test coverage and quality standards. Evaluate and set up automation frameworks/tools for various projects. Effectively communicate with cross-functional stakeholders to drive quality and efficiency. Who You Are Strong experience in automation testing using tools like Playwright, Cypress, Selenium, or WebDriver IO. Solid understanding of software QA methodologies, tools, and processes within SDLC (Agile, Sprint, etc.). Proficiency in programming concepts, with expertise in JavaScript, TypeScript, Python, or Java (JavaScript/TypeScript preferred). Experience in test automation script development and standard automation frameworks. Skilled in test suite optimization for coverage, efficiency, and execution speed. Familiarity with CI/CD tools like Maven, Jenkins, GitHub, and related build/deployment processes. Hands-on experience with API testing (HTTP, RESTful web services) and API automation tools. Experience in database testing with SQL, MongoDB, or similar databases. Nice to have: Experience in performance testing with tools like JMeter. At Cisco, we are shaping the future of secure connectivity with cutting-edge innovations. We believe in fostering a culture where employees can thrive, grow, and make an impact. Innovation & Growth: Work on industry-leading security solutions that safeguard the digital world. People-First Culture: We celebrate diversity, individuality, and collaboration to drive meaningful change. Giving Back: Employees receive dedicated time off for volunteering, supporting causes they are passionate about. A Place to Belong: Our 30+ Inclusive Communities empower employees to connect and grow in an inclusive environment. We welcome your unique perspective whether you're a tech enthusiast, problem-solver, or innovator, bring your passion to Cisco Secure and help shape the future of security! Take the next step. Be you, with us!

Job Description You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.As a DFT engineer Direct Responsibilities of the role, but not limited to: Working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus. Qualifications Candidate must possess a master's degree in Electronics or Computer Engineering with at least 5 or more years of experience or a bachelor's degree with at least 7 years of experience of DFT experience. Strong knowledge of ATPG, various fault models, fault grading. Knowledge of memory BIST, IJTAG/TAP architecture. DFT logic generation, integration, and verification. EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring up preferably Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer. Post Silicon/ATE Bring-Up Support. Experience with RTL (Verilog, System Verilog, VHDL). Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Candidate must possess a master's degree in Electronics or Computer Engineering with at least 5 or more years of experience or a bachelor's degree with at least 7 years of experience of DFT experience.

Job Description Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans to include definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications M Tech with 2 years of experience / B Tech with 3+ years of experience. Electrical & Electronics / Communication Engineering Hands on Experience on verification of IPS / Min 1 years hands on experience on formal verification Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : M Tech with 2 years of experience / B Tech with 3+ years of experience.

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years Track record of 'first-pass success' in ASIC development cycles Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle At least 9+ years of hands on experience Preferred Qualifications Experience in development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet Experience working across and building relationships with cross-functional design, model and emulation teams Qualification : Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years

We are seeking a highly skilled and experienced DFT Engineer to join our team. The ideal candidate will have a strong background in Design for Testability (DFT) methodologies and implementation, with a deep understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). The role will involve developing and implementing DFT strategies for complex mixed-signal integrated circuits (ICs), ensuring high fault coverage and testability. ASIC Implementation DFT Responsibilities Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test. Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns. Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement. Generate high-quality test patterns using automated test pattern generation (ATPG) tools. Verify the correctness of DFT implementation through simulation and hardware testing. Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process. Minimum Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering. 10+ years of experience in DFT for mixed-signal ICs. Understanding of DFT concepts, including scan insertion, BIST, and boundary scan. In-depth knowledge of DFT EDA tools (Siemens/Synopsys). Familiarity with IEEE standards 1149, 1500, and 1687. Experience with fault simulation and coverage analysis tools. Problem-solving and analytical skills. Strong communication skills Work independently and as part of a team. Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation. Preferred Qualifications Master's degree in Electrical Engineering or Computer Engineering. Experience with mixed-signal DFT methodologies. Knowledge of scripting languages (e.g., Perl, Python) for automation. Experience with hardware testing and debugging. Qualification : Bachelor's degree in Electrical Engineering or Computer Engineering.

Associate Principal Graphic Designer Location: Bangalore About Tekion Tekion is transforming the automotive industry with the first cloud-native automotive platform, connecting OEMs, dealerships, technology partners, and consumers. Through our Automotive Retail Cloud (ARC), Automotive Enterprise Cloud (AEC), and Automotive Partner Cloud (APC), we deliver seamless digital experiences powered by big data, AI, and machine learning. Tekion employs ~3,000 people across North America, Asia, and Europe, driving innovation in a fast-moving industry. Role Overview We are seeking an Associate Principal Graphic Designer who can combine strategic thinking with exceptional design execution. You will own the visual identity across digital platforms, collaborate with marketing, communications, and leadership teams, and mentor a small design team. This is a leadership role for someone passionate about building and scaling a high-performing design practice in a fast-paced tech company. Key Responsibilities Brand Vision & Consistency Maintain and evolve the brand s visual standards. Build and manage design systems, guidelines, components, and patterns for consistency across all channels. End-to-End Creative Leadership Lead projects across web, mobile, and marketing campaigns, from concept to final launch. Collaborate with marketing, communications, product, and leadership to create designs that drive business impact. Ideation & Storytelling Research and translate concepts into actionable designs. Present and defend design decisions to designers, marketers, and executives. Team Leadership & Growth Mentor and coach a small design team to improve skills, maintain quality, and develop accountability. Review all design work before release to ensure consistency and quality standards. Systems & Workflow Innovation Build efficient workflows and scalable design systems to increase team output without compromising quality. Strategic Design Advocacy Represent design in cross-functional and executive meetings. Connect design decisions to business goals such as brand perception, adoption, and revenue. Requirements 5+ years of hands-on experience in visual and brand design in tech or SaaS. Proven experience leading or managing designers and owning project outcomes. Expertise in Figma and Adobe Creative Suite; familiarity with motion, prototyping, and collaboration tools is a plus. Strong portfolio demonstrating strategic thinking, storytelling, and high design craft. Ability to build and scale brand identities, logos, and web experiences across enterprise audiences. Excellent communication and executive presence to align teams around shared vision. Track record of end-to-end project execution, from brief to delivery. Passion for staying ahead of design, product, and culture trends. High accountability, ownership, and commitment to quality standards. Perks & Benefits Competitive compensation & stock options Medical insurance coverage Opportunity to work with some of the brightest minds in Silicon Valley Lead and grow a high-performing creative team in a fast-moving tech environment

Sr. Member of Technical Staff - UI Engineering Location: Bengaluru Company: Aviatrix Experience: 3+ years About Aviatrix: Aviatrix is a leading cloud network security company trusted by over 500 enterprises globally. We specialize in simplifying and securing multi-cloud environments, providing a unified networking solution built specifically for the cloud. Role Overview: UI Engineering (Co-Pilot Team) We are seeking a Senior UI Engineer to join our Co-Pilot product development team. You will design, develop, and maintain high-quality UI solutions that offer customers seamless access to sophisticated cloud management and network security tools. Technical Requirements Core Competencies: Frontend Stack: Advanced proficiency in TypeScript, React, and Node.js. Web Standards: Expert knowledge of HTML5 and CSS3. API Integration: Solid understanding of REST APIs and asynchronous data handling. Version Control: Professional experience with Git and collaborative workflows. Education: BE/B.Tech in Computer Science or related field (or equivalent practical experience). Nice to Have / Bonus Skills: Design Systems: Experience with MUI (Material UI) or in-house design frameworks. Advanced Protocols: Exposure to gRPC, gRPC-web, and Go. Data Visualization: Familiarity with Elasticsearch and high-scale data dashboards. Cloud Domain: Previous experience in cloud networking or security sectors. Key Responsibilities Feature Development: Build efficient, scalable, and well-tested code for the Aviatrix product suite. UX Partnership: Collaborate with UX designers to translate complex requirements into intuitive user interfaces. System Maintenance: Manage bug fixes, UI enhancements, and participate in on-call rotations for field issues. Continuous Improvement: Contribute to the evolution of development processes and product quality. Benefits & Why Aviatrix Comprehensive Health: Private medical coverage, life assurance, and long-term disability. Financial & Growth: Pension scheme and a dedicated annual wellbeing stipend. Time Off: Generous holiday allowance and a flexible approach to work-life balance. Inclusivity: We value unique journeys if you are excited by the role, we encourage you to apply regardless of a perfect "checklist" match.

Staff Engineer - Software Development (Cloud AI & Network Security) Location: Bengaluru Company: Aviatrix Experience Required: 7+ Years About Aviatrix: Aviatrix is a global leader in cloud network security, trusted by over 500 enterprises. We provide a specialized platform for securing multi-cloud environments, giving organizations the control and visibility needed to modernize their cloud strategies. Architectural Focus & Impact As a Staff Engineer, you will architect and deliver advanced AI-driven network security solutions. This role bridges the gap between Distributed Systems (Python/Go), Real-time Telemetry, and LLM-integrated automation to build self-learning, adaptive security infrastructures. Technical Expertise Core Software Engineering: Languages: Deep proficiency in Python and Go (Golang). Distributed Systems: Mastery of Kubernetes, Microservices, and high-scale observability (Prometheus, ELK). Data Pipelines: Experience with real-time stream processing using Kafka, Flink, Kinesis, or Pub/Sub. Networking & Security Domain: Cloud Infrastructure: Expert knowledge of VPC/VNet design, Routing, Load Balancers, and Overlays. Firewall Technologies: Hands-on with Deep Packet Inspection (DPI), NGFW/IDS/IPS, and Cloud-native firewalls (AWS, Azure, GCP). Security Frameworks: Alignment with Zero Trust, NIST CSF, and CIS Benchmarks. AI & Machine Learning Integration: Model Serving: Experience serving ML models via REST or gRPC. Generative AI: Familiarity with LLM integration, RAG (Retrieval-Augmented Generation), LangChain, and vector databases. Key Responsibilities System Architecture: Lead the design of cloud-native microservices for security control planes. AI-Driven Features: Integrate LLMs for Natural Language-to-Firewall Rule translation and automated incident summarization. Technical Leadership: Mentor junior engineers and set high standards through rigorous Design and Code Reviews. Cross-Functional Collaboration: Partner with Data Scientists and Cloud Networking teams to deliver production-grade AI features. Benefits & Why Join Us Regional Package: Comprehensive pension, private medical coverage, and life assurance. Wellbeing: Annual wellbeing stipend and generous holiday allowance. Growth Culture: We value unique career paths and prioritize candidates who are passionate about the intersection of AI and Security.

Staff Engineer Solutions Automation (NMS/SMx) Location: Bangalore Type: Full-Time Experience Required: 12+ Years (QA Lead/Architect level) Role Overview: Strategic Quality Leadership We are seeking a Staff Engineer to lead Solutions Test Automation for our next-generation Network Management System (SMx). This is a high-impact, strategic role requiring a deep mastery of networking protocols and modern GUI automation. You will drive complex automation projects, mentor junior engineers, and integrate AI-driven tools to redefine our testing methodologies and product reliability. Technical & Domain Expertise Networking & Fiber Optics: L2/L3 Protocols: Strong understanding of OSPF, BGP, ISIS, VLAN, and VRF. Protocol Mastery: Expert knowledge of Ethernet, TCP/IP, and SNMP. Telecom Infrastructure: Experience with fiber optics technology such as GPON and XGSPON is a significant advantage. Automation Stack: Frameworks: Proficiency in Robot Framework, PYART, and Playwright. GUI & API Testing: Extensive experience developing automated tests for complex enterprise GUI applications. Programming: Strong Python proficiency for script and framework development. DevOps Integration: Ability to integrate automated suites into CI/CD pipelines (Jenkins, GitLab) using Docker/Kubernetes. Key Responsibilities Leadership & Mentorship: Team Guidance: Mentor junior engineers, conduct rigorous code reviews, and foster a culture of technical excellence. Project Ownership: Drive the full automation lifecycle from strategy and environment planning to execution and results analysis. Innovation & Quality: AI-Driven Testing: Incorporate AI/ML tools (self-healing tests, visual validation) to enhance efficiency. Scenario Design: Leverage domain expertise to design realistic network topologies and simulate complex customer use cases. Continuous Improvement: Propose and implement enhancements in tools and methodologies to increase test coverage and reliability. Qualifications & Preferred Skills Experience: 12+ years in QA/Test Automation with a track record in progressively responsible leadership roles. Education: Bachelor s or Master s in Computer Science, Telecommunications, or a related field. Certifications (Preferred): CCNA, CCNP, or ISTQB Advanced Test Manager. Industry Context: Prior experience with NMS/EMS products (e.g., Calix AXOS, Cisco Prime) or OSS/BSS systems is a major plus. Soft Skills for Success Communication: Ability to explain complex technical networking concepts to non-technical stakeholders. Proactiveness: Staying updated on the latest industry trends and experimenting with new tools. Collaboration: A team player comfortable working in a hybrid environment with global teams. Qualification : Bachelors or Masters in Computer Science, Telecommunications, or a related field

Senior Manager, Security Operations Center (SOC) Location: Bangalore Type: Full-Time Experience Required: 8+ Years (3+ in Leadership) Role Overview: Strategic Cyber Defense We are seeking a Senior Manager to lead and modernize our SOC operations across enterprise and product environments. You will oversee a high-performance team dedicated to threat detection, advanced detection engineering, and incident response. This role is a strategic blend of technical mastery leveraging AI and SOAR and people leadership, focused on building a resilient, automation-first security culture. Core SOC Service Offerings & Expertise Advanced Defense & Detection: Detection Engineering: Implement Detection-as-Code practices and prioritize backlogs based on the evolving threat landscape. Threat Intelligence & Hunting: Deliver actionable intel and execute structured threat hunting hypotheses to proactively identify stealthy adversaries. Deception & Validation: Manage deception strategies (honeypots/tokens) and use attack emulation tools to validate detection logic effectiveness. Forensics: Lead digital forensic investigations, evidence acquisition, and post-incident analysis. Automation & Technology Stack: Azure Ecosystem: Advanced proficiency with Microsoft Sentinel, Defender XDR, and Defender for Cloud using KQL. Cloud Operations: Strong knowledge of security operations across Azure, AWS, and preferably GCP. SOAR & AI: Champion the integration of Security Orchestration, Automation, and Response (SOAR) and AI to drive SOC efficiency. Key Responsibilities Leadership & Strategy: Team Development: Coach and mentor the SOC team, conducting regular 1-on-1s and fostering a growth-oriented culture to prevent burnout. Roadmap Execution: Help define a comprehensive SOC strategy and maturity framework aligned with organizational risk management. Stakeholder Liaison: Act as a trusted advisor to Product, IT, and Development leaders to integrate security into cross-functional workflows. Metrics & Operational Excellence: Data-Driven Reporting: Develop dashboards (e.g., Power BI) to track KPIs, KRIs, and detection coverage. Incident Lifecycle: Lead the lifecycle of escalated incidents, conduct root cause analysis, and execute tabletop exercises. 24/7 MDR Strategy: Define operational procedures for Managed Detection and Response (MDR) and sustainable on-call rotations. Qualifications for Success Proven Leadership: 8+ years in InfoSec with specific experience leading SOC or MDR functions. Azure Mastery: Deep technical expertise in the Microsoft security stack. Framework Knowledge: Familiarity with MITRE ATT&CK, Purple Teaming, and cloud-native detection. Soft Skills: Exceptional ability to simplify complex technical content for executive-level communication.

Job Overview: The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arm s future architecture roadmap. In ATG, we are developing world-leading Secure CPU and System architectures and associated technologies; enabling our ecosystem to build compelling products. Along with the architecture definition, ATG develops products to confirm compliance to the architecture. The ATG team located in Bangalore develops a product called Architecture Compliance Kits (ACK) that are delivered to multiple internal and external CPU design teams to validate that Arm architecture CPU implementations are compliant with the Arm architecture. You will learn Arm Architecture and apply it along with hardware and software verification skills to develop products for verifying the Architecture. You will develop good engineering and technical skills, and a fair understanding of CPU architecture and microarchitecture. You will connect with a wide range of teams within ATG, architects, and with our external partners. In this role, you will also develop solutions for future Arm architecture developments and influence the product offering. Responsibilities: Technical expertise, understanding architecture definitions, carrying out investigations and feasibility studies, defining and developing verification strategies, and contributing to the development of compliance products. Design verification test plans and test cases in assembly, C, HVL, and higher abstraction languages using automation techniques as needed. Strong and continuous communication on deliveries and risks, ensuring that all engineering commitments are delivered successfully. Drive efficiency improvements through adoption of the right development flows and methodologies. Excellent verbal and written communication skills. Required Skills and Experience: B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering. 8+ years of verification experience (CPU/complex IP verification is a plus). Strong understanding of computer architecture. Proficiency in logical programming using C/C++/Assembly with experience in adopting software engineering best practices. Nice To Have Skills and Experience: Experience in CPU verification would be a plus. Knowledge of x86 or Arm processor architecture. We are guided by our core beliefs that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and craft outstanding products and careers. In Return: We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to complex core implementation to full custom physical IPs, here you'll have our backing to push limits in vital areas. #LI-KR2 Qualification : B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering.

Job Title: Senior ATE Test Engineer Manufacturing & Product Engineering Job Description: Intel is seeking a Senior ATE Test Engineer to drive the testability and manufacturability of integrated circuits from feasibility to high-volume production (HVM). The role involves developing and validating test methodologies, debugging functionality and performance issues, and optimizing test processes for yield and cost efficiency. The engineer will work closely with design, process development, fab, assembly, and manufacturing teams to ensure seamless production ramp-up and quality assurance. Key Responsibilities: Test Development & Debugging: Design, develop, and validate testability circuits and test flows for new products. Debug functionality and performance issues to root cause using Automatic Test Equipment (ATE). Interface with design, DFx (Design for Test, Debug, Manufacturing), and product teams to drive test development. Manufacturability & High-Volume Ramp (HVM): Collaborate with fab, assembly, test factories, and quality/reliability teams to enable smooth production ramp-up. Perform ATE device characterization, define datasheet specifications, and conduct yield analysis. Analyze early customer returns and drive test hole closure activities to enhance quality and reliability. Production Test Optimization: Drive test time reduction by analyzing fallout data and balancing product cost optimizations. Implement bin split and die-level cherry-pick (DLCP) strategies to optimize product supply. Ensure manufacturability through process and spec corner analysis to resolve yield issues before mass production. Hardware & Software Development: Develop and debug complex software programs for test conversion and test automation. Create and validate test hardware solutions for production testing. Optimize component production relative to quality and cost constraints. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields. Technical Expertise: ATE Test Engineering: Strong expertise in Automatic Test Equipment (ATE) development and debug. DFT & Test Methodologies: Knowledge of DFT architectures and methodologies including Analog DFT, JTAG, etc. Understanding of test engineering processes and tester debugging techniques. Debugging & Validation: Hands-on experience with design/validation and advanced debugging skills. Expertise in Advantest 93K, Teradyne Ultraflex, J750, and related test platforms. Manufacturing Process & Yield Analysis: Experience in yield analysis, bin splitting, and test time optimization. Ability to analyze process corners and drive manufacturing readiness. Soft Skills: Excellent problem-solving skills, teamwork, and communication. Strong interpersonal and planning skills for cross-functional collaboration. About Intel s Manufacturing & Product Engineering (MPE) Group: The MPE team is responsible for test development across Intel s product segments, contributing to 95% of Intel s revenue. The team delivers pre-production test suites and physical debug capabilities to enable high-quality, high-volume manufacturing. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates. Intel offers a competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields.

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience