Design Closure Jobs in Bengaluru

Business Development Manager Software Sales Department: Sales Location: Bangalore Experience: 4 6 Years Job Description We are seeking an experienced and results-driven Business Development Manager Software Sales to drive revenue growth by selling Dassault Syst mes and MSC Software products to commercial and government clients across Karnataka. The ideal candidate will have a strong background in CAD/CAM/CAE software sales, with the ability to build and manage key client relationships. Key Responsibilities Identify, engage, and develop new business opportunities with commercial enterprises, government agencies, and educational institutions. Promote and sell CAD/CAM/CAE solutions including Dassault Syst mes, MSC Software, and other industry-standard platforms. Build and maintain strong relationships with key decision-makers and stakeholders. Understand customer requirements and propose software solutions that address their design, simulation, and manufacturing needs. Meet or exceed assigned sales targets and contribute to the overall growth strategy. Conduct product presentations, demos, and follow-ups to close sales. Maintain detailed records of sales activities in CRM tools and provide regular forecasts and reports. Collaborate with technical teams for pre-sales support and solution implementation. Requirements Qualifications: Bachelor s degree or diploma in Engineering (preferably Mechanical), Business Administration, or related fields. MBA in Marketing is a plus. Experience: 4 6 years of experience in software sales, specifically in CAD/CAM/CAE products such as Siemens NX, Solid Edge, CATIA, SolidWorks, Pro-E, Ansys, Altair, or similar. Proven track record in selling to large commercial organizations, SMEs, government agencies, and academic institutions. Skills: Strong understanding of the CAD/CAM/CAE software market. Excellent communication, negotiation, and interpersonal skills. Ability to work independently and manage client relationships effectively. Self-motivated, target-driven, and highly organized. Qualification : Bachelors degree or diploma in Engineering (preferably Mechanical), Business Administration, or related fields

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Job Title: Associate Credit Card Operations Location: Bengaluru, India Employment Type: Full-time About Zeta Zeta is a Next-Gen Banking Tech company transforming how banks and fintechs design and launch modern financial products. Founded in 2015 by Bhavin Turakhia and Ramki Gaddipati, Zeta s flagship platform, Tachyon, is the industry s first fully cloud-native and API-enabled banking stack. It integrates issuance, processing, lending, fraud & risk, and more into a single-vendor platform. With over 15 million cards issued globally, Zeta enables banks to deliver: Rich, digital-first experiences Hyper-personalized card programs Rapid deployment via web-based product configurators API-based innovation and scalability Intuitive, modern back-office systems Advanced regulatory and compliance tools We re trusted by major banks and fintechs globally and backed by investors like SoftBank and Mastercard, with a $1.5 billion valuation and a team of 1700+ employees, over 70% in R&D. About the Role Zeta is collaborating with HDFC Bank to manage and operate a modern credit card program built on the Zeta Platform. We are seeking dynamic professionals to join our Credit Card Business Operations Unit, supporting critical functions such as onboarding, dispute handling, reconciliation, and end-to-end lifecycle management of credit card customers. This is an exciting opportunity to be part of a growing, innovation-driven team that is reshaping banking operations. Key Responsibilities Operations Oversight: Monitor and resolve onboarding, delivery, and dispatch issues for new credit card customers. Dispute & Fraud Resolution: Handle fraud and dispute cases in compliance with process and regulatory timelines. Reconciliation & Settlement: Manage transaction settlement processes and ensure accurate reconciliation of accounts. Lifecycle Management: Oversee credit card lifecycle processes, including account maintenance, repayment tracking, credit balance refunds, and closures. Stakeholder Coordination: Collaborate with internal and external teams (e.g., product, engineering, bank partner) to resolve operational issues effectively and on time. Skills & Competencies Strong communication and interpersonal skills. Customer-first mindset with a proactive problem-solving approach. High level of accountability and attention to detail. Ability to manage time effectively in a fast-paced and dynamic environment. Qualifications & Experience Education: Graduate degree in any discipline. Experience: 1 5 years of relevant experience in Credit Card Operations, Customer Servicing, or Banking Operations. Prior exposure to onboarding, dispute management, settlements, and lifecycle operations in cards domain is highly preferred. Equal Opportunity Statement Zeta is an equal opportunity employer. We celebrate diversity and are committed to building an inclusive environment for all employees. We encourage individuals from all backgrounds, communities, and identities to apply. Qualification : Graduate degree in any discipline.

Senior Customer Success Engineer II Bangalore (EST Shift) Location: Bangalore, India Shift: EST Hours About Rubrik s Global Customer Support & Success Team Rubrik s Global Customer Support and Success Organization is dedicated to delivering a world-class post-purchase experience. Our team provides comprehensive post-deployment technical support across a diverse set of technologies and cloud environments. We ensure timely activation and adoption of Rubrik s SaaS products and technologies to deliver maximum value. As a vital member of this team, you will serve as a trusted advisor and key point of contact for customers and partners, working closely with cross-functional teams to ensure customer success. In a data-driven world, Rubrik s Customer Support Team is the backbone of data security strategies, leveraging deep technical expertise in data management, protection, and recovery to swiftly resolve complex issues while maintaining exceptional customer experience. Role Overview As a Senior Customer Success Engineer II, you will provide enterprise-level technical support to customers through multiple channels including phone, web, email, and chat. You will deliver effective solutions to technical and non-technical users while supporting a broad range of cloud and technology deployments. Key Responsibilities Manage and resolve technical support cases from basic queries to advanced troubleshooting involving complex issues. Analyze and isolate root causes using structured troubleshooting and problem analysis techniques. Independently diagnose and resolve problems within the customer s environment, escalating when necessary. Provide expert advice on cloud infrastructure services and best practices. Research, troubleshoot, and resolve escalated customer issues promptly and accurately. Ensure detailed documentation, recording, and closure of all cases. Collaborate with internal teams (escalations, engineering, etc.) to facilitate clear communication and resolution. Contribute technical content to Rubrik s Deployment Guides, Knowledge Base, and FAQs. Demonstrate strong case management skills to proactively resolve issues and maintain high customer satisfaction. Create technical designs and documentation related to cloud deployment architectures. Required Experience & Skills 8+ years of experience in enterprise technical support, DevOps, or related fields. Expertise in troubleshooting advanced issues such as snapshots, replication, data recovery, cloud deployments, networking, and VMware administration. Strong problem-solving skills with ability to work independently. Proficient knowledge of VMware, Linux, Kubernetes, Google Cloud Platform, AWS, Azure, Office 365 API, databases (preferably MS SQL), scripting languages (Python, Perl), automation, microservices architecture, SaaS systems, and cloud application management. Hands-on experience with cloud deployments and infrastructure. Ability and willingness to learn and adapt across a broad technology stack. Comfortable filing bugs and collaborating with engineering teams to reproduce and resolve issues. Bachelor s degree in Computer Science, Engineering, or a related field. Rubrik (NYSE: RBRK) is committed to securing the world s data with its industry-leading Zero Trust Data Security approach. Our Security Cloud, powered by machine learning, protects data across enterprises, clouds, and SaaS applications. We empower organizations to maintain data integrity, ensure availability during disruptions, continuously monitor risks, and quickly restore business operations in the event of cyberattacks or failures. Qualification : Bachelors degree in Computer Science, Engineering, or a related field.

Sr. Manager, Internal Audit Location: Bengaluru, India Company: ShopUp HQ Role Overview The Senior Manager of Internal Audit will lead the planning, execution, and reporting of audits across multiple departments. This role focuses on evaluating risk management processes, internal controls, and compliance with both organizational policies and external regulations. The ideal candidate will bring extensive experience auditing FMCG companies and distribution operations, with a strong emphasis on process improvement, regulatory adherence, and supporting organizational governance. Key Responsibilities Plan, lead, and conduct internal audits across departments to assess risks, control effectiveness, and compliance with policies and regulations. Perform targeted audits related to FMCG and distribution house operations, addressing operational risks and process inefficiencies. Analyze current business processes to identify inefficiencies or risk areas, and recommend actionable process improvements. Develop and implement audit strategies, methodologies, and frameworks aligned with organizational objectives. Collaborate with internal stakeholders to communicate audit findings, provide guidance, and drive timely corrective actions. Prepare comprehensive audit reports, highlighting key risks, gaps, and recommendations for senior management and leadership. Track and monitor the implementation of audit recommendations and follow-up actions to ensure closure. Design and deliver training programs to foster awareness of internal controls, risk management, and compliance culture throughout the company. Conduct field visits and on-site audits as per the audit calendar and perform unannounced surprise audits. Qualifications & Experience Professional Experience: Minimum 8 years of experience in Internal Audit, risk management, compliance, and process improvement. Hands-on experience auditing FMCG companies and distribution-heavy operations is strongly preferred. Educational Qualifications: Bachelor s degree in any discipline with a strong academic record. Qualification : Bachelors degree in any discipline with a strong academic record.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Job Title: Delivery Manager Experience: 12 to 15 years Education: Bachelor s degree (Engineering or Non-Engineering) Who We Are: HashedIn by Deloitte is a born-in-the-cloud technology firm, specializing in leveraging cloud-native technologies to build innovative, market-leading solutions. Since inception, HashedIn has successfully delivered solutions to over 100 customers across industries and geographies, helping them launch new products, disrupt industries, and scale operations. With a team of 900+ Hashers, we are proud to be recognized as a Great Place to Work multiple times, fostering a culture that promotes freedom to experiment, continuous learning, and fun at work. Role Overview: As a Delivery Manager, you will be responsible for managing and driving multiple project deliveries across various customers and geographies. This role demands strong leadership, project management expertise, technical understanding, and the ability to align delivery processes with business goals. Key Responsibilities: Own and manage delivery for multiple projects simultaneously. Define project roadmaps aligned with key business objectives. Lead both onshore and offshore teams, managing project schedules, scope, and delivery plans. Define and manage project scope, budget, and timelines from initiation to closure. Identify, anticipate risks and issues, and proactively work towards resolution to ensure successful delivery. Collaborate with Recruitment & Operations to ensure projects are adequately staffed with the right talent. Conduct regular team meetings to monitor progress, manage escalations, and align on project priorities. Ensure efficient and cost-effective delivery processes across projects. Act as the single point of contact for delivery, representing HashedIn to clients and stakeholders. Manage project profitability, ensuring that each project operates as a profit center. Own and drive delivery excellence in a global delivery model (onshore-offshore). Lead and coordinate crisis management when required. Desired Profile: 12 to 15 years of hands-on project delivery experience. Solid understanding of Agile methodologies and software development lifecycle. Strong grasp of OOP concepts, architectural design patterns, and data structures. Extensive experience with any technology stack, such as MEAN, .NET, or Java. Proven experience in project planning, budgeting, and milestone tracking. Excellent problem-solving skills, with the ability to build contingency plans and handle high-pressure situations professionally. Strong negotiation, presentation, and communication skills. Experience acting as the primary delivery contact for customers, representing the delivery team in client conversations. Ability to drive delivery governance processes across teams and ensure alignment with organizational goals. Qualification : Bachelors degree (Engineering or Non-Engineering)

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: Senior ATE Test Engineer Manufacturing & Product Engineering Job Description: Intel is seeking a Senior ATE Test Engineer to drive the testability and manufacturability of integrated circuits from feasibility to high-volume production (HVM). The role involves developing and validating test methodologies, debugging functionality and performance issues, and optimizing test processes for yield and cost efficiency. The engineer will work closely with design, process development, fab, assembly, and manufacturing teams to ensure seamless production ramp-up and quality assurance. Key Responsibilities: Test Development & Debugging: Design, develop, and validate testability circuits and test flows for new products. Debug functionality and performance issues to root cause using Automatic Test Equipment (ATE). Interface with design, DFx (Design for Test, Debug, Manufacturing), and product teams to drive test development. Manufacturability & High-Volume Ramp (HVM): Collaborate with fab, assembly, test factories, and quality/reliability teams to enable smooth production ramp-up. Perform ATE device characterization, define datasheet specifications, and conduct yield analysis. Analyze early customer returns and drive test hole closure activities to enhance quality and reliability. Production Test Optimization: Drive test time reduction by analyzing fallout data and balancing product cost optimizations. Implement bin split and die-level cherry-pick (DLCP) strategies to optimize product supply. Ensure manufacturability through process and spec corner analysis to resolve yield issues before mass production. Hardware & Software Development: Develop and debug complex software programs for test conversion and test automation. Create and validate test hardware solutions for production testing. Optimize component production relative to quality and cost constraints. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields. Technical Expertise: ATE Test Engineering: Strong expertise in Automatic Test Equipment (ATE) development and debug. DFT & Test Methodologies: Knowledge of DFT architectures and methodologies including Analog DFT, JTAG, etc. Understanding of test engineering processes and tester debugging techniques. Debugging & Validation: Hands-on experience with design/validation and advanced debugging skills. Expertise in Advantest 93K, Teradyne Ultraflex, J750, and related test platforms. Manufacturing Process & Yield Analysis: Experience in yield analysis, bin splitting, and test time optimization. Ability to analyze process corners and drive manufacturing readiness. Soft Skills: Excellent problem-solving skills, teamwork, and communication. Strong interpersonal and planning skills for cross-functional collaboration. About Intel s Manufacturing & Product Engineering (MPE) Group: The MPE team is responsible for test development across Intel s product segments, contributing to 95% of Intel s revenue. The team delivers pre-production test suites and physical debug capabilities to enable high-quality, high-volume manufacturing. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates. Intel offers a competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

About the Role We are seeking a Software QA Engineer to join our dynamic team and drive quality throughout the software development lifecycle. In this role, you will work closely with our software engineering team to ensure that requirements are clearly understood, achievable, and rigorously tested. You will be involved in testing complex systems and applications, while contributing to process improvements and ensuring high-quality releases. This position offers an exciting opportunity to work with cutting-edge technology and be a key advocate for quality in every phase of the development process. Key Responsibilities Collaboration: Work within our software engineering team to ensure requirements are understood, achievable, and tested thoroughly. Problem-Solving: Investigate and debug complex problems, driving them to closure. Test Planning: Create detailed, comprehensive, and well-structured test plans and test cases (end-to-end). Testing Coordination: Estimate, prioritize, plan, and coordinate testing activities across teams. Automated Testing: Design, develop, and execute automated test scripts to ensure consistent application functionality. Bug Tracking: Identify, record, document, and track bugs in detail. Regression Testing: Perform regression testing following the resolution of identified bugs. Metrics Tracking: Track and report on quality assurance metrics to ensure continuous improvement. Documentation: Contribute to the creation and maintenance of technical documentation related to test processes. Quality Advocacy: Be a vocal proponent for quality in every phase of the development process. Key Skills Software QA Methodologies: In-depth knowledge of QA methodologies, tools, and processes. Test Plans & Cases: Proven experience in writing detailed and comprehensive test plans and test cases. Automated Testing Tools: Hands-on experience with automated testing tools and knowledge of BDD test automation frameworks (e.g., Specflow, TestNG). GUI & API Testing: Experience in GUI testing (e.g., Selenium) and API testing. Programming Language: Preferably experience with C# for test automation. CI/CD: Familiarity with CI/CD pipelines (e.g., Azure DevOps Pipelines). SOA and Microservices: Experience working with SOA architectures and microservices. Machine Learning: An interest in Machine Learning technologies is a plus. Experience & Qualifications Experience: 7+ years of experience in software QA and automation testing. Test Execution: Ability to execute automated tests, understand the automation code, and prioritize the failures effectively. Self-Motivation: Passion for ensuring quality in software development. Communication Skills: Excellent verbal and written communication skills, with a focus on clear documentation and reporting. QA Methodologies: Strong knowledge of QA best practices, including writing test plans and test cases. Cloud Computing: Experience with cloud computing (applications, infrastructure, storage, platforms, data). Education: A University Degree in Computer Science, a related technical field, or equivalent practical experience. What We Offer Agile Working Environment: An agile and safe working environment that promotes flexibility and trust. Competitive Benefits: Competitive annual leave, sick leave, group incentive schemes, and insurance coverage (life, workmen s compensation, medical). Global Opportunities: Short and long-term global employment opportunities. Collaboration & Knowledge Sharing: Be part of a global team that emphasizes collaboration and knowledge sharing. Digital Innovation: Engage in initiatives focused on digital innovation and transformation. Equality, Diversity, and Inclusion At Mott MacDonald, we prioritize equality, diversity, and inclusion. We promote fair employment practices, ensuring equal opportunities for all. We encourage individual expression and are committed to creating an inclusive environment where everyone has the opportunity to contribute and thrive. Qualification : A University Degree in Computer Science, a related technical field, or equivalent practical experience.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Job Summary: Google Cloud is seeking a Program Manager to join our Scaled Services team in Go-to-Market (GTM) Strategy and Operations. This role will focus on operational excellence, helping optimize seller and compensation operations, and enabling growth by improving processes that support the cloud seller experience. You will work with cross-functional teams to design, launch, and optimize operational processes across vendor teams and key business functions. Key Responsibilities: Lead high-priority escalations from intake to resolution, ensuring effective execution and closure. Analyze and optimize operational performance by identifying and articulating process improvement opportunities. Collaborate with Compliance, Finance, Payroll, and Regional Strategy teams to optimize timelines for case resolution and ensure smooth operations. Deliver process optimization that enhances efficiency and reduces friction in key business operations, including order management and compensation. Build relationships and influence cross-functional teams to drive continuous improvements across escalation paths and business processes. Translate business needs into technical requirements, working with Engineering and other internal teams to implement scalable solutions. Track and resolve issues related to data quality, account, billing, planning, quota, and attainment. Minimum Qualifications: Bachelor s degree or equivalent practical experience. 3+ years of experience in program or project management. Proven experience in translating business needs into technical requirements. Experience working with executive-level clients or stakeholders. Preferred Qualifications: Experience in managing vendor relationships and third-party collaboration. Experience with Salesforce or other CRM/ERP systems. Experience in process design and re-engineering, optimizing workflows and operational efficiency. Why Join Google Cloud? At Google Cloud, you'll be part of a team that accelerates digital transformation for organizations worldwide. This role offers a chance to work with cutting-edge technology and collaborate with various teams to enhance the seller experience while optimizing key operational processes. Qualification : Bachelor's degree or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs Participates in the definition of architecture and microarchitecture features of the block being designed Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features Supports SoC customers to ensure high quality integration and verification of the IP block Drives quality assurance compliance for smooth IP SoC handoff Qualifications Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components Knowledge of Power management is preferred. Experience with formal apps would be good. Expertise in Verilog and System Verilog-based logic design. Expertise in Verilog and System Verilog-based logic design Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must Knowledge of considerations for performance, power, and cost optimization is desirable. Knowledge of formal property verification using Jasper is preferred Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills Set aggressive goals and meet/beat the commitments Flexible enough to work in a dynamic environment and multitask seamlessly. Ability to work independently and in a team Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience

Job Description You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master s degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor s degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : You must possess a masters degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelors degree with at least 10 years of experience.

Job Description The Client DDRPHY team is looking for an energetic and passionate Logic Methodology Engineer who conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the logic/RTL design of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Defines methodologies that produce enhancements in power, performance, and area for designs on the new architectures and process technology nodes and aids high-speed digital design targeted towards low power optimized IP implementations. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing logic/RTL related TFM. Works closely with the logic design teams to create and enhance logic design methodologies that enable fast design convergence and facilitate seamless integration. You will be responsible for setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams. The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.Objectives of the position Own and deliver TFM flows which aid in the logic design of Mixed Signal IP Continuously drive the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements Drive area/power of IPs and come up with improvements on IP Area/Power metrics Critical Decision making on Technical issues. Qualifications The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience. Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation. Experience in the following areas/ skills are desired: Strong communicator Self-starter with a penchant for creative problem solving through quick thinking Good aptitude for automation Git/Perforce/CVS know how Perl/Python/TCL Spyglass Lint, CDC, DFT, VCLP, Open Latch Multiple clock domain design Synthesis and speed path debug Below experience is desirable, but not a must: Logic design using System Verilog Low-power design using UPF and clock gating State machine design Simulation and debug experience using VCS/Verdi Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience.