Design Flow Jobs in Bengaluru

Staff Software Engineer AI & Automation Location: Bengaluru Company: Okta, The World s Identity Company Experience: 8+ Years Type: Full-Time About Okta Okta is the world s leading identity platform. We empower people to securely access any technology, anywhere, on any device. With products like the Okta Platform and Auth0, we place identity at the core of business security, enabling growth through safe digital transformation. At Okta, we value diverse perspectives and experiences. We believe in learning, collaboration, and building an inclusive environment where everyone belongs. About the Team The Business Technology - Shared Services team is at the forefront of Okta s internal digital transformation. We focus on building intelligent, automated platforms that simplify operations and deliver smarter, faster experiences to both employees and customers. We collaborate across engineering, data science, security, and business units to deliver cutting-edge solutions powered by Generative AI (GenAI), virtual agents, workflow orchestration, and intelligent recommendations. The Opportunity As a Staff Software Engineer, you ll play a critical role in designing and developing AI-powered platforms that drive automation, scale, and intelligence across Okta s business. You ll help make LLM-powered solutions and intelligent automation a reality for the enterprise ensuring performance, security, and reliability at scale. This is a hands-on, individual contributor (IC) role, ideal for engineers who are passionate about solving complex problems, architecting scalable systems, and pushing the boundaries of AI integration. What You ll Do Design & Build: Develop scalable backend services that embed GenAI and automation into core business workflows (e.g., virtual agents, document intelligence, smart routing). Collaborate Across Teams: Work closely with product managers, data scientists, and other engineers from ideation to production. Architect for Scale: Make key architectural decisions around LLM integration, API design, data flow, and observability. Code with Excellence: Write clean, secure, and maintainable code in Python, Java, or similar languages. Build for Production: Use Docker, Kubernetes, and CI/CD pipelines to build and deploy high-availability services. Champion Best Practices: Promote high standards for testing, security, code reviews, and operational readiness. Mentor & Guide: Support a collaborative team culture through peer mentorship and design reviews. What You ll Bring 8+ years of experience in software engineering with a strong track record of building and maintaining production-grade, cloud-native services. Expertise in distributed systems, API development, and cloud infrastructure (AWS, GCP, or Azure). Proficiency in Python, Java, or Go. Experience with Docker, Kubernetes, and observability tools (e.g., Prometheus, Grafana, ELK). Exposure to AI/ML concepts and eagerness to work with LLMs, NLP, or automation platforms. A strong sense of ownership, collaborative mindset, and a bias toward action. Passion for learning and working with emerging technologies especially in the AI and automation space. Why Join Okta Make AI Real: Help move GenAI from experimentation to enterprise-wide impact. Build with Purpose: Work on challenges that simplify and secure Okta s internal operations. Grow in a Human-Centered Culture: Join a humble, technically driven team that values learning, excellence, and personal growth. Join Okta and shape how identity, AI, and automation come together to power the modern enterprise.

Job Title: Lead Product Engineer Location: Bengaluru, Karnataka, India Department: Product Engineering Experience: 6 10 years About TheMathCompany TheMathCompany (MathCo ) is a global Enterprise AI and analytics firm helping Fortune 500 and Global 2000 organizations drive better decision-making through custom-built AI solutions. With our proprietary platform NucliOS, we power scalable, reusable, and intelligent products that accelerate digital transformation across industries. At MathCo, we empower our engineers to innovate, take ownership, and work on cutting-edge enterprise-grade products from scratch. If you re passionate about full-stack product development and thrive in a dynamic, high-impact environment, we d love to talk to you. About the Role As a Lead Product Engineer, you will be responsible for the architecture, development, and deployment of full-stack applications that are critical to our enterprise clients success. You ll lead a cross-functional team and work closely with product managers, designers, and data scientists to deliver high-performance solutions that scale and transform. This role combines hands-on coding, system architecture, and team leadership, and is ideal for engineers looking to make a direct impact on product direction and execution. Key Responsibilities 1. Full Stack Development Build and maintain RESTful APIs and microservices using languages like Python or Node.js. Design and develop scalable and maintainable UI components using modern front-end frameworks (e.g., React, Vue, Angular). Architect and manage application databases (SQL & NoSQL). Integrate with authentication/authorization protocols (e.g., OAuth2, OIDC, SAML). Participate in the full product lifecycle from ideation and development to deployment and support. 2. Product Development & Collaboration Translate business requirements into technical solutions in collaboration with product managers and designers. Provide technical leadership and guidance to the development team. Optimize systems for performance, scalability, and reliability. 3. Code Quality & Testing Write clean, efficient, well-documented code following best practices and industry standards. Conduct and participate in code reviews. Develop and maintain automated test frameworks; ensure unit, integration, and end-to-end testing coverage. Oversee CI/CD pipelines and manage cloud-based deployments. Must-Have Technical Skills 6 10 years of experience in full-stack development and system design. Proficiency in backend languages like Python, Node.js (bonus: Rust, Go). Strong front-end experience with HTML, CSS, JavaScript, and frameworks like React, Angular, or Vue.js. Expertise in REST APIs, microservices, and database design (ER modeling, data flow, API integration). Hands-on with PostgreSQL, MySQL, MongoDB, or similar. Experience deploying applications on cloud platforms (AWS, Azure, GCP). Familiarity with Docker, Kubernetes, and infrastructure tools like Terraform, CloudWatch. Version control and DevOps experience with GitHub, Azure DevOps, and CI/CD pipelines. Non-Technical & Soft Skills Strong knowledge of Agile methodologies (SCRUM). Excellent problem-solving and debugging capabilities. Strong communication and collaboration skills across teams. Ability to manage multiple projects in a fast-paced environment. Work with some of the best minds in data science, engineering, and AI. Drive high-impact product development used by Fortune 500 companies. Be part of a flat, inclusive, and innovation-driven workplace culture. Access to cutting-edge tools, custom-built platforms, and rapid experimentation. Apply now and help build world-class AI-driven solutions with MathCo.

Job Title: Senior Video Editor Location: Bengaluru, India Employment Type: Full-time We re building the future of real-world experiences. With $130M in revenue, guests in 100+ cities, and over 18 months of profitability, Headout is the fastest-growing travel marketplace globally. We've raised $60M+ from top-tier investors and are scaling rapidly. Our mission? To be the easiest, fastest, and most delightful way to head out to real-world experiences from tours and attractions to concerts and immersive events. We ve proven the model and built momentum now we re entering our most exciting growth phase. If you want your work to be seen by millions and shape a global brand at scale, there s no better time to join. The Role As **Senior Video Editor**, you ll be the creative engine behind Headout s most compelling video content transforming footage, animation, and sound into emotionally resonant stories across platforms. You ll own end-to-end production for a wide range of content formats, collaborate closely with the creative team, and play a key role in elevating Headout s visual identity globally. If you love storytelling, obsess over visual detail, and want to lead with innovation, this role is made for you. Creative storytelling at scale: Turn raw footage into captivating, scroll-stopping videos for YouTube, Reels, TikTok, and web. Full ownership: Take projects from concept to final delivery you ll have both creative freedom and accountability. Shape the brand: Be the voice behind how Headout tells stories visually, and elevate the video team s standards. AI meets creativity: Leverage the latest generative AI tools to push the boundaries of modern content creation. Collaboration meets leadership: Work with designers, scriptwriters, and content strategists, while also mentoring and leveling up those around you. What You ll Bring Editing Mastery Expert in Adobe Premiere Pro & After Effects Strong grasp of Photoshop/Illustrator Advanced color grading (DaVinci Resolve experience is a plus) Deep knowledge of sound design, transitions, pacing, and narrative flow Proven motion graphics experience Experience 1 5 years of professional editing experience A strong portfolio demonstrating work across platforms and formats long-form, shorts, motion graphics, social, etc. Strong storytelling instincts and creative problem-solving Leadership & Team Spirit High ownership mindset end-to-end responsibility from brief to delivery Experience mentoring teammates or leading video initiatives is a major plus Comfortable working in a fast-paced, collaborative creative environment Bonus Points Strong understanding of content strategy for social platforms (Instagram, YouTube Shorts, TikTok, etc.) Experience with generative AI tools: Midjourney, Runway ML, Krea AI, Kling, Hailuo, etc. Passion for travel, culture, or storytelling through real-world experiences What Success Looks Like Videos that not only look good, but perform well driving engagement, awareness, and conversions Smooth collaboration with design, marketing, and content teams Leading experimentation with new video formats, styles, and tools Raising the bar of craft and storytelling across all touchpoints Join Headout. Create content that travels the world and helps others do the same.

Product Designer - II Location: Bangalore, Karnataka | Department: Product & Design About the Team At Meesho, we re on a mission to enable 100 million businesses to succeed online. We re making e-commerce accessible for Tier-2+ markets, where users are new to online shopping. Our Design team is as diverse as our users, comprising 30 Designers, including Interaction and Visual Designers. We are passionate about understanding our users and solving for them. Whether it s language, literacy, culture, or technology, we re breaking barriers to create a seamless and impactful user experience. About the Role Your role will involve breaking down complex tasks, understanding both customer and business needs, and translating them into easy-to-use, intuitive, and delightful designs. You will create high-fidelity mockups, wireframes, user flows, and prototypes, and collaborate with teams to implement these designs. Your goal will be to continuously improve processes and user experiences based on feedback and data. What You Will Do Design new experiences: Create mockups, wireframes, flow diagrams, sketches, and other UX artifacts that delight users. Conduct usability testing: Gather user feedback and iterate designs quickly to improve usability. Communicate your designs: Present your ideas to stakeholders, clearly explaining design decisions and incorporating feedback. Collaborate with teams: Work with product, business, and engineering teams to create scalable, impactful solutions. Advocate for the user: Ensure the design solves user problems while aligning with business goals. Use data to inform design decisions: Leverage both quantitative and qualitative data to drive design and measure success. What You Will Need 3+ years of design experience in a product company. Experience in fast-paced environments, especially working in startups. A strong portfolio showcasing your interaction and visual design skills. Attention to detail with a desire to continuously learn in a fast-paced environment. Experience consolidating research and stakeholder feedback to influence design decisions. Cross-functional collaboration experience with product, engineering, and business teams. Proficiency in design tools: Experience with Figma and other design/prototyping tools. Design System experience: Knowledge of using and evolving design systems for new use cases. About Us Welcome to Meesho, where every story begins with a spark of inspiration and a dash of entrepreneurial spirit. We re not just a platform we re your partner in turning dreams into realities. Curious about life at Meesho? Our employees love working here, and we re proud to be one of the top-rated e-commerce workplaces on Glassdoor! Our Mission Meesho was created with a simple mission: to democratize internet commerce for everyone. We are the e-commerce destination for the next billion Indian consumers, helping over 1.75 million sellers grow their businesses. With industry-first benefits like zero commission and the lowest shipping costs, Meesho is paving the way for small businesses to thrive online. Our tech infrastructure, pan-India logistics, and affordable products make online shopping accessible to first-time internet users. Culture & Total Rewards At Meesho, we focus on creating a dynamic and performance-driven workplace. Our people-centric culture is built around high impact and excellence. Our 11 guiding principles (or "Mantras") form the foundation of everything we do, from recognition and evaluation to growth discussions. What We Offer: Competitive compensation both cash and equity-based rewards, tailored to job roles and individual experience. Comprehensive wellness support through our MeeCare Program, which includes physical, mental, financial, and social wellness initiatives. Generous medical insurance benefits for employees and their families, as well as wellness services like telehealth and gym discounts. Work-life balance: Generous leave policies, parental support, retirement benefits, and continuous learning support. Employee recognition: Personalized gifts, engagement activities, and a culture of appreciation for hard work. Additional benefits like salary advance support, relocation assistance, and flexible benefit plans.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

End to End Solution Architect Location: Bangalore Role: End to End Solution Architect Experience: 15 - 25 years Number of Positions: 2 Qualifications: Job Description: Minimum of 15 years experience as an enterprise/solution architect in the telecom domain. Should have worked in telecom OSS systems. Knowledge about Enterprise products (B2B space) is needed e.g., managed broadband, managed security, etc. Telecom/Cable background is a must. Must be fluent in German. Must have experience in a multi-vendor environment. Manage Architecture deliverables; ensure understanding of Solution across all Epics and Tracks. Create and maintain end-to-end architecture artifacts including but not limited to, interface design documents, process design documents, sequence diagrams, data flow diagrams, and data models across the B/OSS ecosystem. Create and maintain the solution architecture roadmap across all Epics and produce architecture blueprints for each release iteration. Review business requirements and collaborate with development teams to identify system impacts and estimates. Conduct and represent in Joint Application Design (JAD) sessions as necessary during the design and integration phases. Follow through architecture issues and integration challenges that arise throughout the software development life cycle and provide resolution. Collaborate and drive alignment with key business stakeholders, solution development, and testing teams on architecture approach and direction. Co-ordinate with PM s, infrastructure/operations team, testing teams, and release/change control teams as needed. Defining software enterprise architecture. Demonstrating the ability to create systems architecture and solution design given a brief product requirement. Designing new features to meet new business requirements. Must have knowledge of Middleware-oriented management, Enterprise Service Bus (ESB), Enterprise Architecture tools (Visio, IBM Rational Software Architect, etc.), and Service Oriented Architecture (SOA). Workflow and business process management. System integration lifecycle for an OSS implementation. Expertise on leading COTS platforms. Office core field service management. Familiarity with Agile software development processes knowledge of the scaled agile framework is preferred. Ability to work in a multi-vendor environment.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

What Gramener Offers You Gramener provides an inviting workplace, talented colleagues from diverse backgrounds, steady career growth prospects, and numerous opportunities for innovation. Our goal is to create an ecosystem of easily configurable data applications focused on data storytelling for both public and private use. Roles and Responsibilities Participate in the end-to-end development lifecycle of IT solutions, from requirements gathering to launch, as part of a cross-functional team. Design, develop, test, and document software changes for new applications, feature enhancements, and bug fixes. Develop and implement ServiceNow solutions based on business requirements, ensuring alignment with best practices. Perform requirement analysis, design, and implementation of assigned projects while adhering to engineering standards and processes. Collaborate with global teams to translate customer requirements into optimized software solutions that operate within platform constraints. Customize and configure ServiceNow modules, workflows, forms, and scripts to meet business needs. Develop integrations between ServiceNow and other systems, ensuring seamless data flow and process automation. Design and implement UI policies, data policies, access controls, and ensure data integrity and security. Gain an in-depth understanding of business processes and domain knowledge, applying that knowledge to deliver solutions and fixes for customer requirements. Skills and Qualifications Bachelor s or Master s degree in Computer Science, Information Technology, or a related field. 6+ years of experience as a ServiceNow Developer with a track record of successful project implementations. Strong knowledge of the ServiceNow platform architecture, modules, and functionalities. Hands-on experience in configuring Business Rules, Client Scripts, UI Policies, UI Actions, complex workflows, and solution migration to higher environments. Experience in developing custom ServiceNow applications and widgets, with expertise in backend scripting. Proficiency in ServiceNow integrations using APIs, web services, and data imports/exports. Familiarity with IT Service Management (ITSM) and IT Operations Management (ITOM) processes. Experience in creating and managing SLAs, Record Producers, Catalog Items, and transform maps for data imports. Working knowledge of scheduled jobs, events, triggers, and business process automation. Solid understanding of data structures, algorithms, and operating system concepts. ServiceNow certifications, such as Certified Application Developer (CAD) or Certified System Administrator (CSA), are preferred. Strong analytical and problem-solving skills with a methodical approach to troubleshooting. About Us At Gramener, we help organizations make data-driven decisions. Through strategic data consulting, we create roadmaps for data transformation, equipping businesses to turn data into a strategic differentiator. Our products and services focus on analyzing and visualizing large datasets to deliver actionable insights that drive smarter decisions. Qualification : Bachelors or Masters degree in Computer Science, Information Technology, or a related field.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Overview: Titan, a leader in the retail industry, is seeking a highly motivated and experienced individual to join our team as the Lead - Leadership Development & Talent Management. This role will be integral in identifying and developing top talent, as well as designing and executing leadership development programs that align with the organization s goals. The individual will contribute significantly to building a pipeline of future leaders and ensure the continued growth of our employees across the organization. Key Responsibilities: Talent Management Strategy: Develop and implement comprehensive talent management strategies to attract, retain, and nurture high-performing individuals across the organization. Create initiatives that ensure a continuous flow of talent aligned with business goals. Leadership Development Programs: Design and implement innovative leadership development programs to identify, develop, and nurture high-potential employees for future leadership roles within Titan. Talent Reviews & Succession Planning: Conduct regular talent reviews and succession planning exercises to identify emerging leaders. Develop personalized growth plans and career development paths for high-potential employees. Collaboration with Department Leaders: Partner with leaders across departments to identify key skills and competencies required for different roles. Collaborate in the creation of training programs aimed at closing skill gaps and supporting career progression. Performance Management Integration: Work closely with the HR team to align performance management processes with talent management strategies, ensuring that talent is consistently developed and engaged. Continuous Learning: Stay abreast of industry trends and best practices in talent management and leadership development. Continuously assess and improve programs to ensure they meet evolving organizational needs. Mentorship & Coaching: Provide mentorship and coaching to employees at all levels of the organization, offering guidance and support for their professional development. Qualifications: Educational Background: Bachelor's degree in Human Resources, Business Administration, or a related field. A Master s degree in Human Resources or a related discipline is preferred. Experience: Minimum of 15+ years in Human Resources, with at least 5 years focused specifically on Talent Management and Leadership Development. A significant portion of this experience should be in a leadership or people management role. Retail industry experience is preferred but not mandatory. Skills: Deep understanding of talent management principles and best practices. Experience designing and implementing leadership development programs. Excellent communication and interpersonal skills, with a proven ability to collaborate effectively across functions and levels. Strong analytical skills with the ability to assess data and provide actionable insights. Ability to influence senior leadership and engage employees in development programs. Proven success in developing and retaining top talent in an organization. Additional Information: This is a full-time position based in Bengaluru, Karnataka, India. Some travel may be required for the delivery of training and development programs. The ideal candidate will be passionate about leadership development, talent management, and have a genuine desire to make a meaningful impact within Titan. Qualification : Masters degree in human resources, or a related field.

Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs Participates in the definition of architecture and microarchitecture features of the block being designed Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features Supports SoC customers to ensure high quality integration and verification of the IP block Drives quality assurance compliance for smooth IP SoC handoff Qualifications Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components Knowledge of Power management is preferred. Experience with formal apps would be good. Expertise in Verilog and System Verilog-based logic design. Expertise in Verilog and System Verilog-based logic design Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must Knowledge of considerations for performance, power, and cost optimization is desirable. Knowledge of formal property verification using Jasper is preferred Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills Set aggressive goals and meet/beat the commitments Flexible enough to work in a dynamic environment and multitask seamlessly. Ability to work independently and in a team Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience

Job Description: We are looking for an experienced CPU Circuit Design Engineering Manager to lead and manage Intel's cutting-edge CPU design projects. As part of a world-class team, you will oversee a group of engineers working on complex circuit designs, driving the development of Intel s most advanced CPUs. You will play a pivotal role in shaping the architecture and ensuring the high performance, power efficiency, and reliability of next-generation processors. Key Responsibilities: 1. Team Leadership and Development: Lead, mentor, and develop a team of talented circuit design engineers. Oversee all aspects of CPU circuit design, from initial conceptualization to post-silicon validation. Foster an environment of innovation, excellence, and collaboration. 2. Design Execution and Methodology: Manage the design, implementation, and validation of high-performance CPU circuits, including critical components like logic circuits, clock distribution, and power management. Drive the adoption of best practices and state-of-the-art design methodologies to ensure efficient design execution. Ensure that the designs meet Intel s performance, power, and area (PPA) targets. 3. Cross-functional Collaboration: Collaborate closely with cross-functional teams including architecture, layout, validation, and manufacturing to ensure a seamless transition from design to silicon. Communicate effectively with senior management and other stakeholders to drive the successful delivery of CPU designs. 4. Process and Efficiency Improvement: Continuously work on improving design processes, tools, and methodologies to optimize efficiency and reduce time-to-market. Implement strategies to mitigate design risks, enhance quality, and maintain high standards across all CPU designs. 5. Performance, Power, and Area Optimization: Ensure the CPU circuits are designed to meet optimal power, performance, and area (PPA) goals. Collaborate with other teams to ensure that design specifications align with broader product requirements. 6. Innovation and Strategy: Stay abreast of industry trends, new technologies, and cutting-edge circuit design techniques. Lead efforts to incorporate new circuit design innovations into Intel s CPU development pipeline. Qualifications: Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in CPU circuit design, with at least 5 years in a leadership role. Proven track record of successfully leading complex CPU circuit design projects from concept to implementation. Strong understanding of circuit design principles, including logic design, timing, power, and signal integrity. Preferred Qualifications: Experience with advanced semiconductor process technologies (e.g., 7nm, 5nm, or lower nodes). Expertise in tools for circuit design, simulation, and analysis (e.g., Cadence, Synopsys). Knowledge of high-performance CPU architecture and chip design. Strong problem-solving skills and the ability to work under pressure in a fast-paced environment. Excellent communication and interpersonal skills, with experience working in a cross-functional and global environment. Inside this Business Group: The Core and Client Development Group (C2DG) is at the heart of Intel s product development, creating the next generation of CPU architectures and technologies. The group is responsible for driving Intel's leadership in the computing industry, delivering high-performance processors that power both client and server markets. Equal Opportunity Employer: Intel is an equal opportunity employer and considers all qualified applicants for employment without regard to race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected by local law. Qualification : You must possess a Masters Degree in Electrical or Computer Engineering with atleast 10 or more years of experience in related field or a Bachelors Degree with atleast 12 years of experience.