Design FOR Verification Jobs in Bengaluru

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Requirements: BE/BTech degree in CS/EE with 8+ years experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus. Qualification : BE/BTech degree in CS/EE

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

CPU Verification Engineer Company Arm Location Bengaluru Job Overview Responsibilities Contribute technically as part of project teams to deliver high-quality ARM CPU designs. Execute comprehensive CPU design verification, focusing on improving design quality through stress testing and bug identification. Effectively plan, conduct reviews, provide status updates, and meet delivery expectations. Collaborate with design and architecture teams to ensure effective coverage and provide accurate project planning inputs. Design and develop verification testbenches and components required for effective verification. Maintain knowledge of company processes to work effectively within defined standards and methodologies. Drive efficiency improvements in verification tools and methodologies and mentor team members to support career development. Required Skills and Experience 3+ years of experience in CPU, IP, or SoC product development environments. Experience in design verification/validation, including developing test plans, testbenches, and executing measurable verification processes. Familiarity with processor verification using assembly language and C/C++. Knowledge of microprocessor and/or SoC architecture and microarchitecture, preferably ARM processors and ARM-based systems. Strong problem-solving and debugging skills, with a commitment to continuous improvement. Nice-To-Have Skills and Experience Strong understanding of CPU architecture and microarchitecture. Experience with ARM-based system designs and hierarchical memory systems. Programming languages: Verilog, Assembly, C/C++, Perl, Python. Experience with verification languages such as SystemVerilog. Familiarity with power-aware verification methodologies. What Arm Offers This is a fantastic opportunity to shape the future of CPU verification at Arm while advancing your own career. Join our CPU design verification team and play a key role in delivering Arm's strategic goals! #LI-KR2

Job Overview: The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arm s future architecture roadmap. In ATG, we are developing world-leading Secure CPU and System architectures and associated technologies; enabling our ecosystem to build compelling products. Along with the architecture definition, ATG develops products to confirm compliance to the architecture. The ATG team located in Bangalore develops a product called Architecture Compliance Kits (ACK) that are delivered to multiple internal and external CPU design teams to validate that Arm architecture CPU implementations are compliant with the Arm architecture. You will learn Arm Architecture and apply it along with hardware and software verification skills to develop products for verifying the Architecture. You will develop good engineering and technical skills, and a fair understanding of CPU architecture and microarchitecture. You will connect with a wide range of teams within ATG, architects, and with our external partners. In this role, you will also develop solutions for future Arm architecture developments and influence the product offering. Responsibilities: Technical expertise, understanding architecture definitions, carrying out investigations and feasibility studies, defining and developing verification strategies, and contributing to the development of compliance products. Design verification test plans and test cases in assembly, C, HVL, and higher abstraction languages using automation techniques as needed. Strong and continuous communication on deliveries and risks, ensuring that all engineering commitments are delivered successfully. Drive efficiency improvements through adoption of the right development flows and methodologies. Excellent verbal and written communication skills. Required Skills and Experience: B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering. 8+ years of verification experience (CPU/complex IP verification is a plus). Strong understanding of computer architecture. Proficiency in logical programming using C/C++/Assembly with experience in adopting software engineering best practices. Nice To Have Skills and Experience: Experience in CPU verification would be a plus. Knowledge of x86 or Arm processor architecture. We are guided by our core beliefs that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and craft outstanding products and careers. In Return: We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to complex core implementation to full custom physical IPs, here you'll have our backing to push limits in vital areas. #LI-KR2 Qualification : B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

Position: VLSI Trainer Experience: 3 8 years Education: M.Tech in VLSI / B.E. in Electronics and Communication Engineering (ECE) Industry: Education, E-Learning, Semiconductor Job Type: Training Job Description We are seeking an experienced VLSI professional with strong expertise in digital design and verification to join our training team. The ideal candidate should have a passion for teaching and hands-on experience in VLSI design and verification methodologies. Key Responsibilities: Conduct training sessions on Digital Design, SystemVerilog (SV), UVM, Verilog, VHDL, DFT, and related tools. Provide hands-on support and guidance to trainees on various projects. Debug and troubleshoot source code in Verilog, SV, and UVM. Develop and support training projects and technical content. Deliver high-quality training sessions and post-training support. Desired Skills & Experience: Proficiency in Digital Design, Verilog, VHDL, SystemVerilog (SV), UVM, DFT, and Physical Design. Experience working with Mentor Graphics EDA, Cadence, or Synopsys tools is a plus. 3 to 8 years of experience in the semiconductor industry, teaching, or training. Strong communication and presentation skills. Mandatory Requirements: Solid understanding of VLSI design and verification concepts. Excellent problem-solving abilities and debugging skills. Qualification : M.Tech VLSI/BE ECE

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Job Description: We are seeking a highly skilled and experienced CPU Verification Engineer with a focus on ARM and NCC-based ARM architecture. This role requires a deep understanding of CPU microarchitecture, SOC integration, and verification methodologies. The ideal candidate will lead verification efforts, collaborate with cross-functional teams, and mentor junior engineers to ensure high-quality CPU design verification. Key Responsibilities: Lead and execute verification plans for CPU designs based on ARM and NCC-based ARM architecture. Develop and enhance testbenches and verification environments using advanced automation techniques. Collaborate with design and architecture teams to identify and resolve specification gaps, ensuring comprehensive verification coverage. Perform SOC-level verification, including integration and validation of CPU subsystems. Utilize industry-standard verification tools and methodologies such as UVM, SystemVerilog, and simulation/emulation platforms. Mentor and guide junior verification engineers, providing technical leadership and support. Continuously improve verification processes and methodologies to enhance efficiency and effectiveness. Qualifications: Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 8 14 years of experience in CPU verification, with a focus on ARM and NCC-based ARM architecture. Proficiency in verification languages and methodologies, including SystemVerilog, UVM, and scripting languages (Python, Perl, etc.). Strong understanding of CPU microarchitecture, memory hierarchy, and SOC integration. Experience with simulation, emulation, and formal verification tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills, with the ability to work in a collaborative environment. Preferred Qualifications: Experience with low-power design verification and performance verification. Knowledge of hardware security verification techniques. Familiarity with machine learning and AI-based verification approaches. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of hardware engineering or related work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or related field and 1+ year of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Job Overview As a Tools Support & Infrastructure Engineer at Qualcomm, you'll play a vital role in supporting and enhancing the design flows and infrastructure for Qualcomm's Digital Signal Processing (DSP) team. The DSP design team delivers high-performance DSP cores that are integral to Qualcomm's multi-tier SoC roadmap, particularly for mobile applications. This position involves managing DSP design databases, developing automation tools to streamline the verification process, and collaborating with global teams to optimize design efficiency and quality. Key Responsibilities Manage DSP Design Database: Oversee the DSP design database, supporting design and verification teams with infrastructure needs. Build Automation: Create new automation tools to enhance the productivity of design verification teams, making it easier to debug simulation failures. Collaborate with Global Teams: Work with Qualcomm s global DSP design teams (architecture, implementation, post-silicon, and back-end teams) to enhance DSP IP infrastructure. Improve Tool Methodologies: Design and deploy new tool methodologies to continuously improve the quality, efficiency, and effectiveness of design and verification processes. Support Design Flows: Contribute to and improve design flows, ensuring the seamless integration of tools and resources used by design teams. Minimum Qualifications Educational Requirements: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 5+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant work experience. Skills & Experience Programming & Tools Support: 3-10 years of experience in programming, database management, and providing tools support for complex DSP IP designs. Automation Expertise: Extensive experience in building automation tools that improve design and verification processes. Programming Languages: Expertise in C++ and Java. Scripting & Automation: Proficiency with scripting languages and tools such as Perl, Python, Shell, Makefiles, and TCI. Analytical Skills: Strong analytic, programming, and debugging abilities. Object-Oriented Programming (OOP): Deep understanding of OOP concepts. Web Programming: Familiarity with Java for web programming is a plus. Unix Environment: Solid understanding of the Unix environment. Digital Design Flows: Knowledge of digital design flows is a plus. Communication: Excellent interpersonal and communication skills, with the ability to work collaboratively with global teams.

Job Overview As a Hardware Engineer at Qualcomm, you'll be part of a dynamic team that plans, designs, optimizes, verifies, and tests cutting-edge electronic systems, including circuits, mechanical systems, digital/analog/RF/optical systems, and more. Your role will focus on SerDes PHY Analog Design, specifically within the BDC SerDes Mixed-Signal Design team. This team is directly involved in delivering next-generation custom PHY designs for SoCs (System on Chips), with a key focus on low-power analog designs to support Qualcomm s wireless products. You ll work with cross-functional teams to meet performance requirements and help bring innovative products to market. Key Responsibilities Analog Circuit Design: Hands-on experience in analog circuit design, working on multiple analog building blocks, including LDO, high-speed TX and RX (Equalizer, Sampler, PI, Deserializer), Bias, and Reference circuits. PLL and Frequency Synthesis: Design and implement Analog and Digital PLLs for frequency synthesis and SerDes applications, including Charge Pumps, Loop Filters, VCO/DCO, PFD/TDC, and high-speed dividers. PLL Loop Dynamics: Model PLL Loop Dynamics, including sources of Jitter (RJ & DJ). Schematic to Post-Layout Verification: Take designs from initial schematic to post-layout verification, and ensure integration sign-off for post-silicon bring-up. Collaboration: Work closely with RTL, DD, PD, DV, and SoC Verification teams to integrate the PHY into SoCs. Minimum Qualifications Educational Background: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 3+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 2+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 1+ year of relevant work experience. Skills & Experience Analog Circuit Design: Hands-on experience with designing analog building blocks such as LDO, high-speed TX/RX, bias, and reference circuits. PLL Design: Strong background in Analog and Digital PLLs for frequency synthesis and SerDes applications. Charge Pump and VCO/DCO: Experience in designing charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers. Jitter and PLL Loop Dynamics: In-depth understanding of PLL loop dynamics, jitter modeling, and frequency synthesis for SerDes systems. Design Verification: Experience in taking designs from schematic through post-layout verification, integration, and post-silicon bring-up. Team Collaboration: Ability to work with cross-functional teams such as RTL, DD, PD, DV, and SoC verification teams to ensure smooth integration.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Job Description: Arm s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in today's Enterprise, Auto and Client markets. Responsibilities: As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience : 4-15 years of proven experience in working on IP/Subsystem/Soc Verification Experienced in one or many of these technologies/ protocols - PCIe, CXL, USB, Ethernet. Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs. Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies UVM, formal and low power. Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support. Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers. Nice To Have Skills and Experience : Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture/micro-architectures! In Return: With offices around the world, Arm is a diverse organisation of dedicated, innovative and very hardworking engineers. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their outstanding contributions to Arm's success in the global marketplace Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Qualification : 4-15 years of proven experience in working on IP/Subsystem/Soc Verification

Overview: Collins Aerospace is looking for a talented Software Verification Lead Engineer to join the Navigation and Advanced Technology team. In this role, you will be responsible for performing validation and verification for critical avionics systems, focusing on protocols and applications like Maintenance, OMS, and Dataload. You will collaborate with senior developers and architects to design scalable, extensible, and sustainable solutions, while ensuring the highest standards of quality and performance. Primary Responsibilities: Avionics DAL A Product Verification: Verify avionics products in the CNS (Communication, Navigation, and Surveillance) domain, ensuring compliance with industry standards and customer requirements. Tool Development & Test Design: Develop common supporting tools necessary for development and verification activities, as well as create validation tests for avionics systems. Collaboration with Cross-functional Teams: Work closely with architects and senior developers to create scalable solutions, ensuring that new technologies are effectively integrated into the system architecture. CI/CD Pipeline Management: Build CI/CD pipelines and collaborate with the DevOps team to ensure streamlined deployments. Troubleshoot and resolve build issues while supporting deployment processes. Basic Qualifications: Education: BE/B.Tech/ME/M.Tech in Engineering. Experience: 6-8 years of experience in avionics systems and software development. Technical Skills: Proficiency in Python, C/C++, and Matlab/Simulink. Strong understanding of Avionics Systems/Software Architecture, including CNS, FMS, FCS, or Displays. Familiarity with DO-178B/C software standards. Avionics Domain Knowledge: Experience in Communication, Navigation, and Surveillance systems, including protocols for voice and data communications, satellite-based navigation, weather detection, traffic awareness, and collision avoidance. About Collins Aerospace: Collins Aerospace, a Raytheon Technologies company, is a global leader in aerospace and defense solutions. We offer advanced technology and services across a wide array of civil, military, and government missions. Our products are integral to the safety and efficiency of modern aviation, from emergency power systems to reliable cabin controls and quieter engines. Joining our team means being part of a mission-driven company that innovates every day to deliver safer, smarter, and more efficient aerospace systems. Collins Aerospace Diversity & Inclusion Statement: Diversity drives innovation, and inclusion drives success. At Collins Aerospace, we foster a culture that values diversity of thought and experience, which enables us to tackle the toughest challenges in our industry. We are committed to ensuring all employees have the opportunity to share their ideas and passions, paving the way for limitless possibilities. Benefits Package: Insurance: Group Term Life Insurance, Group Health Insurance, Group Personal Accident Insurance. Leave Entitlements: 18 days of vacation and 12 days of contingency leave annually. Employee Programs & Work-life Balance: Employee Scholar Program, work-life balance initiatives, car lease program, National Pension Scheme, Leave Travel Allowance (LTA), and meal vouchers. Additional Benefits: Fuel and maintenance/driver wages, and more! Ethical & Safety Commitment: Collins Aerospace prioritizes strong ethical practices and safety. All positions in India require a background check, which may include a drug screen (for operations positions). Why Collins Aerospace? At Collins Aerospace, we are redefining aerospace. Join our team and be part of a company that plays a critical role in modern flight, providing innovative solutions that enhance safety, efficiency, and the travel experience for millions of passengers worldwide. Qualification : BE/B.Tech/ME/M.Tech with Understanding of Avionics Systems/Software Architecture CNS, FMS, FCS or Displays.