Digital Asic Engineer Jobs in Bengaluru

Position: Social Media Executive (Graphics & Video Specialist) Location: Bengaluru Employment Type: Full-Time Job Overview We are seeking a highly creative and results-driven Social Media Executive to serve as the voice and visual face of Fracktal across all digital channels. This role combines strategic social media management with hands-on content creation, with a strong focus on producing compelling **graphics and high-quality video content** for a technical and industrial audience. Key Responsibilities Content Creation & Production (Primary Focus on Graphics & Video) Plan, script, shoot, and edit **original video content** for platforms like YouTube, Instagram Reels, and LinkedIn (including product demos, testimonials, and explainer videos). Design professional, on-brand **visual assets** such as infographics, social media posts, stories, and ads using tools like **Adobe Creative Suite or Canva**. Ensure consistent visual identity and brand voice aligned with the additive manufacturing industry. Social Media Strategy & Management Develop and implement a comprehensive social media strategy across **LinkedIn, Instagram, YouTube, and Facebook**. Maintain a dynamic **content calendar** balancing promotional, educational, and engagement-focused posts. Monitor, listen, and respond to user interactions, ensuring professional and timely **community management**. Analytics & Reporting Track, analyze, and report on **key social media metrics** (reach, engagement, traffic, conversions). Use **data-driven insights** to optimize content strategy and enhance future campaign performance. Industry Engagement Stay updated on the latest social media trends, platform updates, and advancements in **3D printing and additive manufacturing** to create relevant and engaging content. Key Skills & Requirements Experience: 1 3 years in social media management, digital marketing, or related roles. Creative Skills: Strong proficiency in **graphic design (Photoshop, Illustrator, or equivalent)** and **video editing (Premiere Pro, Final Cut Pro, or equivalent)**. Portfolio: Must provide a **portfolio** demonstrating experience in creating engaging social media graphics and video content. Technical Aptitude (Optional but Advantageous): Basic understanding of or strong interest in engineering, **3D printing**, or manufacturing technologies. Soft Skills: Excellent written and verbal communication, attention to detail, and ability to work independently in a fast-paced environment. Compliance & Safety Ensure adherence to industry regulations, company policies, and safety protocols. Maintain a clean, organized, and hazard-free work environment.

Senior Manager Full Stack Engineering Location: Bangalore Company: Capital One India About Capital One India At Capital One India, we blend the agility of a startup with the scale of a Fortune 100 company. Our technology teams drive transformation across banking by building next-generation financial products that are secure, user-centric, and powered by cutting-edge engineering practices. We are makers, breakers, doers, and thinkers working together to reinvent consumer finance through technology, modern design, and data science. As a company that builds its own software and platforms, we re constantly innovating to help over 65 million customers bank better. About the Role As a Senior Manager Full Stack Engineering, you ll lead multiple teams building highly available, scalable, and secure platforms and applications. You ll be at the forefront of technical design, architecture, and implementation, helping your teams deliver impactful solutions across web, mobile, backend services, and cloud infrastructure. This is a hands-on leadership role ideal for an experienced engineering leader who still loves to write code, mentor engineers, and contribute directly to architecture and product evolution. What You ll Do Lead full-stack engineering teams delivering cross-functional, multi-platform applications using modern cloud and open-source technologies. Own end-to-end technical design, architecture decisions, and delivery strategy for critical systems. Partner with architects, product managers, and cross-functional leaders to understand requirements, prioritize needs, and develop scalable solutions. Guide and mentor engineers, driving technical excellence, performance, and career growth across teams. Drive Agile delivery, ensuring projects meet timelines and quality standards while promoting DevOps best practices. Champion and enforce best practices in secure coding, architecture, compliance, and accessibility. Collaborate with internal and external stakeholders to align technology vision with business goals. Manage full software development lifecycle: planning, estimation, implementation, deployment, and support. Foster a culture of engineering excellence, continuous learning, and experimentation. Basic Qualifications Bachelor s Degree in Computer Science, Engineering, or a related field 8+ years of experience in software development, with a focus on full-stack systems 5+ years of experience managing software development teams through full release cycles Proven track record of leading Agile teams and delivering high-impact technology projects 5+ years of people management experience, including mentoring and team scaling Preferred Qualifications Master s Degree in Computer Science, Engineering, or Business 10+ years of software engineering experience in large-scale, distributed systems 6+ years of experience applying Agile methodologies (Scrum, Kanban, SAFe) Hands-on experience with some or all of the following: Languages: Java, Python, Go, JavaScript, Node.js Frontend: React, AngularJS, HTML5, CSS Cloud: AWS, Azure, GCP (AWS preferred) DevOps: CI/CD, Docker, Kubernetes, Terraform Databases: NoSQL (MongoDB, Cassandra), SQL, Redshift, Snowflake Strong understanding of accessibility standards and building inclusive digital products Experience with Big Data, event-driven architectures, and RESTful APIs Passion for mentoring, technical excellence, and building diverse, high-performing teams Join a team that's redefining how software powers banking Build next-gen cloud-native applications from scratch Work on meaningful problems with direct customer impact Thrive in a collaborative, transparent, and inclusive culture Access top-tier learning opportunities, technical conferences, and internal mentorship Qualification : Masters Degree in Computer Science, Engineering, or Business

Job Title: Consultant - Content Operations Location: Bangalore, India Company: Glance An InMobi Group Company About Glance Glance is a leading consumer technology company powering innovative digital platforms such as Glance, Roposo, and Nostra. Founded in 2019 and headquartered in Singapore, Glance s smart lock screen technology transforms how users engage with their smartphones by delivering relevant content without searching or downloading apps. Currently, Glance s lock screen reaches over 400 million smartphones globally. Our platforms include: Glance: The revolutionary smart lock screen platform Roposo: A dynamic LIVE video platform transforming creator-led experiences Nostra: The largest gaming platform across India and Southeast Asia Join Glance and unlock your potential in a fast-paced, innovative environment. Here, your ideas matter you ll work on impactful projects alongside ambitious peers, leveraging the latest tech to reshape digital content experiences. We value autonomy, creativity, and collaboration. Enjoy benefits such as daily meals, wellness programs, tech tools, and a family-friendly workplace where your kids and pets are welcome. Key Responsibilities Content Operations Consultant Content Moderation: Ensure all user-generated and platform content adheres to Glance s brand guidelines, legal compliance, and community standards. Content Curation: Analyze user preferences, regional trends, and current events to select and organize engaging, relevant content. Creative Enhancement: Innovate by adding creative elements that boost emotional connection and user engagement across platforms. Content Publishing: Manage the end-to-end content publishing lifecycle, guaranteeing accurate, timely releases aligned with operational goals. Cross-Functional Collaboration: Work closely with engineering and product teams during content production and staging to ensure flawless publishing and technical accuracy. Candidate Profile & Qualifications Demonstrated experience (0.5 months to 1 year) in content moderation, digital content curation, creative content strategy, or content publishing in a fast-paced digital or tech environment. Strong understanding of content compliance, audience engagement, and digital publishing workflows. Ability to collaborate with cross-functional teams including engineering and product management. Excellent attention to detail, creativity, and adaptability in a dynamic work setting.

Senior Research Specialist Location: Bengaluru, Karnataka, India Department: Sales & Solutioning Experience: 6 9 Years Employment Type: Full-Time About CloudSEK CloudSEK is a fast-growing, AI-powered cybersecurity company on a mission to make the digital world safer through contextual threat intelligence. With industry-leading platforms like XVigil, BeVigil, and SVigil, we help global enterprises proactively identify and respond to digital threats. Headquartered in Singapore with a strong presence across India and Southeast Asia, we are proud to be recognized for our innovation and rapid growth in the cybersecurity domain. Role Overview: Senior Research Specialist (Sales & Solutioning) We are looking for an experienced and analytical Senior Research Specialist to join our Solutioning Team. This hybrid role combines technical expertise, client engagement, and team leadership. You will lead solution design for complex data engineering needs and directly contribute to shaping scalable architectures, ETL frameworks, and modernization strategies. Your work will directly support sales efforts, proposal development, and solution delivery making you a critical bridge between technical execution and business strategy. Key Responsibilities Solution Design & Research Lead technical discovery sessions to understand client needs, pain points, and opportunities. Review and guide research efforts, validating solution strategies proposed by the team. Design scalable and realistic end-to-end data engineering roadmaps with cross-functional alignment. Evaluate technologies, cloud platforms (AWS, GCP, Azure), tools, and architectures for each engagement. Support proposal creation, RFP responses, and client presentations by crafting engaging, value-focused narratives. Client & Stakeholder Engagement Act as a technical advisor to prospective clients, articulating solutions in a business-relevant context. Translate complex data engineering challenges into easy-to-understand presentations and documentation. Collaborate with internal teams sales, delivery, data architects, and domain experts to co-create tailored solutions. Team Mentorship & Enablement Mentor a team of solution engineers; promote collaboration, learning, and delivery excellence. Provide leadership during pitch cycles and client interactions, fostering a high-performance, agile culture. Oversee quality and consistency across solutioning documentation, storyboards, demos, and technical narratives. Must-Have Qualifications Bachelor s or Master s in Engineering, Computer Applications, Mathematics, or Statistics. 6 9 years of experience in solutioning, data engineering, or technical consulting. Proven experience working with cloud ecosystems: AWS, Azure, or GCP. Strong research and analytical capabilities to evaluate tools, strategies, and solutions. Hands-on experience in designing and communicating data engineering solutions. Comfortable interacting with clients and translating requirements into executable plans. Excellent communication and presentation skills for technical storytelling. Nice-to-Have Skills Experience in proposal design, storyboarding, and client demos. Team leadership or experience managing solution engineers. Exposure to sales engineering, pre-sales consulting, or customer success. Familiarity with cybersecurity or digital risk platforms is a bonus. Mission-Driven Work: Shape cutting-edge, high-impact solutions for cybersecurity and data intelligence. Collaborative Culture: Work in a high-energy, fast-paced, and innovation-focused environment. Personal Growth: Take on diverse challenges with support for continuous learning and leadership development. Flexible Environment: Enjoy work-life balance with flexible hours and a creative workspace. Qualification : Bachelors or Masters in Engineering, Computer Applications, Mathematics, or Statistics.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Senior PLM Analyst Teamcenter Location: Bengaluru Experience Required: 2 5 years Company: Pratt & Whitney (Raytheon Technologies) Job Overview Pratt & Whitney is looking for an experienced Senior PLM Analyst with a strong background in Teamcenter PLM systems to support the Engineering Applications team in delivering digital transformation and Model-Based Systems Engineering solutions across the enterprise. Responsibilities Develop, implement, and support customized PLM solutions using Teamcenter. Work closely with Engineering and DevOps teams to improve system availability, performance, and integration. Participate in Agile ceremonies, code reviews, sprint planning, and backlog grooming. Consult on PLM configuration issues, digital thread integration, and MBSE alignment. Contribute to the PLM roadmap and evaluate new tools and technologies like OpenPDM. Provide support for deployment, monitoring, and optimization of PLM tools. Assist with technical documentation, project status updates, and stakeholder presentations. Basic Qualifications 2 5 years of experience in PLM Teamcenter development and integration. Proficiency in customizing, configuring, and deploying PLM platforms. Strong communication, leadership, and cross-functional collaboration skills. Familiarity with DevSecOps practices and agile development methodologies. Preferred Qualifications Hands-on experience with Teamcenter Systems Modeler and OpenPDM. Understanding of MBSE, digital twin, or digital thread concepts. Ability to drive end-to-end solutions from design to implementation. Strong analytical and organizational skills with a proactive attitude. At Pratt & Whitney, we're redefining the future of aerospace. Join us to be part of a world-class team creating innovative technologies that power modern flight and sustainable innovation. Equal Opportunity Statement We are an equal opportunity employer and consider all qualified applicants without regard to race, color, religion, sex, national origin, disability, or protected veteran status. Apply Now Explore your potential with Pratt & Whitney. Apply today and be part of the digital transformation in aerospace engineering.

Role: System Administrator Experience Required: Minimum of 4+ years of relevant experience Location: Bangalore Notice Period: Open Preferably Immediate Joiners Employment Type: Full-Time About Aezion: Aezion is a forward-thinking technology solutions provider, specializing in custom software development, AI-driven solutions, and enterprise digital transformation. As a trusted digital engineering partner in the USA, we are committed to exceeding client expectations by delivering results that transform clients into long-term partners. Our promise: We get it right or make it right. At Aezion, we believe that work is more than just a job it s a ministry that reflects our values. We are dedicated to delivering excellence throughout the entire project lifecycle, from design and development to hosting, maintenance, and support. Our Culture: Aezion is a mission-driven company with a purpose rooted in service: Love others like Christ. Guided by our core values Love, Dependability, Humility, Diversity, Speed, and Innovation we aim to provide exceptional service. Our 200+ dedicated employees work together to turn our customers into lifelong partners, fueling their success through a commitment to excellence. Role Overview: As a System Administrator at Aezion, you will be pivotal in designing, implementing, and maintaining our IT infrastructure. You will ensure the reliability, scalability, and security of systems, while also optimizing performance and minimizing downtime. This role requires you to collaborate with cross-functional teams to develop infrastructure solutions that align with the business s strategic goals. Key Responsibilities: Provide day-to-day technical support for desktops, laptops, and servers, ensuring minimal downtime for end-users. Troubleshoot and resolve hardware, software, and network-related issues across the organization. Install, configure, and maintain both Windows and Linux operating systems. Manage user accounts, permissions, and security settings within Active Directory and other identity management systems. Deploy, configure, and maintain enterprise applications, antivirus solutions, and other security tools. Support and troubleshoot peripheral devices such as printers, scanners, and mobile devices. Assist with network connectivity issues, including Wi-Fi, LAN, and VPN configurations. Perform regular system updates, patch management, and ensure compliance with security protocols. Document technical procedures, troubleshooting solutions, and best practices for internal use and knowledge sharing. Provide training and support to users regarding IT policies, security, and best practices. Required Skills and Experience: Proven experience with Windows & Linux desktop and server environments. Strong troubleshooting skills for hardware, software, and network issues. Familiarity with Active Directory, Group Policy, and user management processes. Knowledge of IT security best practices, including antivirus solutions and endpoint protection. Expertise in software installation, driver configurations, and system updates. Experience with remote desktop support tools. Basic understanding of networking concepts such as IP addressing, DNS, DHCP, and VPN. Proficiency in supporting Office 365, email clients, and enterprise-level applications. Excellent customer service and communication skills for providing end-user support. IT certifications such as CompTIA A+, Microsoft Certified (MCP, MCSA), or ITIL are highly desirable.

Role: Senior SEO Executive Experience Required: Minimum of 4+ years of relevant experience Location: Bangalore Notice Period: Open Immediate joiners preferred Employment Type: Full-Time About Aezion: Aezion is a leading technology solutions provider, specializing in custom software development, AI-driven solutions, and digital transformation for enterprises. As one of the trusted digital engineering partners in the USA, we are committed to delivering excellence by exceeding client expectations across all stages of the project lifecycle architecting, designing, developing, hosting, maintaining, and supporting. We live by our core promise: "Get it right, or make it right." At Aezion, we view work as a ministry, an expression of our values, where results not only transform our clients but also forge lasting partnerships. Our Culture: At Aezion, we are a mission-driven organization guided by our Purpose Love others like Christ and our values: Love, Dependability, Humility, Diversity, Speed, and Innovation. We believe service defines us, and our dedicated team of 200+ employees work tirelessly to transform our customers into lifelong partners. Through service excellence, we aim to impact lives and drive success. Role Overview: We are seeking a skilled and motivated Senior SEO Executive to join our dynamic team. You will be responsible for driving organic search growth and improving visibility across search engines. This role will involve developing SEO strategies, conducting keyword research, optimizing on-page elements, building backlinks, and monitoring performance using SEO tools. Additionally, you will collaborate with cross-functional teams to align SEO efforts with broader marketing and content goals. Key Responsibilities: SEO Strategy Development: Formulate and implement effective SEO strategies to improve organic search visibility and drive traffic to the website. Keyword Research: Conduct comprehensive keyword research to identify high-value search terms relevant to Aezion s target audience and industry. On-Page Optimization: Optimize on-page content, including metadata, headers, image alt tags, and internal links, to enhance search rankings and relevance. Content Collaboration: Work closely with the content team to ensure all published content adheres to SEO best practices and targets strategic keywords. Technical SEO: Identify and resolve technical SEO issues, such as crawl errors, page speed optimization, mobile-friendliness, and XML sitemaps. Collaborate with web developers to implement technical SEO best practices across the site. Link Building: Build high-quality backlinks through outreach, guest blogging, and content promotion. Performance Monitoring & Reporting: Track, analyze, and report on organic performance metrics (traffic, rankings, bounce rate, etc.) using tools like Google Analytics, Google Search Console, and other SEO platforms. Provide actionable insights for continuous improvement. Social Media Integration: Develop and implement a social media content strategy that aligns with the overall marketing goals. Manage Aezion s social media presence across platforms like Facebook, Twitter, LinkedIn, and Instagram. Engagement Monitoring: Monitor social media channels for mentions, comments, and messages, responding promptly to inquiries and feedback to maintain brand reputation. Required Skills and Experience: SEO Expertise: At least 4+ years of hands-on experience in SEO, including keyword research, on-page optimization, and link building. Content & Technical SEO: Proven experience in optimizing both content and technical SEO elements to improve rankings and user experience. Analytics & Reporting: Proficiency with SEO tools such as Google Analytics, Google Search Console, Ahrefs, SEMrush, or similar platforms. On-Page & Off-Page SEO: Strong understanding of on-page optimization techniques (metadata, content, internal linking) and off-page strategies (backlink building). Social Media Savvy: Experience in managing and optimizing social media content to support SEO and marketing initiatives. Communication Skills: Strong written and verbal communication skills, with the ability to collaborate effectively with cross-functional teams. Problem-Solving: Ability to identify and resolve SEO challenges, from technical issues to content optimization. Preferred Qualifications: Experience with SEO in a competitive digital environment, preferably in technology or software services. Familiarity with CMS platforms (WordPress, Joomla, etc.) and basic HTML/CSS. Certifications in SEO or related fields (e.g., Google Analytics, SEMrush, or HubSpot) are a plus.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Job Overview Role: SEO Architect (Web Analytics & SEO Optimization Specialist) Job Title: Staff Technical Systems Analyst About Juniper Networks At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Summary We are looking for an experienced and innovative SEO Architect to join our growing Future of X, Digital Experience team. This role will primarily focus on optimizing website performance, implementing SEO strategies, and leveraging web analytics tools to drive data-backed decisions for enhanced visibility, engagement, and conversion. The ideal candidate will combine technical SEO expertise with an in-depth understanding of web analytics to improve organic search performance, user experience, leverage AI technology, and overall site functionality. Key Responsibilities SEO Strategy Development and Implementation Lead the development and execution of comprehensive SEO strategies for websites and digital platforms. Perform thorough keyword research, competitive analysis, and industry trend monitoring to inform SEO planning. Design and implement on-page and off-page optimization strategies, including metadata, content, internal linking, and backlink development. Web Analytics Integration and Optimization Manage and optimize the implementation of web analytics tools (e.g., Google Analytics, Adobe Analytics, Google Search Console). Leverage web analytics data to assess SEO performance, identify opportunities, and guide optimization strategies. Create and maintain SEO dashboards and reports for stakeholders, delivering actionable insights based on data trends. Technical SEO & Website Audits Conduct comprehensive technical audits to identify issues affecting search rankings, such as site speed, mobile optimization, crawl errors, and indexing problems. Collaborate with development teams to implement technical SEO improvements and troubleshoot issues related to structured data, schema markup, redirects, and URL optimization. Recommend and execute solutions to enhance site architecture, navigation, and URL structure for better crawlability and user experience. Content Optimization and Performance Work closely with content teams to ensure SEO best practices are followed for content creation, optimization, and syndication. Monitor content performance and implement adjustments to improve rankings, CTR, and conversion rates. Advise on content strategy, ensuring alignment with SEO goals and audience intent. SEO Reporting & KPIs Define and track key SEO metrics and KPIs such as organic traffic, conversion rates, bounce rates, SERP rankings, and backlink profile health. Provide regular performance reports to stakeholders, highlighting trends, insights, and action plans. Work with cross-functional teams to set clear performance targets and SEO goals. Cross-Functional Collaboration Partner with marketing, product, UX/UI, and engineering teams to ensure SEO alignment in all digital initiatives. Advise on SEO-related decisions for site redesigns, A/B testing, and new feature launches. Stay updated on industry trends and best practices to share insights with internal teams and improve SEO strategies. Qualifications Education Bachelor's degree in Computer Science, or a related field (or equivalent experience). Experience 10+ years of hands-on experience in SEO, including a focus on web analytics and technical SEO. Proven experience in leveraging web analytics tools (Google Analytics, Adobe Analytics) to inform decision-making and drive SEO performance. Strong understanding of SEO tools, ranking algorithms, and industry trends. Experience with CMS platforms (e.g., WordPress, Salesforce CMS) and HTML/CSS for basic site edits. Familiarity with AI technology, RAG-based solutions, and understanding of data science and ML techniques. Skills and Expertise Expertise in SEO best practices, including on-page, off-page, technical SEO, and content optimization. In-depth knowledge of web analytics platforms (Google Analytics, Google Tag Manager). Experience conducting and analyzing website audits and making actionable recommendations for SEO improvements. Strong analytical and problem-solving skills, with the ability to interpret complex data and translate it into actionable insights. Familiarity with web performance tools (e.g., PageSpeed Insights, Lighthouse) and conversion rate optimization (CRO) tools. Excellent communication skills, capable of presenting data-driven insights to both technical and non-technical teams. Preferred Qualifications Advanced certifications in SEO, Google Analytics, or other relevant digital marketing fields. Experience with advanced technical SEO strategies, including JavaScript SEO, server-side rendering, and international SEO. Experience in managing large-scale SEO projects with cross-functional teams. Familiarity with marketing automation and CRM platforms. Qualification : Bachelor's degree in Computer Science, or a related field (or equivalent experience).

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.