Digital Design Flow Jobs in Bengaluru

Product Manager Payments Location: Bengaluru Work Type: Full Time Experience: 2 6 years About Tazapay Tazapay is a leading fintech platform for cross-border businesses. We provide local and global collections, holding, and payouts across multiple markets. As we expand into the digital asset ecosystem, we are building comprehensive crypto and stablecoin payment solutions to meet the growing demand for blockchain-based cross-border transactions. About the Team At Tazapay, product development is highly collaborative, involving engineering, design, partnerships, legal, risk, operations, and go-to-market teams. The cross-border payment platform team owns the core features of Tazapay s Payment Platform, including Payins, Payouts, and crypto/stablecoin infrastructure. Role Overview As Product Manager Payments, you will lead the design, development, and launch of global payment rails across both traditional and crypto/stablecoin systems. You will ensure enterprises can successfully build and operate payment operations using Tazapay s platform, bridging fiat and digital asset ecosystems. Key Responsibilities Design and launch crypto/stablecoin payment flows, including digital wallet integrations, stablecoin/blockchain settlements, and multi-chain payment solutions. Drive feature development and market launches for stablecoins like USDC, USDT, and emerging stablecoins across blockchains such as Ethereum, Polygon, and Solana. Collaborate closely with engineering, legal, sales, support, and compliance teams throughout the product lifecycle to deliver seamless payment experiences. Integrate traditional banking rails with crypto payment options, providing merchants with unified access across all payment types. Navigate and ensure compliance with global crypto regulations, working with legal and compliance teams on AML/KYC, licensing, and emerging regulatory requirements. Use a data-driven approach to analyze blockchain transactions, payment metrics, and user behavior to optimize product performance. Who You Are Minimum Requirements 2 6 years of product management experience, with at least 2 years in fast-paced fintech or crypto startups. Hands-on experience with crypto/blockchain integrations, stablecoins, wallet connectivity, smart contracts, or digital asset payment systems. Deep understanding of stablecoin ecosystems (USDC, USDT, DAI, and algorithmic stablecoins) and their underlying mechanisms. Expertise in financial API design with experience in both traditional and blockchain/crypto API integrations. Strong technical understanding of blockchain fundamentals: transaction lifecycles, gas optimization, multi-chain architecture, and consensus mechanisms. Knowledge of crypto compliance requirements and emerging global regulatory frameworks (AML/KYC, licensing, etc.). Analytical mindset with ability to leverage blockchain and payment data to drive product decisions. Preferred Qualifications Degree in Computer Science, Engineering, Finance, or related field, with blockchain coursework or certifications. Proven track record of launching successful crypto/stablecoin payment products or features at scale. Hands-on experience with major blockchain networks, ecosystems, development tools, and integration patterns. Experience collaborating with crypto exchanges, wallet providers, or blockchain infrastructure companies. Qualification : Degree in Computer Science, Engineering, Finance, or related field, with blockchain coursework or certifications

Staff Software Engineer AI & Automation Location: Bengaluru Company: Okta, The World s Identity Company Experience: 8+ Years Type: Full-Time About Okta Okta is the world s leading identity platform. We empower people to securely access any technology, anywhere, on any device. With products like the Okta Platform and Auth0, we place identity at the core of business security, enabling growth through safe digital transformation. At Okta, we value diverse perspectives and experiences. We believe in learning, collaboration, and building an inclusive environment where everyone belongs. About the Team The Business Technology - Shared Services team is at the forefront of Okta s internal digital transformation. We focus on building intelligent, automated platforms that simplify operations and deliver smarter, faster experiences to both employees and customers. We collaborate across engineering, data science, security, and business units to deliver cutting-edge solutions powered by Generative AI (GenAI), virtual agents, workflow orchestration, and intelligent recommendations. The Opportunity As a Staff Software Engineer, you ll play a critical role in designing and developing AI-powered platforms that drive automation, scale, and intelligence across Okta s business. You ll help make LLM-powered solutions and intelligent automation a reality for the enterprise ensuring performance, security, and reliability at scale. This is a hands-on, individual contributor (IC) role, ideal for engineers who are passionate about solving complex problems, architecting scalable systems, and pushing the boundaries of AI integration. What You ll Do Design & Build: Develop scalable backend services that embed GenAI and automation into core business workflows (e.g., virtual agents, document intelligence, smart routing). Collaborate Across Teams: Work closely with product managers, data scientists, and other engineers from ideation to production. Architect for Scale: Make key architectural decisions around LLM integration, API design, data flow, and observability. Code with Excellence: Write clean, secure, and maintainable code in Python, Java, or similar languages. Build for Production: Use Docker, Kubernetes, and CI/CD pipelines to build and deploy high-availability services. Champion Best Practices: Promote high standards for testing, security, code reviews, and operational readiness. Mentor & Guide: Support a collaborative team culture through peer mentorship and design reviews. What You ll Bring 8+ years of experience in software engineering with a strong track record of building and maintaining production-grade, cloud-native services. Expertise in distributed systems, API development, and cloud infrastructure (AWS, GCP, or Azure). Proficiency in Python, Java, or Go. Experience with Docker, Kubernetes, and observability tools (e.g., Prometheus, Grafana, ELK). Exposure to AI/ML concepts and eagerness to work with LLMs, NLP, or automation platforms. A strong sense of ownership, collaborative mindset, and a bias toward action. Passion for learning and working with emerging technologies especially in the AI and automation space. Why Join Okta Make AI Real: Help move GenAI from experimentation to enterprise-wide impact. Build with Purpose: Work on challenges that simplify and secure Okta s internal operations. Grow in a Human-Centered Culture: Join a humble, technically driven team that values learning, excellence, and personal growth. Join Okta and shape how identity, AI, and automation come together to power the modern enterprise.

Job Title: Assistant Manager Process Design Location: Bangalore Employment Type: Full-time About Zeta: Zeta is a Next-Gen Banking Tech company empowering banks and fintechs to launch innovative financial products. Co-founded by Bhavin Turakhia and Ramki Gaddipati in 2015, Zeta s flagship platform Zeta Tachyon is the industry s first modern, cloud-native, fully API-enabled banking stack. With over 15 million cards issued globally, Zeta Tachyon enables: Seamless, digital-first cardholder experiences Embeddable banking support for partners Hyper-personalized card programs Rapid product launches through web-based configurators Robust compliance and fraud management capabilities Zeta is working with major banks and fintechs globally and has 1,700+ employees, with 70% in R&D. The company raised $280M at a $1.5B valuation in 2021, backed by SoftBank, Mastercard, and other top investors. Role Overview: We are looking for an Assistant Manager Process Design who will drive automation, process transformation, and customer experience optimization. This role involves working closely with Product, Engineering, and Operations teams to build scalable and efficient customer support processes. Key Responsibilities: Identify opportunities for automation and process improvements and create a transformation roadmap. Design intuitive chatbot customer flows to enhance digital experience. Re-engineer existing processes to improve First Time Resolution (FTR) and overall customer satisfaction (CSAT). Set up proactive monitoring for customer journey leakages and coordinate with relevant teams for quick resolution. Establish a robust Voice of Customer (VOC) mechanism using inputs from multiple channels (email, chat, NPS, social media). Define and implement strategic process transformation initiatives to enhance the customer journey. Lead cross-functional efforts with Product, Engineering, and Operations to deliver process excellence. Support recovery work when necessary, ensuring business continuity. Deliver timely status updates to management and project stakeholders. Required Skills & Competencies: 2 4 years of experience in Process Design, Process Excellence, or Operational Transformation. Background in Operational Metrics (CSAT, AHT, FTR, Re-opens, FRT). Strong knowledge of Excel and PowerPoint. Six Sigma certification (preferably Black Belt) and experience with Lean methodologies. Familiarity with AI, automation, and digital tools in customer support. Excellent analytical and critical thinking abilities. Strong decision-making skills in real-time scenarios. Proven ability to work with multiple stakeholders to drive results. Excellent verbal and written communication skills. Qualifications: Bachelor s Degree (B.E./B.Tech) or a Postgraduate Degree / MBA in a relevant field. Equal Opportunity Employer: Zeta celebrates diversity and is committed to creating an inclusive environment for all. We welcome applicants from all backgrounds, cultures, and communities and believe a diverse workforce is key to our success. Qualification : Bachelors Degree (B.E./B.Tech) or a Postgraduate Degree / MBA in a relevant field

Job Title: Lead Product Engineer Location: Bengaluru, Karnataka, India Department: Product Engineering Experience: 6 10 years About TheMathCompany TheMathCompany (MathCo ) is a global Enterprise AI and analytics firm helping Fortune 500 and Global 2000 organizations drive better decision-making through custom-built AI solutions. With our proprietary platform NucliOS, we power scalable, reusable, and intelligent products that accelerate digital transformation across industries. At MathCo, we empower our engineers to innovate, take ownership, and work on cutting-edge enterprise-grade products from scratch. If you re passionate about full-stack product development and thrive in a dynamic, high-impact environment, we d love to talk to you. About the Role As a Lead Product Engineer, you will be responsible for the architecture, development, and deployment of full-stack applications that are critical to our enterprise clients success. You ll lead a cross-functional team and work closely with product managers, designers, and data scientists to deliver high-performance solutions that scale and transform. This role combines hands-on coding, system architecture, and team leadership, and is ideal for engineers looking to make a direct impact on product direction and execution. Key Responsibilities 1. Full Stack Development Build and maintain RESTful APIs and microservices using languages like Python or Node.js. Design and develop scalable and maintainable UI components using modern front-end frameworks (e.g., React, Vue, Angular). Architect and manage application databases (SQL & NoSQL). Integrate with authentication/authorization protocols (e.g., OAuth2, OIDC, SAML). Participate in the full product lifecycle from ideation and development to deployment and support. 2. Product Development & Collaboration Translate business requirements into technical solutions in collaboration with product managers and designers. Provide technical leadership and guidance to the development team. Optimize systems for performance, scalability, and reliability. 3. Code Quality & Testing Write clean, efficient, well-documented code following best practices and industry standards. Conduct and participate in code reviews. Develop and maintain automated test frameworks; ensure unit, integration, and end-to-end testing coverage. Oversee CI/CD pipelines and manage cloud-based deployments. Must-Have Technical Skills 6 10 years of experience in full-stack development and system design. Proficiency in backend languages like Python, Node.js (bonus: Rust, Go). Strong front-end experience with HTML, CSS, JavaScript, and frameworks like React, Angular, or Vue.js. Expertise in REST APIs, microservices, and database design (ER modeling, data flow, API integration). Hands-on with PostgreSQL, MySQL, MongoDB, or similar. Experience deploying applications on cloud platforms (AWS, Azure, GCP). Familiarity with Docker, Kubernetes, and infrastructure tools like Terraform, CloudWatch. Version control and DevOps experience with GitHub, Azure DevOps, and CI/CD pipelines. Non-Technical & Soft Skills Strong knowledge of Agile methodologies (SCRUM). Excellent problem-solving and debugging capabilities. Strong communication and collaboration skills across teams. Ability to manage multiple projects in a fast-paced environment. Work with some of the best minds in data science, engineering, and AI. Drive high-impact product development used by Fortune 500 companies. Be part of a flat, inclusive, and innovation-driven workplace culture. Access to cutting-edge tools, custom-built platforms, and rapid experimentation. Apply now and help build world-class AI-driven solutions with MathCo.

Job Title: Assistant Manager Process Design Location: Bangalore, India Employment Type: Full-time About Zeta Zeta is a Next-Gen Banking Tech company empowering banks and fintechs to launch modern, cloud-native financial products at speed and scale. Founded in 2015 by Bhavin Turakhia and Ramki Gaddipati, Zeta s flagship platform, Tachyon, is the world s first modern, API-first banking stack supporting issuance, processing, lending, core banking, fraud, risk, and more all under one roof. With over 15 million cards issued on its platform globally, Zeta partners with leading banks and fintechs to deliver digital-first experiences, hyper-personalized programs, and rapid product innovation. We are a global team of 1700+ employees, with more than 70% dedicated to R&D, and are backed by major investors including SoftBank and Mastercard, with a valuation of $1.5 billion. Role Summary Zeta is seeking a driven and analytical Assistant Manager Process Design to spearhead customer journey improvements and process automation. You will be responsible for transforming customer-facing processes to enhance user experience, improve operational efficiency, and contribute to strategic initiatives across Product, Engineering, and Operations teams. Key Responsibilities Process Automation & Transformation: Identify improvement areas, create transformation roadmaps, and implement automation strategies to enhance service delivery. Customer Journey Mapping: Design chatbot flows and other digital experiences to ensure seamless, intuitive customer interactions. Continuous Improvement: Evaluate and re-engineer existing workflows to increase First Time Resolution (FTR), reduce Average Handling Time (AHT), and drive CSAT. Monitoring & Proactive Support: Establish early-warning systems and collaborate cross-functionally to prevent and address service issues. Voice of Customer (VOC): Build robust VOC mechanisms by analyzing feedback from email, chat, NPS, social media, etc., to drive actionable improvements. Strategic Initiatives: Lead cross-functional initiatives with Product, Engineering, and Business Ops to elevate customer experience and operational excellence. Project Reporting: Deliver timely and detailed project updates and reports to stakeholders and leadership. Skills & Competencies Experience in Process Design, Process Excellence, Automation, or Operational Excellence. Prior work with Customer Support teams and KPIs like CSAT, AHT, FTR, Reopens, and First Response Time. Proficiency in Microsoft Excel and PowerPoint for analytics and presentations. Working knowledge of Six Sigma (preferred: Black Belt), Lean methodologies, and digital tools. Familiarity with AI, chatbots, workflow tools, and digital customer experience technologies. Strong analytical thinking, decision-making, and stakeholder management skills. Exceptional communication skills, both verbal and written. Qualifications & Experience Education: BE/B.Tech or Postgraduate/MBA from a recognized institution. Experience: 2 4 years in a relevant role involving process optimization or customer journey transformation. At Zeta, we believe People Must Grow. You ll work with brilliant minds, cutting-edge technologies, and game-changing products. Our culture promotes innovation, continuous learning, and an inclusive workplace where every individual is valued. Equal Opportunity Statement Zeta is an equal opportunity employer. We celebrate diversity and are committed to building an inclusive environment for all employees regardless of background, gender, religion, ethnicity, or identity. Qualification : BE/B.Tech or Postgraduate/MBA from a recognized institution.

UX/UI Designer About The Team Rubrik s Marketing Team is growing, and we're looking for an exceptional, curious, user-obsessed UX/UI Designer who loves combining creativity with smart, data-driven thinking. If you are someone who can transform complex challenges into beautifully simple solutions while pushing creative boundaries; if you're excited about creating Marketing experiences that are not only captivating but backed by evidence and built for real people; if you love design and geek out over the details; if you have a portfolio that makes people say 'wow,' we d love to meet you. You ll help shape the look, functionality, and especially the feeling of our web presence but more importantly you ll do so with purpose, using data to inform decisions, validate ideas, and continuously improve how users interact with our digital experiences. From user flows and wireframes to high-fidelity mockups, you'll design with empathy and iterate with intention. What you'll do Collaborate closely with Dev, Creative, Web, Digital, and cross-functional partners to translate business goals into intuitive, elegant web experiences. Design and iterate on responsive UI components that support accessibility, usability, and brand consistency, all while building and evolving our design system with scalability and consistency in mind. Leverage analytics, user feedback, and testing to drive user-centric design decisions and optimize performance across key user journeys. Skills: Portfolio: A strong portfolio showcasing your UX/UI design skills, including examples of user research, wireframing, prototyping, and stunning visual design that reflect a deep understanding of design principles and user-centred design best practices. Design Tools: Proficiency in design tools such as Figma or similar for prototyping, wireframing, and visual design. Strong ability to create interactive prototypes and iterate based on user feedback and insights from usability testing. Design Systems: Experience in working with or contributing to design systems, ensuring consistency and scalability across different teams and product components. Apply design thinking principles to identify and solve user problems. Focus on creating intuitive, engaging, and meaningful user experiences that align with business goals and user needs. Experience in responsive web design and accessibility best practices. User Research: Experience in conducting user research, usability testing, analyzing data, and translating insights into actionable design solutions that prioritize user needs and business goals. Communication & Collaboration: You're great at expressing your ideas, both in conversations and in writing. You can confidently explain your design choices and work well with people from different teams. You help keep everyone on the same page by documenting important decisions and processes, and you enjoy sharing knowledge with your fellow designers. You also have a knack for maintaining high design standards and making sure everything fits within the big picture. Experience you'll need Experience of 7-10 years in UX/UI design, with a focus on web or software products, and a proven track record of delivering end-to-end user experiences. Expertise in Figma. Familiarity with HTML/CSS or front-end development. Familiarity with Adobe Experience Manager (CMS). A degree in Interaction Design, Human-Computer Interaction, Graphic Design, or a related field. Join Us in Securing the World's Data Rubrik (NYSE: RBRK) is on a mission to secure the world s data. With Zero Trust Data Security , we help organizations achieve business resilience against cyberattacks, malicious insiders, and operational disruptions. Rubrik Security Cloud, powered by machine learning, secures data across enterprise, cloud, and SaaS applications. We help organizations uphold data integrity, deliver data availability that withstands adverse conditions, continuously monitor data risks and threats, and restore businesses with their data when infrastructure is attacked.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Graphic Designer Location: Mumbai Type: Full-Time Department: Design Job Summary: A Graphic Designer combines creativity with technical expertise to produce visually compelling designs. You will be responsible for designing visual concepts for both digital and print mediums, ensuring a high standard of design quality that aligns with client needs and brand identity. Key Responsibilities: Designing Visual Concepts: Develop original design concepts to communicate the message or theme for client campaigns, branding, and marketing materials. Creating Layouts and Artwork: Produce layouts, illustrations, and other graphic elements for print and digital projects, ensuring designs meet brand guidelines. Collaborating with Teams: Work with marketing, copywriting, and other creative teams to ensure cohesive branding and messaging across projects. Revising Designs: Take client feedback into account and revise designs accordingly to meet specifications, deadlines, and quality standards. Maintaining Consistency: Ensure all design elements are aligned with the company s or client s brand identity, ensuring they are visually appealing across all platforms. Required Skills and Qualifications: Proficiency in Design Tools: Advanced knowledge of design software such as Adobe Photoshop, Illustrator, InDesign, and other graphic design tools. Creative Conceptualization: Strong ability to generate creative ideas, develop concepts, and transform them into visually effective designs. Typography and Color Theory: Solid understanding of typography, color schemes, and visual storytelling. Print and Digital Design: Experience creating designs for both print and digital media, including brochures, social media content, banners, posters, websites, and more. Attention to Detail: A keen eye for detail and precision, ensuring that all design elements are executed flawlessly. Qualifications: Educational Background: Bachelor s degree in Graphic Design, Visual Arts, Fine Arts, or a related field. Experience: 1-3 years of experience for junior roles, with 3-5+ years required for mid-level and senior roles. Portfolio: A strong portfolio showcasing a variety of graphic design work across different mediums and industries. Certifications (Optional but Beneficial): Adobe Certified Expert (ACE) or other relevant design certifications. Qualification : Bachelors degree in Graphic Design, Visual Arts, Fine Arts, or a related field.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Job Overview As a Tools Support & Infrastructure Engineer at Qualcomm, you'll play a vital role in supporting and enhancing the design flows and infrastructure for Qualcomm's Digital Signal Processing (DSP) team. The DSP design team delivers high-performance DSP cores that are integral to Qualcomm's multi-tier SoC roadmap, particularly for mobile applications. This position involves managing DSP design databases, developing automation tools to streamline the verification process, and collaborating with global teams to optimize design efficiency and quality. Key Responsibilities Manage DSP Design Database: Oversee the DSP design database, supporting design and verification teams with infrastructure needs. Build Automation: Create new automation tools to enhance the productivity of design verification teams, making it easier to debug simulation failures. Collaborate with Global Teams: Work with Qualcomm s global DSP design teams (architecture, implementation, post-silicon, and back-end teams) to enhance DSP IP infrastructure. Improve Tool Methodologies: Design and deploy new tool methodologies to continuously improve the quality, efficiency, and effectiveness of design and verification processes. Support Design Flows: Contribute to and improve design flows, ensuring the seamless integration of tools and resources used by design teams. Minimum Qualifications Educational Requirements: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 5+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant work experience. Skills & Experience Programming & Tools Support: 3-10 years of experience in programming, database management, and providing tools support for complex DSP IP designs. Automation Expertise: Extensive experience in building automation tools that improve design and verification processes. Programming Languages: Expertise in C++ and Java. Scripting & Automation: Proficiency with scripting languages and tools such as Perl, Python, Shell, Makefiles, and TCI. Analytical Skills: Strong analytic, programming, and debugging abilities. Object-Oriented Programming (OOP): Deep understanding of OOP concepts. Web Programming: Familiarity with Java for web programming is a plus. Unix Environment: Solid understanding of the Unix environment. Digital Design Flows: Knowledge of digital design flows is a plus. Communication: Excellent interpersonal and communication skills, with the ability to work collaboratively with global teams.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.