DRC Design Rule Check Jobs in Bengaluru

Position: Marketing Manager / Deputy Manager Type: Full Time Experience: 8 10 Years Location: Bangalore Role Purpose To lead integrated marketing efforts that drive lead generation, customer engagement, and sales enablement across digital platforms, marketing automation systems, and sales operations. This position is crucial in aligning marketing initiatives with sales productivity, ultimately boosting market share and customer reach for the organization. Key Responsibilities Market Analysis & Product Communication Conduct competitive benchmarking, market research, and customer insight gathering for the concrete equipment sector. Develop technical marketing collateral and product content in collaboration with Product Management & Engineering teams. Create newsletters, mailers, and presentations aligned with brand guidelines to support sales efforts. Sales Operations Support Partner with Sales teams to improve CRM usage, lead tracking, and pipeline visibility. Enhance customer journey mapping and conversion processes with sales and product teams. Analyze sales data for trends, opportunities, and engagement gaps. Support the design and implementation of sales enablement tools and mobile sales apps. Digital Marketing & Lead Generation Run and optimize SEO, SEM, and paid media campaigns to increase inbound leads. Manage digital presence across social media, email, and landing pages. Drive performance from platforms like IndiaMART and apply corrective actions where needed. Marketing Automation & Tools Implement and manage platforms such as HubSpot, Zoho Marketing Plus, Salesforce Marketing Cloud, or Marketo. Automate campaigns, lead scoring, and segmentation to enhance efficiency. Track campaign performance and optimize for improved ROI. Events, Exhibitions & Campaigns Plan and execute industry event participation (e.g., EXCON, BAUMA, Concrete Show) in coordination with marketing leadership. Support product launches, roadshows, BTL activities, and customer meets. Oversee vendor coordination and logistics for successful event execution. After-Sales Marketing & Customer Engagement Partner with After-Sales and Parts teams to roll out service campaigns, loyalty programs, and feedback initiatives. Design post-sale campaigns and customer health check content to maintain engagement. Reporting & Analytics Maintain dashboards to track digital, lead conversion, and sales enablement KPIs. Ensure CRM data hygiene and provide actionable insights. Assist with marketing budgeting and monthly expense tracking. Desired Skills & Competencies Strong B2B marketing background, preferably in industrial or capital goods sectors. Proficiency in CRM platforms (Salesforce, Zoho CRM) and marketing automation tools (HubSpot, Marketo). Excellent content creation skills for technical and product marketing. Strong analytical mindset with data-driven decision-making. Effective collaboration with cross-functional teams. Experience with SEO tools, Google Analytics, and LinkedIn Campaign Manager. Educational Qualifications MBA/PGDM in Marketing, Sales, or Business Analytics from a reputed institute. Preferred Industry Background B2B Industrial, Capital Goods, Construction Equipment, or Automotive Components. Qualification : MBA/PGDM in Marketing, Sales, or Business Analytics from a reputed institute

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Join Us in Revolutionizing the Data Storage Industry We re at the forefront of a transformative tech movement, fundamentally reshaping the data storage industry. At Pure Storage, you ll have the chance to lead with innovative thinking, grow alongside us, and collaborate with the smartest team in the industry. If you re ready to make a lasting impact and seize boundless opportunities, come join us! SHOULD YOU ACCEPT THIS CHALLENGE... As an Instructional Designer, you will create high-impact learning experiences that empower our partners. This role is critical in designing, developing, and delivering training programs that provide our partners with the knowledge and skills necessary to succeed with our products, solutions, and go-to-market strategies. Working as part of the GTM & Partner Experience team, you will design scalable, engaging learning solutions that drive partner adoption, sales effectiveness, and technical expertise. You'll collaborate cross-functionally with Subject Matter Experts (SMEs), partner managers, sales, and technical teams to ensure the training aligns with business goals and partner needs. In This Role, You Will: Develop structured learning courses and paths tailored to various partner personas (e.g., sales, technical sales, marketing, operations, executives), ensuring they have the right knowledge to drive business success. Design and develop effective and engaging learning modules using Articulate 360, incorporating videos, simulations, and instructional best practices. Convert complex content into clear, concise, and engaging training materials, such as e-learning modules, instructor-led training, job aids, videos, infographics, simulations, and assessments. Collaborate with SMEs to gather and refine content that aligns with learning objectives. Apply instructional design models (e.g., ADDIE, SAM), gamification, and interactive learning strategies to create impactful experiences. Utilize our Intellum LMS (Learning Management System) to publish, track, and manage learning content. Develop assessments to measure learning outcomes and knowledge retention. Continuously evaluate training effectiveness using metrics, data, and partner feedback to assess engagement, course completion rates, and learning impact, iterating on content as needed. Stay updated on trends in instructional design, e-learning technologies, and gamification to enhance training programs. What You ll Need to Bring to This Role: Basic Qualifications: Bachelor s or Master s degree in Instructional Design, Learning & Development, Education, or a related field. 12+ years of experience in instructional design, curriculum development, or e-learning development. Proficiency in e-learning authoring tools (Articulate Storyline, Rise, Captivate, Camtasia, Vyond, etc.) is a plus. Familiarity with Intellum LMS or similar learning platforms, and SCORM-compliant content. Experience designing training programs for partners, channel sales, or reseller networks. Strong writing, communication, and project management skills. Ability to translate complex technical and sales topics into engaging, digestible learning experiences for partners. Solid understanding of adult learning principles, instructional methodologies, and training needs analysis. Excellent project management skills, attention to detail, and the ability to meet deadlines. What You Can Expect from Us: Pure Innovation: We celebrate those who think critically, embrace challenges, and aspire to be trailblazers. Pure Growth: We provide the space and support for you to grow alongside us and contribute meaningfully. Pure Storage has been recognized as one of Fortune's Best Large Workplaces in the Bay Area, Fortune s Best Workplaces for Millennials, and certified as a Great Place to Work. Pure Team: We build each other up, setting aside egos for the greater good. Additionally, we understand the importance of a healthy work-life balance and offer various perks, including flexible time off, wellness resources, and company-sponsored team events. For more details, check out purebenefits.com. Qualification : Bachelors or Masters degree in Instructional Design, Learning & Development, Education, or related field.

Job Title: IMPO UAM Authorization Analyst Location: Bengaluru, India Unit: Johnson & Johnson Innovative Medicine Principal Operations (IMPO) Job Type: Full-Time Employment Type: Permanent About Johnson & Johnson: At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, profoundly impacting health for humanity. Role Purpose: The IMPO UAM Authorization Analyst role at Johnson & Johnson is responsible for enhancing user access security and compliance within global SAP S/4 systems, while driving key User Access Management (UAM) initiatives. This role supports business adaptation through SAP S/4 HANA implementation, focusing on core SAP Manufacturing, Order to Cash, Procure to Pay, and Finance processes. The position is part of the IMUAM team, ensuring security requirements are designed and implemented compliantly within the Transcend Program, a global initiative for business transformation. Key Responsibilities: Security Workshops & Role Design: Lead security workshops to gather business and compliance requirements for role design, ensuring validation post-build for S/4 HANA Roles and Authorization requirements. UAM Strategy Development: Develop UAM strategies involving composite roles, Fiori tiles, business roles/user personas, and data security/UI masking concepts for S/4HANA. Data Validation & Compliance Documentation: Perform data validation, conduct health checks, and provide compliance documentation to ensure proper security implementation. Role Design & Testing: Design, test, and implement rule sets for SAP S/4HANA role design, ensuring they align with security protocols. User Account Setup & Support: Support role data and user account setup. Provide advice on role design testing and coordinate business UAT activities. Authorization Defects Management: Manage authorization defects and provide support for user cutover and Hypercare activities during and post-implementation. Collaboration & Training: Work closely with the Business Adaptation team to facilitate training, communication, and readiness across regions. Assist in transitioning between project phases and operational support teams. Compliance & Security Audits: Ensure compliance with internal and external standards through regular SAP security assessments and audits. Issue Troubleshooting & Resolution: Troubleshoot and resolve complex SAP security issues to maintain a secure environment. Documentation Management: Develop and maintain comprehensive documentation for SAP security policies, procedures, and configurations. Mentorship & Team Development: Train and mentor junior team members, promoting the implementation of SAP security standard processes. Qualifications: Required: Educational Background: Bachelor s degree in a relevant field (preferably Risk Management, Compliance, Audit). Experience: 6-8 years of experience in UAM within an enterprise risk management framework. Demonstrated expertise in SAP GRC Access Control and Identity Management tools. Hands-on experience with end-to-end SAP S/4HANA implementation, including Fiori. Deep knowledge of SAP authorization concepts, Segregation of Duties (SoD) mitigation, and remediation strategies. Proficiency in risk matrix/rule set maintenance, data analysis, conversion, and migration. Tools & Platforms: Experience with teamwork platforms (e.g., Confluence, Jira, MS Teams). Project Management: Strong project management and collaboration skills with experience in remote and virtual environments. Language Skills: Fluent in English with outstanding oral and written communication skills. Additional Experience: Experience in the pharmaceutical domain is a plus. Preferred: Industry Experience: Experience in Life Sciences, Pharmaceuticals, or similar industries. Leadership & Innovation: Demonstrated leadership skills with the ability to embrace innovation and promote a culture of continuous improvement. Project Management: Previous experience in a PMO role managing large-scale SAP implementation projects. Cross-Cultural Team Collaboration: Ability to work effectively with team members from different cultural and technical backgrounds. Other Requirements: Hybrid Work: Ability to work on-site a minimum of three days per week, with up to two remote workdays based on the flexible work policy. Travel: May require up to 10% domestic and/or international travel. Diversity & Inclusion: Johnson & Johnson is an Affirmative Action and Equal Opportunity Employer. We are committed to fostering an inclusive and diverse work environment, and we encourage applicants from all backgrounds to apply. We value diversity and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, age, national origin, or veteran status. Qualification : Bachelors degree in a relevant field, with a preference for studies in Risk Management, Compliance, and Audit.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Sr. Member of Technical Staff - UI Engineering Location: Bengaluru Company: Aviatrix Experience: 3+ years About Aviatrix: Aviatrix is a leading cloud network security company trusted by over 500 enterprises globally. We specialize in simplifying and securing multi-cloud environments, providing a unified networking solution built specifically for the cloud. Role Overview: UI Engineering (Co-Pilot Team) We are seeking a Senior UI Engineer to join our Co-Pilot product development team. You will design, develop, and maintain high-quality UI solutions that offer customers seamless access to sophisticated cloud management and network security tools. Technical Requirements Core Competencies: Frontend Stack: Advanced proficiency in TypeScript, React, and Node.js. Web Standards: Expert knowledge of HTML5 and CSS3. API Integration: Solid understanding of REST APIs and asynchronous data handling. Version Control: Professional experience with Git and collaborative workflows. Education: BE/B.Tech in Computer Science or related field (or equivalent practical experience). Nice to Have / Bonus Skills: Design Systems: Experience with MUI (Material UI) or in-house design frameworks. Advanced Protocols: Exposure to gRPC, gRPC-web, and Go. Data Visualization: Familiarity with Elasticsearch and high-scale data dashboards. Cloud Domain: Previous experience in cloud networking or security sectors. Key Responsibilities Feature Development: Build efficient, scalable, and well-tested code for the Aviatrix product suite. UX Partnership: Collaborate with UX designers to translate complex requirements into intuitive user interfaces. System Maintenance: Manage bug fixes, UI enhancements, and participate in on-call rotations for field issues. Continuous Improvement: Contribute to the evolution of development processes and product quality. Benefits & Why Aviatrix Comprehensive Health: Private medical coverage, life assurance, and long-term disability. Financial & Growth: Pension scheme and a dedicated annual wellbeing stipend. Time Off: Generous holiday allowance and a flexible approach to work-life balance. Inclusivity: We value unique journeys if you are excited by the role, we encourage you to apply regardless of a perfect "checklist" match.

Analytics Engineer Location: Bengaluru Work Type: Full-Time About Postman Postman is the world s leading API platform, used by over 40 million developers and 500,000 organizations, including 98% of the Fortune 500. Our mission is to build an API-first world, simplifying every step of the API lifecycle and enabling teams to create better APIs, faster. Founded in Bengaluru, Postman is headquartered in San Francisco, with offices in Boston, New York, and Bengaluru. We are privately held, backed by Battery Ventures, BOND, Coatue, CRV, Insight Partners, and Nexus Venture Partners. The Opportunity We are seeking an Analytics Engineer to join our Data Team and help strengthen the foundation of our modern data stack. In this role, you will own critical transformation pipelines, design scalable data models, and ensure that our analytics environment is performant, reliable, and future-ready. You will operate with a high degree of independence, driving projects from design through production, while implementing best practices in dbt, semantic layers, medallion architecture, and lakehouse paradigms. Key Responsibilities Take ownership of large portions of our dbt project (3k+ models), ensuring scalability, maintainability, and adherence to best practices. Design and implement robust data models, including dimensional modeling, incremental strategies, and Slowly Changing Dimensions (SCDs). Establish and enforce dbt test coverage, automated quality checks, and CI/CD pipeline standards using GitHub Actions. Profile and optimize SQL queries and warehouse performance for efficiency and cost reduction. Build and refine our semantic layer, ensuring consistent business logic across Looker, Redash, and downstream tools. Collaborate with analysts and business partners to define metrics and deliver self-serve data assets. Document models, lineage, and transformation logic to make data discoverable and usable across the company. Contribute to shaping team standards and playbooks, collaborating with analysts on modeling and transformation best practices. Stay ahead of modern data stack innovations, including dbt metrics layer, universal semantic layers, data contracts, and observability. Enabling Self-Serve Analytics & AI Build transformations that empower business stakeholders and analysts to explore data confidently. Ensure metric definitions are consistent, discoverable, and reusable across BI tools. Prepare clean, structured, and accessible datasets for AI-driven initiatives like conversational analytics and anomaly detection. Partner with Data Science & ML teams to provide reliable pipelines that accelerate experimentation and AI/ML deployment. About You 3 5 years of experience in analytics engineering roles. Advanced SQL skills (query optimization, performance tuning). Strong proficiency in dbt Core: models, macros, snapshots, sources, and custom materializations. Solid background in data modeling techniques (Kimball, SCD handling, incremental pipelines). Practical experience with semantic layers and BI integration (LookML, dbt metrics, or equivalent). Familiarity with Medallion architecture and modern lakehouse approaches. Hands-on experience with Redshift; exposure to Databricks is a plus. Proficiency with GitHub and CI/CD pipelines for analytics code. Strong fundamentals in data quality, governance, and lineage tracking. Flexible schedule with a hybrid work model. Full medical coverage, flexible PTO, wellness reimbursement, and monthly lunch stipend. Access to wellness programs, team-building events, and donation-matching initiatives. An inclusive, collaborative culture where everyone can thrive and grow. Our Values Curiosity: Explore and innovate fearlessly. Transparency: Communicate openly about successes and failures. Focus: Set clear goals aligned with a bold vision. Inclusion: Every voice matters. Excellence: Deliver the best products and experiences together.

Job Title: Architect (Deputy Manager) Location: Bangalore Department: Design & Development Employee Type: Permanent Experience Range: 8 12 years Position Overview We are seeking an experienced Architect (Deputy Manager) with a strong background in high-rise residential and commercial projects. The ideal candidate will be responsible for managing the architectural design process from concept to completion, collaborating with internal teams and external consultants to ensure projects meet design excellence, compliance, and timelines. This role requires solid project management capabilities, a keen eye for detail, and a passion for sustainable, innovative design. Candidates with over 10 years of experience in architectural design and coordination will be well suited for this position. Key Responsibilities Project Management Manage architectural design projects to ensure timely delivery within scope and budget. Coordinate with cross-functional stakeholders, including internal teams and external consultants, to meet project requirements. Ensure accuracy and efficiency throughout the project lifecycle. Design Development Lead the creation and development of design concepts and detailed architectural drawings. Review and refine architectural plans, specifications, and models to maintain quality and compliance. Integrate sustainability and innovation into all design solutions. Team Collaboration Guide, delegate, and support junior team members in their tasks and professional development. Foster strong collaboration between architectural, structural, MEP, landscape, marketing, and sales teams. Liaise with site teams to ensure smooth execution and coordination. Regulatory Compliance Ensure all designs meet local building codes, zoning laws, RERA regulations, and company standards. Coordinate with relevant teams for documentation and approvals required for permits. Quality Assurance Conduct routine design reviews and quality checks to maintain design integrity and executional accuracy. Proactively address any design-related challenges that arise during the project. Innovation & Industry Trends Stay updated on the latest trends, tools, and techniques in architectural design. Introduce innovative design solutions, materials, and practices to improve project outcomes. Qualifications & Skills Education Bachelor s Degree in Architecture (B.Arch) from a recognized institution. Experience 8 12 years of professional experience in architectural design. Proven experience in managing design projects, especially high-rise residential and commercial developments. Technical Skills Proficiency in AutoCAD, Revit, SketchUp, and Microsoft Office tools. Deep understanding of building codes, regulations, and construction standards. Strong project management, coordination, and organizational skills. Soft Skills Excellent communication and presentation abilities. Strong problem-solving skills and high attention to detail. Collaborative mindset and ability to lead and work in cross-functional teams. Qualification : Bachelors Degree in Architecture (B.Arch) from a recognized institution

Electrical System Installation (ESI) Engineer Experience: 3 12 Years Location: Bangalore Role Overview: We are looking for an experienced Electrical System Installation Engineer / Technical Leader to support electrical harness design and installation projects, primarily in aerospace programs such as Airbus A320. This role requires managing design synchronization, modification processes, and ensuring compliance with Airbus design standards and processes. The candidate will work closely with cross-functional teams and design offices to deliver consistent, high-quality electrical system installations. Key Responsibilities: Coordinate and synchronize design activities with various design offices and project teams (e.g., DDMS projects) Manage the complete modification process from Change Request initiation to drawing delivery Establish and maintain design-related processes, methods, and tools to ensure full consistency and coherence Provide accurate and timely reporting to the Head of Project Support system installation design, follow-up, and validation checks Create and maintain drawing sets for Harness Design, Installation, VKE, Equipment Installation, Heater Installation, VU/VE Design Ensure compliance with Airbus installation rules and processes throughout the project lifecycle Qualifications: 3 to 12 years of hands-on experience in Electrical System Installation with strong DMU skills for harness modeling and installation analysis within A320/SA projects Good understanding of Airbus-specific tools and processes including Configuration Management, EHI Concept Design, Electrical Bracket Positioning, IP and UID proposals Experience in system installation design and support activities (design follow-up, installation checks) Knowledge of Functional Electrics (FE) including Configuration Management, Design, RDR & DQN instructions, and support on delivery checks is a plus Familiarity with Design Organization Approval (DOA) is advantageous Technical Skills: Expertise in Catia V5, VPM, PDMLink, PASS SSI / CCD, TAKSY, AIRINA, IPM4Legacy, and other Airbus customized tools Proficient in MS Office applications (Word, PowerPoint, Excel)

Position: Project Coordinator Design & Build Location: Bangalore Experience: 3 5 Years (Preferred background in Commercial Interior Fit-Outs Design & Build, IPCs, or General Contracting) Role Overview: We are seeking an organized and proactive Project Coordinator to support the execution of commercial interior fit-out projects. The ideal candidate will coordinate all aspects of project delivery including planning, scheduling, site management, and reporting ensuring timelines, quality, and budget expectations are met. Experience in a Design & Build or General Contracting environment is preferred. Key Responsibilities: Coordinate project activities, resources, equipment, and information across departments and stakeholders. Break down project requirements into actionable tasks and define clear timeframes. Monitor and supervise site operations to ensure timely and high-quality project execution. Maintain project quality standards by conducting quality assurance checks and enforcing compliance protocols. Prepare and manage site reports, tracking progress, issues, and risk mitigation steps. Utilize project management tools to monitor schedules, working hours, and expenditures. Oversee procurement activities and ensure timely delivery of project materials and equipment. Support project documentation, scheduling, vendor coordination, and client communication. Assist in risk analysis, quality control, and mitigation planning. Qualifications & Skills Required: Bachelor s degree in Engineering; Postgraduate degree in Construction Management preferred. 3 5 years of experience in project coordination, preferably in the commercial interior fit-out sector. Strong client-facing and team collaboration skills. Familiarity with project risk management and quality assurance practices. Ability to prepare and interpret schedules, flowcharts, and action plans. Proficient in project management tools (e.g., Microsoft Project, Excel, etc.). Excellent interpersonal and communication abilities. Strong organizational and vendor management skills. PMP certification is an added advantage. Qualification : Bachelors degree in Engineering; Postgraduate degree in Construction Management preferred.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

About NVIDIA NVIDIA has continually reinvented itself. From pioneering the GPU fueling the growth of the PC gaming industry and transforming modern computer graphics to revolutionizing parallel computing, we have consistently shaped the future of technology. Today, NVIDIA GPUs drive innovation in artificial intelligence (AI), providing highly scalable, parallel computation that powers groundbreaking advancements across industries. We are a company that thrives on learning, evolution, and tackling the world s most complex challenges. Join us, and you ll be part of a diverse, innovative, and supportive team that inspires everyone to achieve their best work. About the Role: SOC Design Engineer The System-On-Chip (SOC) group at NVIDIA is expanding! As the complexity of SOCs grows with chips now integrating tens of billions of transistors we are seeking a talented SOC Design Engineer with a passion for RTL integration and chip-level front-end design. This role focuses on padring design, pinmuxing, SOC assembly, and retiming. If you enjoy developing methodologies and automation solutions to optimize SOC creation, this is the opportunity for you. In this role, you will work on NVIDIA s advanced Tegra SOCs, collaborating closely with cross-functional teams, including System Architecture, Physical Design, CAD, and DFT. You will help define and implement scalable and efficient SOC design methodologies for future technologies. What You ll Be Doing Drive SOC assembly and design chip-level functions for Tegra SOCs. Perform front-end design quality checks, reviews, and collaborate with cross-functional teams to resolve issues. Oversee SOC execution across key milestones by defining, tracking, and managing complex dependencies with multiple stakeholders. Develop system-level methodologies, tools, and IPs to enable efficient and scalable SOC design. Identify and address inefficiencies in front-end chip implementation processes, implementing solutions for continuous improvement. What We Need to See B.Tech or M.Tech in Electronics Engineering or a related field. 2+ years of proven experience in chip design, with a focus on SOC integration and design automation. (Experience with padring design and fuse/floorsweep is a plus.) Strong analytical and problem-solving skills. Proficiency in RTL design (Verilog) and knowledge of SOC design/implementation flows. Experience with scripting languages such as Perl, Python, or other industry-standard tools. Exposure to multiple chip design functions, enabling collaboration and problem-solving across diverse teams. Excellent communication and collaboration skills with a team-oriented mindset. Bonus Skills: Experience in SOC verification, synthesis, physical design, and DFT. Familiarity with RTL build flows and Makefiles. At NVIDIA, you ll work on technologies that make a lasting global impact. We believe in fostering a diverse, inclusive work environment where everyone can grow and thrive. NVIDIA is proud to be an equal opportunity employer and does not discriminate based on race, religion, gender identity, age, disability status, or any other protected characteristic. Qualification : B.Tech or M.Tech in Electronics Engineering.