EDA Tool Development Jobs in Bengaluru

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Emulation Engineer Company Arm Location Bengaluru, India Job Overview Arm s Central Emulation team is excited to welcome experienced Emulation experts to join the team in Bengaluru. You will collaborate with design and verification engineers across the UK, US, India, and France to support advanced Compute Subsystems and SoC projects. Arm is building a team to develop exceptional silicon demonstrators based on Arm s IP compute sub-system solutions, targeting premium mobile, infrastructure, and automotive markets. Using the latest technology nodes (e.g., 3nm) and new 3D packaging innovations, Arm s goal is to demonstrate industry-leading performance by architecting, designing, implementing, and fabricating cutting-edge silicon test chips. This initiative brings together innovative talent and expertise from across the semiconductor industry to shape the next generation of compute on Arm devices. Responsibilities Collaborate with end users to understand system use cases and guide validation efforts. Ensure tight integration between hardware qualification and final application use models. Work in an exciting emulation environment using hybrid and virtual solutions, integrating industry-standard high/low-speed IO IPs into subsystems and SoCs. Engage from early architecture and design phases to pre-silicon validation and post-silicon validation on emulation platforms. Drive pre-silicon emulation across all SoC teams. Ensure design quality and debuggability by collaborating closely with the design team. Support architecture, verification, system validation, performance, power, and DFT teams with insights from performance and power characterization. Develop comprehensive pre and post-silicon test plans in collaboration with verification teams. Develop tests, create bare-metal drivers for industry-standard IO IPs, and build frameworks to enable scalable testing across multiple ASIC projects. Required Skills and Experience Bachelor s degree (BE/BTech) in Electronics Engineering. 8+ years of experience in Pre-Silicon Validation and Emulation/FPGA-based platforms. Experience developing C/C++/SystemC tests for HDL-HVL co-emulation platforms. Proficiency in IO bus protocols such as I2C, SPI, USB, and/or PCIe. Experience with SoC debugging tools such as JTAG and Trace32. Nice-to-Have Skills and Experience Knowledge of ASIC design and prototyping flows. Experience with SystemC/C/C++ and UVM/SystemVerilog (SV) verification languages. Familiarity with domains such as PCIe, Flash, Memory, CPU, GPU, and DRAM. Hands-on experience with emulation toolchains such as Zebu, Veloce, or Palladium. What Arm Offers Arm is committed to global talent acquisition, offering an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace where everyone can thrive, Arm encourages its people to make exceptional contributions to its global success. #LI-KR2 Qualification : Bachelors degree (BE/BTech) in Electronics Engineering.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

CPU Verification Engineer Company Arm Location Bengaluru Job Overview Responsibilities Contribute technically as part of project teams to deliver high-quality ARM CPU designs. Execute comprehensive CPU design verification, focusing on improving design quality through stress testing and bug identification. Effectively plan, conduct reviews, provide status updates, and meet delivery expectations. Collaborate with design and architecture teams to ensure effective coverage and provide accurate project planning inputs. Design and develop verification testbenches and components required for effective verification. Maintain knowledge of company processes to work effectively within defined standards and methodologies. Drive efficiency improvements in verification tools and methodologies and mentor team members to support career development. Required Skills and Experience 3+ years of experience in CPU, IP, or SoC product development environments. Experience in design verification/validation, including developing test plans, testbenches, and executing measurable verification processes. Familiarity with processor verification using assembly language and C/C++. Knowledge of microprocessor and/or SoC architecture and microarchitecture, preferably ARM processors and ARM-based systems. Strong problem-solving and debugging skills, with a commitment to continuous improvement. Nice-To-Have Skills and Experience Strong understanding of CPU architecture and microarchitecture. Experience with ARM-based system designs and hierarchical memory systems. Programming languages: Verilog, Assembly, C/C++, Perl, Python. Experience with verification languages such as SystemVerilog. Familiarity with power-aware verification methodologies. What Arm Offers This is a fantastic opportunity to shape the future of CPU verification at Arm while advancing your own career. Join our CPU design verification team and play a key role in delivering Arm's strategic goals! #LI-KR2

Job Overview: The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arm s future architecture roadmap. In ATG, we are developing world-leading Secure CPU and System architectures and associated technologies; enabling our ecosystem to build compelling products. Along with the architecture definition, ATG develops products to confirm compliance to the architecture. The ATG team located in Bangalore develops a product called Architecture Compliance Kits (ACK) that are delivered to multiple internal and external CPU design teams to validate that Arm architecture CPU implementations are compliant with the Arm architecture. You will learn Arm Architecture and apply it along with hardware and software verification skills to develop products for verifying the Architecture. You will develop good engineering and technical skills, and a fair understanding of CPU architecture and microarchitecture. You will connect with a wide range of teams within ATG, architects, and with our external partners. In this role, you will also develop solutions for future Arm architecture developments and influence the product offering. Responsibilities: Technical expertise, understanding architecture definitions, carrying out investigations and feasibility studies, defining and developing verification strategies, and contributing to the development of compliance products. Design verification test plans and test cases in assembly, C, HVL, and higher abstraction languages using automation techniques as needed. Strong and continuous communication on deliveries and risks, ensuring that all engineering commitments are delivered successfully. Drive efficiency improvements through adoption of the right development flows and methodologies. Excellent verbal and written communication skills. Required Skills and Experience: B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering. 8+ years of verification experience (CPU/complex IP verification is a plus). Strong understanding of computer architecture. Proficiency in logical programming using C/C++/Assembly with experience in adopting software engineering best practices. Nice To Have Skills and Experience: Experience in CPU verification would be a plus. Knowledge of x86 or Arm processor architecture. We are guided by our core beliefs that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and craft outstanding products and careers. In Return: We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to complex core implementation to full custom physical IPs, here you'll have our backing to push limits in vital areas. #LI-KR2 Qualification : B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

About the job At Google, data drives all of our decision-making. Quantitative Analysts work all across the organization to help shape Google's business and technical strategies by processing, analyzing and interpreting huge data sets. Using analytical excellence and statistical methods, you mine through data to identify opportunities for Google and our clients to operate more efficiently, from enhancing advertising efficacy to network infrastructure optimization to studying user behavior. As an analyst, you do more than just crunch the numbers. You work with Engineers, Product Managers, Sales Associates and Marketing teams to adjust Google's practices according to your findings. Identifying the problem is only half the job; you also figure out the solution. Responsibilities Interact cross-functionally with a variety of leaders and teams, and work with Engineers and Product Managers to identify opportunities for design and to assess improvements for advertising measurement products. Collaborate with teams to define questions about advertising effectiveness, incrementality assessment, the impact of privacy, user behavior, brand building, bidding etc., and develop and implement quantitative methods to answer those questions. Work with large, complex data sets. Solve difficult, non-routine analysis problems, applying advanced analytical methods as needed. Conduct analyses that include data gathering and requirements specification, exploratory data analysis (EDA), model development, and delivery of results to business partners and executives. Build and prototype analysis pipelines iteratively to provide insights at scale. Develop knowledge of Google data structures,metrics, advocating for changes where needed for product development. Minimum qualifications: Master's degree in Statistics or Economics, a related field, or equivalent practical experience. 8 years of work experience using analytics to solve product or business problems, coding (e.g., Python, R, SQL), querying databases or statistical analysis, or 6 years of work experience with a PhD degree. Experience with statistical data analysis such as linear models, multivariate analysis, causal inference, or sampling methods. Experience with statistical software (e.g., SQL, R, Python, MATLAB, pandas) and database languages along with Statistical Analysis, Modeling and Inference. Preferred qualifications: Experience translating analysis results into business recommendations. Experience understanding potential outcomes framework and with causal inference methods (e.g., split-testing, instrumental variables, difference-in-difference methods, fixed effects regression, panel data models, regression discontinuity, matching estimators). Experience selecting tools to solve data analysis issues. Experience articulating business questions and using data to find a solution. Knowledge of structural econometric methods. Qualification : Master's degree in Statistics or Economics, a related field, or equivalent practical experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Job Overview As a Tools Support & Infrastructure Engineer at Qualcomm, you'll play a vital role in supporting and enhancing the design flows and infrastructure for Qualcomm's Digital Signal Processing (DSP) team. The DSP design team delivers high-performance DSP cores that are integral to Qualcomm's multi-tier SoC roadmap, particularly for mobile applications. This position involves managing DSP design databases, developing automation tools to streamline the verification process, and collaborating with global teams to optimize design efficiency and quality. Key Responsibilities Manage DSP Design Database: Oversee the DSP design database, supporting design and verification teams with infrastructure needs. Build Automation: Create new automation tools to enhance the productivity of design verification teams, making it easier to debug simulation failures. Collaborate with Global Teams: Work with Qualcomm s global DSP design teams (architecture, implementation, post-silicon, and back-end teams) to enhance DSP IP infrastructure. Improve Tool Methodologies: Design and deploy new tool methodologies to continuously improve the quality, efficiency, and effectiveness of design and verification processes. Support Design Flows: Contribute to and improve design flows, ensuring the seamless integration of tools and resources used by design teams. Minimum Qualifications Educational Requirements: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 5+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant work experience. Skills & Experience Programming & Tools Support: 3-10 years of experience in programming, database management, and providing tools support for complex DSP IP designs. Automation Expertise: Extensive experience in building automation tools that improve design and verification processes. Programming Languages: Expertise in C++ and Java. Scripting & Automation: Proficiency with scripting languages and tools such as Perl, Python, Shell, Makefiles, and TCI. Analytical Skills: Strong analytic, programming, and debugging abilities. Object-Oriented Programming (OOP): Deep understanding of OOP concepts. Web Programming: Familiarity with Java for web programming is a plus. Unix Environment: Solid understanding of the Unix environment. Digital Design Flows: Knowledge of digital design flows is a plus. Communication: Excellent interpersonal and communication skills, with the ability to work collaboratively with global teams.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Minimum Qualifications: Bachelor s degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. At least 5 years of experience in software development, specifically within consumer electronics or embedded systems. A minimum of 3 years of experience in leading ASIC architecture decisions from a software perspective. Proficiency with Linux kernel, bootloaders, SoC, low-power management frameworks, or performance analysis. Preferred Qualifications: Master s degree or PhD in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or a related discipline. 10 years of experience in software design and development, particularly with software layers in ASIC (e.g., boot processes, drivers, embedded firmware, libraries, and APIs for applications). Familiarity with Android OS or similar platforms, especially in power management. Strong understanding of hardware-software interactions across various hardware blocks, including CPUs and accelerators. About the Role: Join a dynamic, diverse team that is pioneering the development of custom silicon solutions powering the future of Google's direct-to-consumer products. As part of the team, you will contribute to groundbreaking innovations in products used by millions globally, shaping the next generation of hardware experiences for optimal performance, efficiency, and integration. As the ASIC Platform Software Architect, you will be instrumental in translating software product requirements and use cases into specific hardware blocks or sub-systems. In this role, you will define the direction of the software team, guiding them in the face of complex constraints. You will work closely with hardware architects to define system architectures for hardware blocks and collaborate with the implementation team to outline solutions. You ll also help influence design decisions to ensure software requirements are met, negotiating hardware/software trade-offs for optimal results. Google's mission is to organize the world s information and make it universally accessible and useful. Our Devices & Services team integrates the best of Google AI, software, and hardware to create transformative user experiences. We focus on researching, designing, and developing new technologies and hardware to make user interaction with computing faster, more seamless, and more powerful. Whether we re innovating on form factors, advancing sensors, or redefining interaction methods, the Devices & Services team is dedicated to improving people's lives through technology. Responsibilities: Collaborate with stakeholders to identify user experience needs and map them to hardware and software solutions. Design architectures and software interfaces that empower developers to leverage hardware accelerators and other intellectual property (IP). Analyze hardware component interactions, troubleshoot issues, propose trade-off solutions, and drive to resolution. Contribute to the design and improvement of hardware from one generation to the next, applying insights from past productization efforts and reducing technical debt.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.