Gate Level Simulation Jobs in Bengaluru

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Lead Cloud Engineer HPC (High Performance Computing) Location: Bengaluru, India Company: Chevron Experience Level: 5 10 Years Department: IT Cloud Engineering Work Mode: Hybrid (Global Operations Support) About the Role Chevron is seeking a Lead Cloud Engineer HPC to deliver next-generation High Performance Computing (HPC) infrastructure and application solutions. This position plays a key role in supporting compute-intensive workloads such as geophysics, reservoir simulations, AI/ML models, and parallel file systems, with a focus on cloud-native solutions and low-latency architectures. This role is ideal for someone experienced in cloud engineering, Linux system administration, and HPC architecture. Key Responsibilities Design, deploy, and support HPC environments for compute-intensive workloads. Configure and manage HPC job scheduling systems (e.g., Slurm, PBS). Implement and maintain parallel file systems such as Lustre. Manage Azure-based cloud infrastructure using VM Scale Sets. Collaborate with data scientists and developers to optimize infrastructure. Leverage Ansible, Satellite, and Python for automation. Optimize low-latency networks for distributed computing. Modernize HPC architecture with an eye on cost control and performance. Required Qualifications Bachelor s degree in Computer Science, Information Systems, or related field. 5 10 years of experience in: Linux system administration in a large-scale environment Microsoft Azure, including VM Scale Sets HPC job schedulers Slurm, PBS Parallel file systems Lustre Automation tools Ansible, Satellite, Python Supporting compute-heavy scientific/engineering applications Understanding of storage systems, networking, and performance tuning in HPC. Willingness to support global operations and participate in after-hours support. Preferred Skills Experience deploying HPC workloads in hybrid cloud environments. Familiarity with reservoir simulation or geophysical applications. Knowledge of security compliance and cost optimization in HPC/cloud. Working Hours Chevron supports global operations. Work hours may be aligned across international teams: Standard Work Days: Monday to Friday Shift Options: 8:00 AM 5:00 PM or 1:30 PM 10:30 PM IST Benefits & Perks Competitive compensation package Health, life, and accident insurance Flexible work schedule and hybrid options Professional development and certification support Work on cutting-edge HPC and AI infrastructure Equal Opportunity Employer Chevron is committed to a diverse and inclusive workforce. All qualified applicants will receive consideration without regard to race, gender, religion, sexual orientation, nationality, age, or disability. Chevron participates in E-Verify in applicable regions. Apply Now If you re passionate about building scalable HPC infrastructure in the cloud, apply now to join Chevron s Cloud Engineering team in Bengaluru. Qualification : Bachelors degree in Computer Science, Information Systems, or related field.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience in micro architecture and requirements/implementation for automotive designs (focused on functional safety) and their Safety Analysis work products like concept FMEDA, DFA, DFMEA, FTA, FMEDA, etc. including FuSa compliant IP development and third-party IP compliance/deliverables/DIA. Responsibilities shall include the following: Developing a system level safety concepts and requirements for ADAS and IVI use cases with customer implementations in mind and to integrate Qualcomm s hardware in leading Automotive OEM and Tier 1 safety critical systems. Work in collaboration with 3rd party, Customer, and Automotive Stack suppliers, Hardware component suppliers (PMIC, DRAM, Sensor, etc) to ensure all aligned customer system level requirements are met Work with IP and SoC teams on the implementation of Technical Safety Concepts (TSCs) on Qualcomm s Snapdragon automotive hardware. Work with various technology teams on architectural features that would enable targeted safety levels (ASIL B to ASIL D, depending upon the technology team and system level requirements) to meet customer targets Conducting safety analyses, both quantitative and qualitative, fault campaigns on automotive hardware designs and identify areas of improvement. Responsibilities will include leading functional safety related activities for SoC development and ensure ISO 26262 compliance with respect to SoC architecture, development processes and work products. Work closely with SoC Design and IP teams, Software team, Quality teams, the functional safety manager(s) as well as customers to ensure the functional safety process is executed and documented. Working with vendors and partners to ensure functional safety requirements are fulfilled by the components that they provide Work with internal and external functional safety assessors to ensure compliance with ISO 26262 Create functional safety collateral for customers viz. Functional Safety Manual, Safety Analyses Reports, dedicated application notes etc. Supporting customer assessments of our safety features and recommending HW and SW based solutions that meet overall system targets. Working closely with customers and supporting them on various functional safety related aspects Minimum Qualifications Bachelor s degree in engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering, SoC Integration, Verification, or related work experience. Collaborative work experience with good communication skills involving customers, vendors, and internal development teams. Structured problem-solving capability and ability to work with teams on root cause analyses. Preferred Qualifications 5+ years Automotive experience and familiarity with Safety work products, experience with Functional Safety Hardware and/or Software development in semiconductor industry meeting IS0 26262/ IEC 61508 standards. Prior automotive experience in ADAS and self-driving systems preferred. System level Functional safety analysis experience on Hardware/Software components integration preferred SoC/IP integration or verification with good understanding of SoC Architecture and IP design experience preferred Requirements Management Tools and establishing traceability for functional safety requirements e.g. DOORS, etc. Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) is required experience using tools to perform FMEA, FTA preferred Familiarity with hardware failure rate calculation (FMEDA) experience using Siemens 29500 and/or IEC 62380 preferred Relevant Safety Certification is desired e.g. CFSE, CFSP Qualification : Bachelors degree in engineering, Information Systems, Computer Science, or related field.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Job Summary: (Sr. Lead Engineer) Qualcomm Simulation platform team would be responsible for defining/prototyping/developing software s on the emulation platforms. Looking for an experienced BSP engineer for virtual platform, who can help us is developing virtual prototype software solution for snapdragon automotive products. Candidate must have an excellent understanding of the complex SoCs architecture & its Software stack. Education & Experience: Bachelor s/master s degree in computer science, electronics engineering, or relevant domain with 6~8 years relevant industry experience. Primary Responsibility: Software (BSP) Bring-up on Virtual Platforms. Understand the emulation platform SoC architecture and develop single software solution. Ability to collaborate with cross functional teams and deliver the quality product under strict timeline. Define & develop custom virtio architectures. Pre-silicon software development platform prototype development Develop solution to improve performance of software running on Virtual platform. Supporting internal & external customers on Bring up & debugging from Software & emulation side. Mandatory Skills: Knowledge in Linux/QNX BSPs & Full Boot Chain. Strong System level programming skills in C/C++. Python, Rust is a plus. Excellent knowledge of OS fundamentals, Data structures, Linux kernel and its device driver model Strong debugging, analytical and problem-solving skills. Should have knowledge on debuggers like T32,gdb, etc., Strong collaboration skills with the ability to collaborate with multiple functional teams. Able to understand and debug large complex SW. Fair understanding of CPU (ARM), subsystems, SOC architecture and its SW-layers Fair understanding of the Virtual Machines with Type1 and Type2 Hypervisors Added Advantage: Fair understanding of QEMU/KVM platforms. Fair understanding of multimedia systems (GPU/Display/CAM/VPU/etc.,) knowledge. Fair knowledge of hardware-software interface and SystemC ASPICE and ISO26262 know how is preferred. Automotive experience is preferred. Qualification : Bachelors/masters degree in computer science, electronics engineering, or relevant domain with 6~8 years relevant industry experience.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Job Title: Pre-Silicon Validation Engineer SoC/IP Job Description: Join the Devices Development Group (DDG), one of Intel s premier System-on-Chip (SoC) design teams, driving innovation in future Intel SoCs and IPs. As a Pre-Silicon Validation Engineer, you will be part of a dynamic team responsible for ensuring the functionality, performance, and reliability of Intel s cutting-edge designs. Key Responsibilities: Validate IP blocks or features at the SoC level, ensuring compliance with design specifications. Develop validation plans and test strategies based on architectural specifications, RTL code, and existing test methodologies. Analyze microarchitecture and debug failures to identify root causes and improve design quality. Develop and utilize various debugging and validation tools to implement validation plans effectively. Participate in silicon debugging, identifying issues and enhancing testing methodologies for future RTL models. Collaborate with IP providers and internal customers to define, develop, and deliver essential infrastructure while addressing issues identified during execution. Qualifications & Requirements: Educational Qualifications: Bachelor s (B.Tech/BS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 5+ years of experience, OR Master s (M.Tech/MS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 3+ years of experience. Technical Skills & Experience: Minimum 2 years of experience in IP or SoC development, verification, or integration using SystemVerilog and UVM (Universal Verification Methodology). Minimum 2 years of experience in writing validation plans and developing software to execute those plans. Minimum 2 years of experience with object-oriented programming languages. Minimum 2 years of experience working with SystemVerilog and UVM. Minimum 1 year of experience with UNIX/Linux environments. Exposure to Graphics Verification and/or Security Verification is a plus. Preferred Qualifications: Minimum 1 year of experience with computer architecture. Minimum 2 years of experience in validation or testing, particularly in silicon design teams. About the Client Computing Group (CCG): The Client Computing Group (CCG) is at the forefront of Intel s PC product and platform development, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. Through strategic partnerships across the industry, CCG delivers innovative computing experiences that empower users to create, connect, and collaborate. As Intel s largest business unit, CCG drives innovation, scalability, and IP development, helping the company fulfill its mission of enriching lives through technology. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, which includes: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development opportunities to support career growth.

Job Description Intel is seeking an experienced Systems Engineer to drive the design, development, and integration of hardware, firmware, and software solutions for Xeon-based platforms. The role focuses on system architecture, performance optimization, and technical risk assessment while ensuring scalability, reliability, and security in system implementations. The ideal candidate will work on customer-centric solutions, influencing next-generation system design and conducting proof-of-concept experiments to validate new features and technologies. Key Responsibilities: System Architecture & Design: Define, develop, and optimize end-to-end solutions integrating software, firmware, board, and silicon/SoC components. Customer-Centric Solutions: Translate business opportunities into use cases, develop product specifications, and implement solutions based on customer needs and system limitations. Performance & Reliability Optimization: Conduct design analysis, assess technical risks, and optimize for security, scalability, and maintainability. Hardware Validation & Debug: Perform schematic reviews, layout verification, mechanical/thermal analysis, and electrical validation (including Signal Integrity (SI) analysis). System Integration: Ensure smooth hardware-software integration, identifying and resolving hardware issues at the component and system levels. Lab-Based Proof-of-Concept Testing: Conduct real-life environment simulations, prototype testing, and performance benchmarking. Documentation & Knowledge Sharing: Develop technical documents, customer presentations, and training materials to enhance internal and external knowledge sharing. Industry Research & Collaboration: Engage in academic and industry research, driving innovation beyond existing solutions. Qualifications & Experience: Educational Requirements: B.E/B.Tech in Electronics & Communication, Computer Science, or a related field. Minimum of 10 years of relevant industry experience. Technical Expertise: Experience in Xeon platform hardware design and validation. Strong knowledge of schematics, PCB layout, mechanical, and thermal analysis. Experience with electrical validation, signal integrity (SI), and power integrity (PI) analysis (desirable). Expertise in hardware issue validation, debugging, and system integration. Strong problem-solving and analytical skills for complex, multi-layered system architectures. Excellent technical documentation and presentation skills. About Intel Validation Engineering (iVE) Group: The Intel Validation Engineering (iVE) Group plays a pivotal role in Intel s technology leadership, validating, debugging, and optimizing Intel s cutting-edge designs. iVE ensures that Intel's next-generation products meet the highest quality standards, enabling Intel to deliver world-class technology platforms. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates, regardless of gender, nationality, disability, or other protected status. Intel offers a top-tier compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Health, retirement, and vacation benefits. Access to cutting-edge technology and career growth opportunities. Qualification : B.E/B.Tech in Electronics & Communication, Computer Science, or a related field.

Job Description Power the Future with us! SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 5000 employees, offices in 34 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. Our R&D division is growing globally, and we are looking for an experienced Power Electronics Engineer to join our dynamic team at the new R&D site in Bangalore, India. As a Power Electronics Engineer at SolarEdge India R&D, you will play a pivotal role in the design, development, and optimization of power electronics and power electronics systems for our advanced solar energy products. You will be responsible for driving the innovation and technical excellence of our power solutions, contributing to the success of SolarEdge's mission to make solar energy more accessible and efficient. Responsibilities: Design, analysis, and development of advanced power electronics and power systems for SolarEdge's solar energy products, including inverters, power optimizers, and energy storage solutions. Collaborate with cross-functional teams, including electrical engineers, Mechanical Engineers/Designers, PCB Layout Engineers, and firmware developers, to ensure seamless development, integration, and optimization of power systems. Conduct power system studies, such as load flow analysis, transient stability, and harmonic analysis, to assess system performance and reliability. Perform detailed design and analysis of power electronic circuits, ensuring compliance with industry standards and safety regulations. Prepare detailed design documentation, Schematics, BoM, and test procedures. Lead the testing and verification of power electronics and power systems, both in the lab and field, to ensure they meet design specifications and quality standards. Participate in design reviews, providing technical expertise and guidance to the team to drive continuous improvement and innovation. Collaborate with suppliers and manufacturing teams to support the transition of designs from R&D to mass production, addressing any design-related issues during production. Mentor and guide junior engineers, fostering a collaborative and innovative work environment. Job Requirements Bachelor s (B.E/B.Tech) or master s (M.E./M.Tech) degree in electrical /electronics Engineering with a specialization in Power Electronics or Power Systems. 4+ years of hands-on experience in power electronics design and power system analysis, preferably in the solar energy or renewable energy industry. Strong understanding of power semiconductor devices (Including SiC and GaN), gate drive circuits, and magnetic components used in power converters. Experience with simulation tools (e.g., PSpice, LT SPICE, Simulink etc.) Knowledge of power converter topologies (e.g., DC/DC, DC/AC and AC/DC), including resonant and bi-directional converters and grid-tied inverters. Excellent knowledge of PCB layout rules, considering high-current traces, thermal management, creepage, clearance requirements for HV and LV traces. Ensure compliance with best practices for power distribution, component placement, and impedance control. Implement EMI/EMC best design practices to ensure compliance with regulatory standards. Familiarity with international safety and regulatory standards for power electronics and solar energy products. Excellent problem-solving skills and the ability to troubleshoot and resolve complex technical issues. Strong communication and interpersonal skills to work effectively in a cross-functional team environment. Proven track record of delivering high-quality power electronics designs from concept to production. Results-oriented mindset with a focus on achieving tangible and measurable results. Qualification : Bachelors (B.E/B.Tech) or masters (M.E./M.Tech) degree in electrical /electronics Engineering with a specialization in Power Electronics or Power Systems.

About the Role: As a Senior Power Electronics Engineer at SolarEdge India R&D, you will play a crucial role in designing, developing, and optimizing power electronics and power systems for our cutting-edge solar energy products. You will be a key driver of innovation and technical excellence, contributing directly to SolarEdge's vision of accessible and efficient solar power. Key Responsibilities: Lead the design, analysis, and development of advanced power electronics and power systems for SolarEdge's solar energy products, including inverters, power optimizers, and energy storage solutions. Collaborate effectively with cross-functional teams (electrical, mechanical, PCB layout, and firmware engineers) to ensure seamless development, integration, and optimization of power systems. Conduct comprehensive power system studies (load flow analysis, transient stability, harmonic analysis) to evaluate system performance and reliability. Perform detailed design and analysis of power electronic circuits, ensuring adherence to industry standards and safety regulations. Create and maintain detailed design documentation, including schematics, Bills of Materials (BOMs), and test procedures. Lead the testing and verification of power electronics and power systems in both laboratory and field settings, ensuring they meet design specifications and quality standards. Actively participate in design reviews, providing technical expertise and guidance to the team to foster continuous improvement and innovation. Collaborate with suppliers and manufacturing teams to support the transition of designs from R&D to mass production, addressing any design-related challenges. Mentor and guide junior engineers, cultivating a collaborative and innovative work environment. Job Requirements: Bachelor's (B.E/B.Tech) or Master's (M.E./M.Tech) degree in Electrical/Electronics Engineering specializing in Power Electronics or Power Systems. 10+ years of hands-on experience in power electronics design and power system analysis, preferably within the solar or renewable energy industry. Strong understanding of power semiconductor devices (including SiC and GaN), gate drive circuits, and magnetic components used in power converters. Proficiency with simulation tools (e.g., PSpice, LTSpice, Simulink). Knowledge of power converter topologies (DC/DC, DC/AC, and AC/DC), including resonant and bi-directional converters and grid-tied inverters. Excellent understanding of PCB layout rules, considering high-current traces, thermal management, creepage, clearance requirements for HV and LV traces. Expertise in best practices for power distribution, component placement, and impedance control. Implementation of EMI/EMC best design practices to ensure compliance with regulatory standards. Familiarity with international safety and regulatory standards for power electronics and solar energy products. Exceptional problem-solving skills and the ability to troubleshoot and resolve complex technical issues. Excellent communication and interpersonal skills to collaborate effectively in a cross-functional team. Proven track record of delivering high-quality power electronics designs from concept to production. Results-oriented mindset with a focus on achieving tangible and measurable outcomes. Qualification : Bachelors (B.E/B.Tech) or masters (M.E./M.Tech) degree in electrical /electronics Engineering with a specialization in Power Electronics or Power Systems.

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Technical Requirements: 1. Experience in Verification: SoC (System on Chip), Sub-system, and Block Level verification. Strong understanding of verification methodologies and flow. 2. ARM Architecture & AMBA Protocol: Hands-on experience in ARM architecture. In-depth knowledge of AMBA protocol at the SoC and sub-system levels. 3. Verification Methodologies: Expertise in UVM (Universal Verification Methodology), OVM (Open Verification Methodology), SV (SystemVerilog), Verilog, and C-based verification methodology. Strong command over verification languages like SystemVerilog and Verilog. 4. Additional Verification Tools & Exposure: Exposure to GLS (Gate-Level Simulation) and power-aware verification is a plus. 5. Protocols Knowledge: Practical experience with verification of various protocols, such as: PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, SPI. 6. RTL Debugging & Test Automation Scripting: Strong RTL (Register Transfer Level) debugging skills. Ability to write test automation scripts using TCL, Perl, or Python. 7. Testbench (TB) and Test Cases: Experience in building testbenches (TB) and test cases from scratch. In-depth knowledge of creating scalable and reusable testbenches. 8. Verification Tools: Familiarity with industry-standard verification tools for simulation, debugging, and automation. Expectations from the Role: 1. Communication & Inter-personal Skills: Strong communication and inter-personal skills. Ability to work independently or as part of a team, collaborating effectively with cross-functional teams. 2. Learning & Adaptability: Ability to quickly learn new technologies and verification tools. Ability to work in a distributed work environment and adapt to diverse work conditions. 3. Ownership & Punctuality: Demonstrated ownership of tasks and projects. High punctuality and accountability in delivering results within agreed timelines.

Technical Requirements: 1. Verification Experience: Strong experience in SoC, sub-system, and block-level verification. Ability to handle different verification stages and methodologies for complex systems. 2. Hands-on Experience with ARM Architecture and AMBA Protocol: ARM architecture familiarity, particularly at the SoC and sub-system level. Expertise in AMBA protocol (e.g., AHB, APB, AXI) and its application in SoC verification. 3. Verification Methodologies: Proficient in UVM/OVM, SystemVerilog, Verilog, and C-based verification methodologies. Solid understanding of testbenches (TB), test cases, and automation methodologies. Experience in test automation scripting with languages such as TCL, Perl, and Python. 4. Exposure to Advanced Verification Techniques: GLS (Gate-Level Simulation) experience is a plus. Power-aware verification knowledge, ensuring low power consumption in designs. 5. Protocol Knowledge: Working knowledge of industry protocols such as PCIe, DDRx, Ethernet, USB, I2C, SPI, among others. Familiarity with AXI, AHB, APB protocols for data communication in embedded systems. 6. RTL Debugging & Tools Proficiency: Strong RTL debugging skills to identify and resolve issues in designs. Well-versed with industry-standard verification tools used in simulation, debugging, and analysis. 7. Building Testbenches & Test Cases: Extensive experience in building testbenches from scratch. Ability to create and implement detailed test cases for different verification scenarios. Expectations from the Role: 1. Communication and Interpersonal Skills: Strong ability to communicate technical concepts effectively both within the team and with other stakeholders. Clear verbal and written communication skills for reporting progress and challenges. 2. Independent and Team-based Work: Ability to work independently on projects or as part of a team. Able to take ownership of tasks and contribute to team discussions effectively. 3. Learning and Adaptability: Ability to learn quickly and adapt to evolving technologies and methodologies. Stay updated with advancements in verification techniques and tools. 4. Ownership and Accountability: Demonstrated ownership of projects, ensuring timely completion and addressing any challenges that arise. Ensuring high-quality results through attention to detail. 5. Leadership & Mentorship: Ability to mentor and lead junior engineers and verification teams. Provide guidance in solving complex problems and ensuring successful project outcomes. 6. Punctuality and Responsibility: Demonstrated punctuality in meeting deadlines and project milestones. Timely execution of tasks and troubleshooting to maintain project timelines. Ideal Candidate Profile: The ideal candidate will have significant experience with SoC verification, ARM architecture, and verification methodologies such as UVM and SystemVerilog. The candidate should possess strong protocol knowledge and be proficient in debugging RTL and automating test scenarios. A key aspect of the role is the ability to work independently, take ownership of tasks, and guide the team in solving technical challenges. Leadership and mentoring abilities are essential, as is the capacity to manage multiple tasks effectively in a distributed work environment.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs Participates in the definition of architecture and microarchitecture features of the block being designed Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features Supports SoC customers to ensure high quality integration and verification of the IP block Drives quality assurance compliance for smooth IP SoC handoff Qualifications Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components Knowledge of Power management is preferred. Experience with formal apps would be good. Expertise in Verilog and System Verilog-based logic design. Expertise in Verilog and System Verilog-based logic design Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must Knowledge of considerations for performance, power, and cost optimization is desirable. Knowledge of formal property verification using Jasper is preferred Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills Set aggressive goals and meet/beat the commitments Flexible enough to work in a dynamic environment and multitask seamlessly. Ability to work independently and in a team Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years Track record of 'first-pass success' in ASIC development cycles Hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle At least 9+ years of hands on experience Preferred Qualifications Experience in development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet Experience working across and building relationships with cross-functional design, model and emulation teams Qualification : Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience of at least 9+ years

JOB PURPOSE: Responsible for complete, timely and qualitative execution of Accounting Operations for R2R according to the defined activity split. Accountable for to the reliability of the financial statements in his/her scope of responsibility in accordance with BKA and BMA, considering the International Financial Reporting Standards (IFRS) and according to the country specific legislation and country specific tax compliant accounting treatment allowing a certification by external auditors. ROLES & RESPONSIBILITIES: Implement the best practice in relevant process and ensure SAP system design in line with group & Subgroup standards to meet the business steering requirement from local and global. Be and act as the owner of market and tasks within assigned team. Participate in expert communities through global calls and other media. Interact with key business functions (e.g. Controlling, Procurement, Product Supply, etc.) to ensure proper accounting for the particular areas of operation. Partner with the expert communities to ensure globally defined standards and activity splits, as well as liaise with the GBS network regarding R2R issues and to implement desired and necessary processes and changes. Interact with internal and external auditors ensuring prompt response to audit requests. Document appropriate ICS controls. Support local projects such as legal entity and system mergers, acquisitions or divestitures. And expectations of "accountant role" on top - to still deliver as well on the basic operational expectations with accountability. WHO YOU ARE: University degree preferable in Accounting, Finance, Tax, Economics, or relevant degree. Completion of Functional FATE academy and capability framework to appropriate level - foundation, Intermediate or Advanced as specified) strongly preferred for promotion to next level. Certified tax advisor or accounting certificate - beneficial. At least 2 years professional experience in Accounting, Controlling, Taxes, Financial Analysis, or similar fields. Fundamental understanding of global accounting, controlling and tax processes and their point of intersection with other business processes. Good level of knowledge of technical accounting, and financial reporting in a corporate environment according to IFRS and local GAAP. Experience in executing technical projects (processes, organization and people) - beneficial. Support optimization projects and continuous improvement initiatives in order to improve quality and efficiency. Contribute to achieve Service Levels of Accounting in collaboration with GBS. Intermediate in SAP FI / CO module, good overview of interfaces with other modules and advanced level of Microsoft Office applications, especially in Excel Basic knowledge about usage of Data Analytics, visualization tools and methodologies to manage Financial Data quality (data structures and hierarchies, interconnected) beneficial. Experience with Bayer s Financial Accounting IT enablers beneficial. (expected if internal) Added Advantages: foundation knowledge of Power Query, Tableau foundation knowledge of Power BI or similar tools for analytics and visualization (can create, share and publish dashboards/reports, can identify areas for implementation) foundation knowledge of Power Automate (can build basic solution or use templates, can identify potential areas of implementation) Qualification : University degree preferable in Accounting, Finance, Tax, Economics, or relevant degree.

Red Team Hacker / Pen Tester (Onsite, Bangalore) Who We Are ColorTokens We re on a mission to keep businesses running safe and sound even when cyber attackers try to mess things up. Our next-gen platform, ColorTokens Xshield , stops ransomware and malware from spreading sideways inside companies, so critical stuff stays locked down and working. We ve got mad skills in spotting and controlling traffic between all kinds of devices and users from your typical laptops to IoT and medical gadgets. That means we can slice and dice security zones to keep bad actors contained. Forrester calls us a Leader in Microsegmentation (Q3 2024), and we help global companies avoid big $$$ downtime. Our Vibe We re all about hustling with heart. You ll get to own your projects, work with smart teammates, and solve tough problems that actually protect people from kids in hospitals to entire cities. If you re driven, curious, and ready to make a real impact, you ll fit right in. The Gig What You ll Do Run epic red team ops that mimic real-world hackers trying to break in. Hack (ethically!) into networks, apps (web, mobile, APIs), and cloud setups to find weaknesses. Build your own scripts and tools to level up your tests and dodge detection. Team up with defenders (blue team) to boost how we spot and stop attacks. Write clear, no-fluff reports with proof-of-concept hacks and smart fixes. Keep your finger on the pulse of the latest threats and hacker tricks. Jump into purple teaming and adversary simulations to sharpen our edge. Bachelor s in Cybersecurity, CS, or you ve got real-world chops that match. 6+ years deep in red teaming, pentesting across web, APIs, infrastructure, and cloud. Pro with tools like Cobalt Strike, Metasploit, Nessus, Burp Suite, Nmap, and scripting (Python/PowerShell/Bash). Solid grasp of MITRE ATT&CK, threat modeling, and adversary emulation. Know Windows & Linux inside out, Active Directory, plus cloud platforms (AWS, Azure, GCP). Bonus points if you re into social engineering, phishing, or physical security. Skilled at writing docs that actually make sense. Must-have certifications: OSCP is a must; CRTP, OSCE, OSEP, CRTE, GPEN, GXPN are pluses. Qualification : Bachelor's degree in Cybersecurity, Computer Science, or related field (or equivalent experience).