Logic Design Engineer Jobs in Bengaluru

MTS - Software Developer (Cloud AI Network Security Developer) Location: Bengaluru Company: Aviatrix Experience: 1 3 years About Aviatrix: Aviatrix is a cloud network security leader trusted by over 500 enterprises. We specialize in securing multi-cloud environments, offering runtime protection and advanced control for modern cloud infrastructures. Role Strategy & Impact In this role, you will build next-generation intelligent cloud network security solutions. You will focus on developing Python/Go microservices that fuse network visibility with LLM-driven insights to redefine cloud firewall capabilities. Technical Requirements Core Competencies: Development: Professional experience in Go (Golang) or Python. Cloud Networking: Fundamentals of Routing, NAT, VPNs, and Subnets. Security: Understanding of Firewall concepts (ACLs) and Zero Trust architecture. AI Integration: Experience using AI/LLM APIs (OpenAI, Vertex AI, etc.). Data Infrastructure: Workflows involving Kafka, data ingestion, and stream processing. Cloud Ecosystem: Hands-on familiarity with AWS, Azure, or GCP. Preferred Qualifications: Network Observability: Experience with NetFlow, IPFIX, or VPC Flow Logs. Modern DevOps: Hands-on with Kubernetes, Container Networking, and Terraform. Generative AI: Knowledge of Prompt Engineering or RAG-based systems. Key Responsibilities Control Plane Development: Build services for firewall rules and policy orchestration. AI Workflows: Integrate LLM-based assistants for anomaly detection and alert summarization. Telemetry Pipelines: Maintain high-performance data pipelines for security event metrics. Security Logic: Design logic for threat pattern recognition and posture scoring. Benefits & Why Join Us Global Benefits: Private medical, pension, and life assurance. Work-Life Balance: Generous holiday allowance and annual wellbeing stipend. Growth Mindset: We value diverse paths if you are passionate about AI and Security, we want to hear from you.

Position: Control Design Lead Department: Automation Department Reporting To: Senior Manager - Automation Location: Bengaluru Key Responsibilities Project Involvement: Actively participate in the Preliminary Stage Meeting (PSM) to evaluate existing sites, equipment, components, processes, and collaborate with customer representatives alongside the Project Leader (PL). System Requirements: Work closely with the PL to understand mechanical and application system requirements and ensure they align with project objectives. Control System Design: Design complete electrical and control systems, including: Wiring diagrams Panel diagrams Flowcharts of operational sequences (CNC & PLC) Operating logic, I/O assignments, sequence of operation, error & exception conditions, and safety interlocks. Program Development: Develop CNC/Robot programs, HMI, and PLC ladder logic based on project needs. Design Documentation: Prepare DAP (Design Approval Package) drawings in accordance with the provided checklist. Ensure the creation of detailed Bill of Materials (BOM) and Critical Bought Out Material (CBOM) lists, adhering to target costs. Release panel and machine wiring diagrams for manufacturing. Generate and track micro-schedules and sub-milestones in design activities to meet timelines. Design Review & Compliance: Review designs individually or with a competent team for correctness, completeness, and suitability, ensuring compliance with application-specific checklists. Proactive Project Support: Provide support during the build, testing, and trials. Address design modifications and handle User Requirement Change Requests (UCR), System Change Requests (SCR), and Engineering Change Requests (ECR). Documentation and Manuals: Develop panel layouts, field wiring diagrams, and basic user manuals (including startup/shutdown sequences, diagnostics, and programmed cycles). Collaboration: Work closely with assembly and design engineers to guide and support throughout the design and manufacturing phases. Skills and Expertise PLC Programming: Expertise in PLC code development with experience in multi-PLC systems (e.g., AB, Siemens, Mitsubishi, etc.). Motion Control Systems: Experience with motion control and CNC Gantry GCode software development. User Interface Development: Ability to design and develop user interfaces for operational ease. System Design: Proficiency in flowchart creation and application development. Professional Expertise: Experience in control systems including CNC, PLC, robotics, drives, servo systems, HMI, IoT, etc. Qualifications Essential: Bachelor s degree or Diploma in Electrical, Mechatronics, Instrumentation, or related fields. Experience: 6-10 years total professional experience. 3-6 years of relevant experience in control system design, automation, or related fields. Qualification : Bachelors degree or Diploma in Electrical, Mechatronics, Instrumentation, or related fields

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Principal Scientist Business Unit: DALP Location: Bangalore About Adobe Adobe leads the digital experience revolution, empowering creators and global brands with innovative tools to design, deliver, and transform how companies interact with customers across every screen. Recognized for 20 consecutive years on Fortune s 100 Best Companies to Work For, Adobe fosters an inclusive, collaborative, and growth-driven culture where new ideas thrive. Role Summary As Principal Scientist for Adobe Learning Manager (ALM), you will spearhead the architecture and delivery of a next-generation, AI-powered eLearning platform supporting tens of millions of learners globally with 40% YoY growth. Your mission is to design scalable, resilient, and ACID-compliant systems that handle unpredictable workloads while enabling hyper-personalized learning experiences through generative AI. Key Responsibilities Lead the technical vision, design, and roadmap for ALM s scalable SaaS platform. Deliver high-performance web services tailored to evolving business needs with a strong focus on scalability, security, and stability. Develop and refine engineering and business processes to enhance team productivity and product quality. Architect solutions that elegantly split complex workflows between data lakes and business logic layers. Mentor and guide junior engineers, fostering innovation and technical excellence. Stay ahead of industry trends and integrate cutting-edge technologies to maintain Adobe s competitive edge. Lead customer-centric initiatives and collaborate closely with cross-functional teams to deliver impactful solutions. What You Need to Succeed Bachelor s degree in Computer Science or Software Engineering. 15+ years of experience building and maintaining highly available, scalable SaaS services, with at least 4 years as a Lead or Chief Architect. Expert proficiency in Java, Spring framework, Tomcat, AWS Cloud, and relational databases like MySQL. Strong problem-solving skills coupled with excellent verbal and written communication abilities. Passion for solving complex customer challenges and pioneering new technological and UX frontiers. Ability to thrive amid ambiguity and shifting priorities while leading technical and non-technical stakeholders. Join a global leader driving innovation in digital experiences and eLearning. At Adobe, you ll influence the future of learning technology, work alongside passionate experts, and be part of a culture that values creativity, diversity, and continuous growth. Qualification : Bachelors degree in Computer Science or Software Engineering.

Job Title: Backend Developer - Python | 4-5 Years Experience | FastAPI, Flask, MySQL | Bangalore, India Location: Bangalore, Karnataka, India Job Overview: We are seeking a skilled Backend Developer with 4 to 5 years of experience in designing and building scalable backend services and APIs using Python. You will work with modern frameworks like FastAPI and Flask, integrate relational databases, and deploy applications in containerized environments. Collaboration with DevOps and frontend teams is key to ensuring seamless feature delivery and backend reliability. Key Responsibilities: Design and develop robust, scalable RESTful backend APIs using FastAPI and Flask Build efficient server-side logic and core business functionalities using Python Design, integrate, and optimize MySQL and PostgreSQL databases for backend applications Deploy and manage applications in Docker and Kubernetes environments to ensure high availability and scalability Maintain and enhance CI/CD pipelines using tools like Git and Jenkins Collaborate closely with DevOps and frontend teams for smooth integration and deployment Ensure high code quality by conducting peer reviews, writing clear documentation, and following best practices Technical Skills: Strong proficiency in Python with hands-on experience in FastAPI and Flask Expertise in building and consuming RESTful APIs Experience with relational databases: MySQL and PostgreSQL Containerization skills using Docker and orchestration with Kubernetes Version control with Git and CI/CD pipeline management using Jenkins Comfortable working in a Linux-based development environment Education & Qualifications: Bachelor s or Master s degree in Computer Science, Engineering, or a related field Desirable Skills: Advanced experience with Docker and Kubernetes for container orchestration Open Positions: 2 Work on scalable backend systems supporting innovative FinTech and other industry projects Collaborate with a skilled team across DevOps, frontend, and backend domains Grow your expertise with cutting-edge technologies and containerized deployments in a dynamic work environment Qualification : Bachelors or Masters degree in Computer Science, Engineering, or a related field

Electrical Principal Engineer FPGA Team Location: Bengaluru, India Team: Electrical Engineering Company: Dell Technologies Role Overview As a Principal Electrical Engineer, you will contribute to the architecture, design, and validation of FPGA-based hardware systems for Dell s next-generation enterprise servers. This role involves working across global teams to deliver robust, scalable, and efficient PCBA (Printed Circuit Board Assembly) and logic solutions that align with industry standards and internal requirements. Key Responsibilities Architect and design next-gen hardware features in collaboration with front-end teams and partners. Analyze and recommend trade-offs in design features and costs. Guide global teams with best practices in electronic hardware design. Own and deliver system interfaces and support cross-functional development efforts. Create comprehensive documentation for testing and validation. Essential Requirements 8 12 years of experience in FPGA hardware verification using Verilog, SystemVerilog, VHDL. Expertise in UVM, ABV (Assertion-Based Verification), code coverage, and unit-level simulation. Knowledge in digital design methodologies: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Static timing analysis Experience with x86 or ARM architectures. Familiarity with peripheral protocols: I2C, I3C, SMBus, IPMI, IPMB. Strong background in both analog and digital design. Understanding of hardware/software co-design and debugging complex systems. Desirable Qualifications Experience with Intel/AMD x86 and ARM-based systems. Hands-on with FPGA tools: Xilinx, Lattice, Altera Quartus, ModelSim/QuestaSim. Passion for mentoring and knowledge sharing. Dell Technologies offers a collaborative and innovative environment where hardware engineers work at the forefront of industry advancements. You'll be empowered to lead cutting-edge hardware projects, influence product design, and make a lasting impact on the future of enterprise technology.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Job Title: Senior Cloud Development Engineer Location: Bengaluru, Karnataka, India About Us: Cloud Software Group combines the capabilities of both Citrix and TIBCO, creating one of the world's largest cloud software providers, serving over 100 million users globally. By joining Cloud Software Group, you will make a significant impact, helping real people access the cloud-based products they rely on to get their work done from anywhere. Our team values passion for technology, the courage to take risks, and the empowerment of every individual to dream, learn, and build the future of work. This is an exciting time to bring your skills to the cloud and be a part of our evolving journey! About This Team: We are seeking a Senior Cloud Development Engineer to join our dynamic DaaS (Desktop as a Service) team. In this role, you'll work with cutting-edge cloud technologies to develop and maintain scalable, secure cloud services. You will be a key contributor to the Citrix DaaS Product Line, working alongside a talented team of engineers to build resilient microservices that power our customer-facing applications. Your work will directly influence the experience of customers and partners globally. Job Description: As a Senior Cloud Development Engineer, you will be responsible for: Back-End Development: Improve business logic, enhance existing features, and build new ones to support the Citrix DaaS product line. Collaboration: Work cross-functionally with teams to define, design, and ship new features that enhance the DaaS experience. Continuous Improvement: Research and evaluate new technologies to maximize development efficiency, with a focus on adopting Generative AI tools where applicable. Agile Methodology: Embrace agile practices such as Jira, SCRUM, SAFE, or Kanban to deliver high-quality products on time. Best Practices: Institute coding standards, including code reviews, integration testing, unit testing, logging, and instrumentation to ensure the robustness of the codebase. Troubleshooting: Understand and resolve field issues, performing root cause analysis and implementing preventive measures to improve performance and security in cloud environments. Required Experience/Skills: Bachelor's Degree (BE/BTech) in a technical field or equivalent work experience. 4+ years of relevant work experience in cloud development or software engineering. Strong understanding of computer science fundamentals, particularly algorithms and data structures. Excellent communication and collaboration skills to effectively discuss technical concepts with cross-functional teams. Strong problem-solving and troubleshooting abilities, with an emphasis on resolving performance and security issues in cloud environments. Preferred Qualifications: Development experience with .NET technologies such as C#. Scripting experience with languages such as Python or PowerShell. Familiarity with cloud computing technologies, including platforms like Microsoft Azure or Amazon EC2. Experience with Sumo Logic or Splunk for troubleshooting and monitoring in cloud environments. At Cloud Software Group, you're not just joining a company; you're becoming part of a team that values your contributions and encourages you to innovate. This is your chance to be a part of one of the largest cloud solution providers, working on cutting-edge technologies that impact millions of users globally. You ll have the opportunity to work in a fast-paced, collaborative environment where your skills are valued and developed. Equal Opportunity Employer: Cloud Software Group is firmly committed to Equal Employment Opportunity (EEO) and to compliance with all federal, state, and local laws that prohibit employment discrimination. All qualified applicants will receive consideration for employment without regard to age, race, color, sex, gender identity, sexual orientation, ethnicity, national origin, citizenship, religion, genetic carrier status, disability, pregnancy, childbirth, or any other protected classification. Qualification : Bachelor's Degree (BE/BTech) in a technical field or equivalent work experience.

Job Title: Principal Cloud Development Engineer Location: Bengaluru, India About Cloud Software Group: Cloud Software Group (CSG), home to Citrix and TIBCO, is one of the largest global providers of cloud-based technologies, empowering over 100 million users worldwide. As a Principal Cloud Development Engineer, you will play a pivotal role in shaping the future of Desktop-as-a-Service (DaaS) solutions helping deliver secure, scalable, and intelligent platforms that drive modern work experiences from anywhere. We re entering an era of accelerated innovation and transformation now is the perfect time to bring your technical leadership, cloud expertise, and mentorship mindset to the forefront. About This Team: The DaaS team at CSG is responsible for designing and building scalable and resilient cloud-native microservices that power Citrix s core virtualization offerings. This team collaborates across product, architecture, operations, and customer success groups to build next-gen capabilities on Azure, AWS, and other hybrid environments. Your Role and Responsibilities: As a Principal Cloud Development Engineer, you will be expected to: Lead design and architecture discussions for cloud-native solutions within the Citrix DaaS product line. Drive the development of scalable and secure backend features, with emphasis on business logic, cloud security, and performance. Mentor junior and senior engineers, guiding them in coding best practices, design decisions, and technical growth. Collaborate with Product Managers, UX Designers, Support, and Site Reliability Engineers to build customer-centric features and maintain high service uptime. Contribute to strategic technical initiatives, including the adoption of Gen AI tools, DevSecOps automation, and performance tuning of production systems. Participate in on-call escalation support, helping debug complex issues and lead incident resolution. Promote a culture of continuous learning and improvement through code reviews, technical sessions, and post-incident analysis. Required Experience and Skills: 14+ years of experience in cloud software development using .NET (C#), Java, or equivalent Object-Oriented Programming languages. Strong computer science fundamentals (algorithms, data structures, systems design). Proven track record in building and leading cloud-native microservices with modern deployment practices (CI/CD, IaC, Kubernetes, Docker). Strong cloud platform expertise, especially in Microsoft Azure or Amazon EC2. Deep understanding of cloud security, including identity/access management, encryption, compliance, and incident response. Advanced knowledge in automation scripting (Python, PowerShell). Familiarity with troubleshooting tools like Sumo Logic, Splunk, or equivalent observability platforms. Experience with Terraform, CI/CD pipelines, and managing Kubernetes-based deployments. Strong communication, collaboration, and mentoring abilities. Preferred Qualifications: Prior experience building secure services in the DaaS, VDI, or enterprise SaaS domain. Hands-on experience with Azure Active Directory, Microsoft AD, or other identity solutions. Moderate understanding of cryptographic protocols and encryption standards. Familiarity with Agile/SAFe development methodologies. Contributions to open-source or technical publications are a plus. Impact: Influence the architecture and direction of mission-critical cloud platforms used globally. Mentorship: Be a technical leader shaping the next generation of engineers. Innovation: Work with a company at the edge of a "Cambrian leap" in cloud evolution. Culture: Inclusive, forward-thinking, and driven by curiosity and collaboration. Flexibility & Benefits: Competitive salary, performance bonus, flexible work model, health insurance, wellness programs, and more. Equal Opportunity Statement: Cloud Software Group is committed to Equal Employment Opportunity and prohibits unlawful discrimination of any kind. All qualified applicants will receive consideration without regard to race, color, religion, gender, gender identity or expression, national origin, age, disability, veteran status, or any other characteristic protected by law.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Requirements: BE/BTech degree in CS/EE with 8+ years experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus. Qualification : BE/BTech degree in CS/EE

Software Engineer Power/Thermal Software Products Team Company Qualcomm India Private Limited Job Area Engineering Group > Software Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world-class products that meet and exceed customer needs. You will collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master s degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Languages such as C, C++, Java, Python, etc. Job Description Job Overview: The Power/Thermal Software Products Team at Qualcomm focuses on delivering industry-leading power, thermal, and limit software management solutions across Qualcomm s Mobile, Automotive, Compute, IoT, and AR/VR chipsets. In this role, you will work with cross-functional teams to: Identify power optimization and performance tuning opportunities. Perform thermal/limits hardware tuning, characterization, and risk assessment. Develop optimized solutions and mitigation strategies. Conduct system-level analysis of power/thermal use cases. Collaborate with Architecture, Hardware Design, Performance, Power/Thermal Systems, and various Software teams to create optimal system-level power/thermal software solutions. Develop tools and methodologies for competitive analysis to understand competitors strengths and weaknesses. Design and implement thermal mitigation schemes that are best in the industry. Preferred Qualifications 3+ years of experience with Programming Languages such as C, C++, Java, Python, etc. Strong systems/hardware background with a solid understanding of microprocessor architecture and common SoC hardware blocks (interconnects, display, graphics, etc.). Good understanding of operating system concepts including scheduling, memory management, process management, interrupt handling, and device drivers. Experience using debug tools such as JTAG debuggers, oscilloscopes, and logic analyzers. Experience developing power/thermal management software. In-depth knowledge of embedded systems, microcontrollers, SoC power, modems, multimedia, wireless communications, and system-level debugging/analysis for SoC power optimization. Equal Opportunity Employer Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may email [email protected] or call Qualcomm s toll-free number found on their website. Upon request, reasonable accommodations will be provided to support individuals with disabilities during the hiring process. Qualcomm is also committed to ensuring its workplace is accessible to individuals with disabilities. (Please note that this email address is exclusively for accommodation requests. Qualcomm will not respond to requests for application status updates or resume inquiries via this email.) Recruitment Policy Qualcomm s Careers Site is only for individuals seeking employment directly with Qualcomm. Staffing and recruiting agencies, as well as candidates represented by agencies, are not authorized to use this site to submit profiles, applications, or resumes. Any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies and is not responsible for any associated fees. Compliance Notice Qualcomm employees are expected to comply with all applicable policies and procedures, including but not limited to security requirements and protection of company confidential and proprietary information, in line with applicable laws. Qualification : Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

Role Overview: We are seeking a Mediation Software Engineer with expertise in Mediation Zone, Oracle DB, and strong Linux and SQL skills. The ideal candidate will have experience designing mediation workflows, developing low-level designs, and working with telecom billing systems and network feeds. Skills Required: Mediation Product: Proficiency in Mediation Zone with knowledge of offline and online mediation processes. Database Knowledge: Experience with Oracle DB. Proficiency in APL/UFDL, Linux, and SQL, with the ability to design templates and patterns. Telecom experience, including familiarity with billing systems and network feeds, is preferable. Roles & Responsibilities: Attend workshops with IT teams to gather and analyze development requirements. Develop low-level designs, update design templates, and maintain operational documentation for mediation services. Design mediation workflows, adhering to standards and defining business logic and data validation rules. Conduct design review walk-throughs with stakeholders. Act as the primary point of contact for the development team on mediation services. Support the testing team by resolving design-related queries, reviewing test plans, and validating test results during various testing phases (UAT, FAT). Create acceptance criteria as part of the requirements documentation to guide developers and testers in creating test cases and validating outputs against business requirements.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.