LOW Level Optimization Jobs in Bengaluru

Gen AI Support Engineer-2 Location: Bengaluru Experience: 4 7+ years Employment Type: Full-time About Us Exotel is the leading full-stack customer engagement platform and virtual telecom operator for emerging markets. Since its inception in 2011, Exotel has been powering 50 million daily engagements across voice, video, and messaging channels. We provide our unified customer engagement solutions to over 6000 companies globally, including industry leaders like Ola, Swiggy, Flipkart, GoJek, Byjus, Urban Company, HDFC Bank, Zomato, and Oyo. With $100 million in Series D funding and an ARR of $60 million, Exotel is a growth-stage company poised for massive impact. Overview We're seeking a Gen AI Support Engineer-2 to join our team. As an L2 Support Engineer, you will be the highest level of technical escalation within the support organization. Your role will encompass system reliability, platform integrity, troubleshooting mission-critical production issues, and collaborating with engineering teams for architecture feedback. Additionally, you'll help mentor junior engineers and improve operational processes and tools for large-scale environments. If you're passionate about writing clean code with Python and Django and want to contribute to a fast-paced, mission-driven company, this role is for you! Responsibilities Mission-Critical Issue Resolution: Own the resolution of high-priority, time-sensitive production issues. Root Cause Analysis (RCA): Lead RCA reviews and push for systemic improvements in system architecture and processes. Performance Optimization: Identify bottlenecks and propose architectural changes to improve system performance and scalability. Patch Management: Assist in configuring, deploying, and testing patches, releases, and application updates to production environments. SME for Production Systems: Serve as the Subject Matter Expert (SME) for Exotel's production systems and integrations. Cross-Team Collaboration: Work with Delivery, Product, and Engineering teams to influence system design, rollout strategies, and improvement plans. Mentorship: Lead and mentor L1/L2 engineers on troubleshooting best practices and continuous learning. Code Writing & Automation: Write clean, maintainable code for internal tools, scripts, and automation using Python and Django. Support Tooling: Automate recovery workflows and design support tools for proactive monitoring. Operational Excellence: Establish and improve SLAs, monitoring dashboards, alerting systems, and operational runbooks to ensure system reliability. Must Have Skills Backend Development Support: 3+ years of experience in backend development support, production support, or DevOps/SRE roles. Core Technologies: Proficiency in Python, Django, SQL, and troubleshooting in Linux. Web Technologies: Strong understanding of HTML, CSS, JavaScript, and other web technologies. Distributed Systems & Cloud: Experience working with distributed systems, cloud architecture (AWS), Docker, and Kubernetes. Automation: Strong scripting skills with Bash/Python for automation and operational support. CI/CD & Observability: Good understanding of CI/CD, observability tools, and release management workflows. Communication Skills: Excellent communication, leadership, and incident command skills for managing production issues and cross-functional collaboration. Nice to Have Experience with AI-powered systems and machine learning technologies. Familiarity with monitoring systems like Prometheus, Grafana, or Elasticsearch. Knowledge of microservices architectures and scaling distributed systems. Innovative Work: Be at the forefront of cloud-based communications technology and AI-driven customer engagement platforms. Impact: Play a key role in maintaining and optimizing systems that power millions of customer interactions daily. Growth Opportunities: Be part of a fast-growing company with ample learning opportunities and career development. Collaborative Environment: Work in a supportive, inclusive environment where your input and ideas matter. Competitive Benefits: Comprehensive benefits package including health insurance, mental wellness support, and more.

Position: Catalog Head Location: Bengaluru Company: Ace Turtle Employment Type: Full-Time About Ace Turtle: Ace Turtle is India s leading tech-native retail company, driving the next phase of transformation in the retail industry. Vertically integrated from design to local manufacturing, marketing, and direct consumer engagement, Ace Turtle leverages proprietary technology and data science to meet the ever-evolving needs of today s consumer. Based in Bengaluru and Singapore, Ace Turtle is the exclusive licensee for iconic global brands such as Lee , Wrangler , Toys R Us , Babies R Us , and Dockers in India and South Asia. Role Overview: As the Catalog Head at Ace Turtle, you will oversee the development, organization, and management of our product catalog, ensuring it aligns with business goals and customer needs. You will work closely with cross-functional teams to maintain an accurate, up-to-date, and engaging catalog that drives sales and enhances the online shopping experience. Key Responsibilities: 1. Catalog Development & Management: Collaborate with product managers, marketing teams, and suppliers to gather comprehensive product data, including specifications, images, and pricing, to build an accurate and dynamic catalog. Regularly update and maintain the catalog, adding new products, removing discontinued items, and ensuring all details such as prices and stock availability are accurate. Ensure the catalog reflects the company s brand identity and product offerings effectively. 2. Data Management & Quality Control: Organize and manage product data, ensuring consistency, accuracy, and integrity across all entries. Handle categorization, tagging, and product attributes, applying best practices in product taxonomy and merchandising techniques. Conduct regular audits to identify and resolve any data discrepancies, ensuring seamless catalog updates. 3. Content Creation & Optimization: Write clear, persuasive, and SEO-optimized product descriptions that highlight key features, benefits, and unique selling points. Optimize product titles, meta tags, and other catalog content elements to enhance search engine visibility and drive conversions. 4. Catalog Presentation & User Experience: Collaborate with design and creative teams to present the catalog in an attractive, intuitive, and user-friendly format. Focus on improving catalog layout, navigation, and visual elements to enhance user experience and drive product discovery. Work with UX/UI teams to ensure an easy and seamless shopping experience, including effective filtering, sorting, and search functionalities. 5. Cross-Functional Collaboration: Partner with internal teams (marketing, sales, e-commerce, procurement) to align catalog strategies with broader business objectives. Collaborate with suppliers and vendors to ensure accurate product listings and timely updates. 6. Performance Analysis & Continuous Improvement: Monitor key performance metrics such as conversion rates, click-through rates, and customer feedback to gauge catalog performance. Use data-driven insights to optimize the catalog s effectiveness and drive improvements in user experience and sales. 7. Project Management: Manage multiple catalog-related projects concurrently, prioritize tasks, and meet deadlines in a fast-paced eCommerce environment. Coordinate with stakeholders to ensure timely execution of catalog updates and improvements. What We re Looking For: Experience: 8+ years of relevant experience in catalog management, product data management, or eCommerce merchandising. eCommerce Expertise: Strong understanding of eCommerce platforms, online retail best practices, and industry trends. Data Management: Proficiency in managing product data in eCommerce platforms or Product Information Management (PIM) systems. Ability to use data analytics tools. Attention to Detail: High level of accuracy in managing product data, ensuring consistency and quality control across the catalog. Communication Skills: Excellent written and verbal communication skills, with the ability to create compelling product descriptions. Analytical Abilities: Strong analytical and problem-solving skills, with the ability to identify opportunities for catalog optimization based on data insights. Technical Proficiency: Familiarity with eCommerce platforms, CMS tools, and digital marketing tools. Basic knowledge of HTML, CSS, or other web development languages is a plus. Project Management: Strong organizational and multitasking skills to manage projects efficiently. Innovative Environment: Be part of a leading tech-native retail company shaping the future of the industry. Growth Opportunities: Work with iconic global brands and contribute to a high-impact, fast-growing business. Collaborative Culture: Join a dynamic, cross-functional team focused on driving results and continuous improvement. Global Reach: Play a pivotal role in managing the product catalog for an internationally recognized portfolio of brands.

Job Title: Lead Associate Software Engineering (Database Developer) Location: Bengaluru Type: Full-Time Level: Senior Database Developer About BetaNXT BetaNXT is shaping the future of connected wealth management infrastructure, delivering real-time data capabilities that improve advisor productivity, reduce operational costs, and enhance the investor experience. Leveraging the combined power of Beta, Maxit, and Mediant, our solutions tackle complex integration challenges and modernize platforms for scalability, agility, and growth. We help wealth management firms turn legacy platforms into differentiating assets. About the Role We are looking for a Senior Database Developer to join our Product Engineering team as a Lead Associate Software Engineering. In this role, you will play a critical part in designing, developing, and optimizing enterprise-grade database solutions to support our next-generation wealth management platform. This position is ideal for a detail-oriented and performance-focused database professional who thrives in a collaborative Agile environment and is passionate about building scalable, reliable data systems. Key Responsibilities Design, develop, and maintain complex SQL queries, stored procedures, triggers, and database scripts. Analyze and optimize database performance, ensuring scalability and efficiency. Develop and maintain SSRS reports, support ETL processes, and collaborate on SSIS packages. Work closely with application developers to ensure seamless database integration and data flow. Perform in-depth data analysis to support business and product requirements. Partner with QA teams to validate data integrity and support testing cycles. Conduct unit testing and developer-level validation to ensure quality before release. Participate in daily Scrum meetings and Agile ceremonies to coordinate development efforts. Troubleshoot and resolve complex technical issues related to data and performance. Document all development work to support maintainability and knowledge sharing. Required Qualifications & Experience Experience: 7+ years of hands-on experience in SQL database development in enterprise environments. Technical Skills: Advanced SQL development skills, including writing and optimizing complex queries and stored procedures. Proficiency in T-SQL (preferred), with acceptable expertise in PL/SQL or equivalent SQL dialects. Experience with SSRS (SQL Server Reporting Services), SSIS, and ETL processes. Strong data modeling, data analysis, and database design capabilities. Hands-on experience in performance tuning and query optimization techniques. Working knowledge of AWS services such as S3, SSM, and DynamoDB is a plus. Soft Skills & Collaboration Strong problem-solving and analytical thinking skills. Excellent verbal and written communication skills. Ability to work collaboratively across cross-functional Agile teams. Highly organized, detail-oriented, and self-motivated. Contribute to a platform backed by industry innovation and 11 technology patents. Help shape the future of real-time data and wealth management systems at scale. Collaborate with a high-impact, global engineering team in a dynamic, fast-paced environment. Thrive in a company culture that values growth, curiosity, and collaboration.

Position: Manager FMRTS CT Location: Bengaluru Experience Required: 5 10 years Department: Operations About the Role: We are seeking a highly analytical and results-driven Manager FMRTS CT to lead key operational excellence initiatives across sort centers in the West region. This role focuses on improving throughput, optimizing workflows, and ensuring process adherence across the end-to-end supply chain. The ideal candidate should possess strong cross-functional leadership, data-driven decision-making, and project management skills. Key Responsibilities: Increase core Throughput Per Hour (TPH) in sort centers through layout standardization and implementation of Zone-Based Palletization (ZBP). Develop and apply mathematical models to optimize load balancing across belts, reducing defects and improving productivity. Own and drive compliance programs such as signage standardization, WIKI documentation, Guard Shack (GS) protocols, and Grace Time Truck Departure (GTTD). Analyze and improve sort center quality metrics; conduct deep dives for underperforming sites and collaborate with cross-functional teams (Operations, Linehaul, Analytics, Safety & Loss Prevention) to meet performance targets. Build and maintain a sortation path planning tool to ensure Long-Term Planning (LTP) is adhered to at the site level. Conduct Time & Motion studies to identify and eliminate non-value-adding activities, improving overall package throughput time. Partner with teams across Category Sourcing, Logistics, Warehousing, Last Mile, Finance, Tech, Warranty, and After-Sales (AFS) to ensure seamless process execution from procurement through to delivery. Address daily operational challenges and strategic issues by working closely with leadership teams across business functions. Lead and manage cross-functional project teams, set milestones, and ensure timely execution of Supply Chain Excellence initiatives. Establish data-driven process controls, tooling requirements, and audit mechanisms to ensure consistent process adherence. Drive adoption of new tools and operational playbooks, ensuring governance, compliance, and best practice implementation. Assess business and technical risks, manage escalations, and maintain a balance between operational needs and technical constraints. Investigate complex sourcing and supply chain challenges, design scalable solutions, and collaborate with engineering and stakeholder teams for implementation. Leverage analytics and technology to lead cross-functional coordination, resolve operational bottlenecks, and drive continuous improvement. What You Bring: 5 10 years of experience in operations, supply chain, or logistics, preferably within e-commerce or high-volume distribution environments. Proven experience in process optimization, data modeling, and performance analysis. Strong knowledge of warehouse/sort center operations and tooling systems. Demonstrated ability to manage cross-functional teams and deliver complex projects end-to-end. Excellent problem-solving, communication, and stakeholder management skills. Proficiency in data analysis tools and methodologies is a strong plus.

Position: Senior Manager, Salesforce Operations Location: Bengaluru, India (Hybrid 3 days onsite) Company: Samsara Technologies India Pvt. Ltd. About Samsara Samsara (NYSE: IOT) leads the Connected Operations Cloud, empowering industries like transportation, agriculture, and manufacturing to harness IoT data for smarter, safer, and more sustainable operations. With a global impact and a fast-scaling culture, Samsara offers unique opportunities to solve real-world challenges with cutting-edge technology. Role Overview Samsara is seeking a Senior Manager, GTMS (Go-to-Market Systems) Operations to lead the Salesforce operations team in Bangalore. Reporting to the Sr. Director of Sales Systems, this role is pivotal in building Samsara s India-based GTMS operations from the ground up, ensuring performance, scalability, and alignment across Sales, Finance, Product, and Business Technology functions. The ideal candidate is an experienced Salesforce operations leader with a passion for systems stability, stakeholder alignment, and continuous process improvement, coupled with strong people leadership and cross-functional collaboration skills. Key Responsibilities Operational Excellence & Governance Lead end-to-end incident and problem management across the Salesforce and GTMS ecosystem. Drive operational stability, reliability, and proactive issue resolution across sales systems. Manage system releases, updates, and quality control processes. Cross-Functional Collaboration Act as a bridge between Sales, Finance, Product, and IT to align systems strategy with business outcomes. Ensure seamless data flow and process integration across enterprise systems. Maintain transparent, regular communication with senior stakeholders. Strategic Planning & Cost Management Build operational strategies that support scale and growth in GTM functions. Optimize resource allocation and control budget and cost efficiency. Support and execute on long-term product and process roadmaps. Team Leadership & Development Build, mentor, and manage L2/L3 operations teams based in India. Foster an inclusive, high-performing team culture with strong talent development practices. Define KPIs and continuously improve team performance through coaching and process optimization. Vendor, Compliance & Risk Management Manage third-party vendor relationships and evaluate tools to enhance operational delivery. Enforce compliance, data security, and privacy standards within the systems landscape. Minimum Qualifications Bachelor s degree in IT, Business, or a related field (Master s preferred). 3+ years experience in a Salesforce-focused operations leadership role. Proven expertise in Salesforce Sales Cloud, CPQ, and GTM systems integration. Deep operational experience in system support, QA, and incident management. Strong executive presence, communication, and stakeholder influencing skills. High level of business acumen and ability to align tech strategy with business goals. Ideal Traits Strategic thinker with a passion for customer-centric system design. Strong collaborator across technical and non-technical teams. Agile leader ready to scale operations in a hyper-growth, data-driven environment. Curious about using AI and automation to elevate system reliability and performance. Qualification : Bachelors degree in IT, Business, or a related field (Masters preferred).

AI-ML Architect Bangalore, India Location: Bangalore Experience: 10 to 15 Years Role: AI-ML Architect Industry: IT Software / Artificial Intelligence & Machine Learning Job Overview: We are seeking a highly experienced AI-ML Architect to lead the design and implementation of advanced AI and Machine Learning systems. The ideal candidate will have extensive expertise in deep learning frameworks, system-level optimization, and scalable infrastructure, driving innovation in AI across cloud and distributed environments. Key Responsibilities: Architect, develop, and optimize deep learning and neural network applications on Windows and Linux platforms Build, train, and fine-tune advanced AI/ML models using frameworks such as PyTorch, TensorFlow, and Caffe Optimize neural network performance at the kernel level for scalability across diverse hardware architectures Lead development and deployment of AI models using techniques like Reinforcement Learning, Transfer Learning, and Federated Learning Design and develop web services and REST APIs with strong proficiency in Python and C/C++ Automate AI/ML model deployment, management, and scaling using Docker, Kubernetes, and MLOps best practices Work with hardware acceleration technologies such as OpenVINO, OneAPI DPC++, OpenCL, and CUDA to enhance performance Design and implement microservices-based AI infrastructure supporting distributed cloud environments Collaborate with cross-functional teams to integrate AI solutions with enterprise cloud architectures Required Skills & Experience: 10+ years of experience in system software development on Windows or Linux Proven expertise with deep learning frameworks: PyTorch, TensorFlow, Caffe Strong background in Reinforcement Learning, Transfer Learning, and Federated Learning Proficient in Python and C/C++ programming Hands-on experience with RESTful API development Experience automating deployments using Docker, Kubernetes, and MLOps tools Knowledge of GPU and accelerator programming: OpenVINO, CUDA, OpenCL preferred Strong understanding of cloud and distributed computing infrastructures Experience adopting microservices architecture for scalable AI platforms Preferred Qualifications: Advanced degree in Computer Science, AI, Machine Learning, or related fields Familiarity with cloud platforms such as AWS, Azure, or Google Cloud Experience in leading AI teams and mentoring architects and engineers Lead AI innovation on cutting-edge projects with global impact Collaborate in a high-growth, fast-paced environment fostering continuous learning Work with advanced AI infrastructure and state-of-the-art hardware acceleration technologies Opportunity to shape AI architecture and influence strategic technology decisions Qualification : Advanced degree in Computer Science, AI, Machine Learning, or related fields

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.

Job Title: Power Optimization & Performance Engineer Windows Platforms Job Description: Intel is seeking a Power Optimization & Performance Engineer to drive power efficiency and responsiveness enhancements across Windows platforms. The role involves deep analysis of software workloads, power-performance tuning, and debugging complex system-level issues to optimize Intel s laptop and desktop platforms. The engineer will work closely with platform architects and cross-functional teams to define power-performance metrics, develop battery life improvement strategies, and drive forward-looking technology readiness initiatives. Key Responsibilities: Power & Performance Analysis: Perform in-depth analysis of software flows at the trace, thread, and process ID levels to identify power optimization opportunities and performance bottlenecks. Platform Power Optimization: Leverage state-of-the-art analysis tools to identify and resolve battery life and performance issues in domains such as Graphics, Multimedia, Display, Imaging, and CPU. Technical Leadership & Troubleshooting: Diagnose complex system-level power and performance issues, demonstrating strong debugging expertise in Windows-based Intel platforms. Cross-Team Collaboration: Work with platform architects and engineers to define power-performance metrics, optimize power delivery across SoC components, and influence next-generation platform architectures. Windows OS & Driver Optimization: Identify and drive power savings features or performance tuning opportunities into current and next-gen Intel platforms. Collaborate with OS and driver teams for power-aware enhancements. Future Technology Readiness: Analyze expected vs. actual platform behavior, propose forward-looking enhancements, and influence SoC and Windows OS architectures. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Electronics or Computer Engineering or related fields. Technical Expertise: Embedded Systems & Software Development: Experience in software/firmware development, integration, or validation. Platform Power Management: Understanding of CPU/SoC architecture, power delivery, sensors, memory, storage, display, multimedia, and imaging subsystems. OS & System Debugging: Strong grasp of Windows OS fundamentals, system-level debugging, and exposure to firmware & device drivers. Windows Debug Tools: Experience with Windows Driver Debugging and Windows Debug tools (preferred). Power & Performance Optimization: Hands-on experience with power-performance measurement, analysis, and benchmarking. Analytical & Problem-Solving Skills: Ability to troubleshoot complex system issues and propose efficient power-saving techniques. Excellent Communication & Collaboration: Strong ability to interact across teams and drive technical discussions. About Intel s Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-ones. As Intel s largest business unit, CCG is dedicated to enhancing PC experiences, fostering innovation, and delivering market-leading computing solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates, regardless of gender, nationality, disability, or other protected status. Intel offers a highly competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Access to cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Electronics or Computer Engineering or related fields.

We are looking for a System Software Architect Programmable Vision Accelerator. As the market leader in deep learning and parallel computing, NVIDIA is seeking an expert system software architect to lead the design and implementation of firmware and driver stack for NVIDIA's Programmable Vision Accelerator (PVA) engine in the Tegra SoC platform. As a Software Architect, you will join a team of software engineers to create and evolve an essential part of the software stack responsible for scheduling and execution of highly optimized computer vision and machine learning kernels for specialized DSP hardware. You will use your design abilities, coding expertise, and creativity to help deliver innovative real-time firmware and kernel mode drivers for a low power, high performance computer vision accelerator engine. You will be architecting and developing new features and improvements to realize the groundbreaking potential of NVIDIA mobile systems, ranging from self-driving cars, intelligent video analytics and autonomous mobile robotics. You will need to demonstrate excellent technical leadership, communication, interpersonal, and analytical skills as well as a real passion for performance-oriented software engineering. If this sounds like a fun challenge, we want to hear from you! What you will be doing: Evolve and define software architecture for future NVIDIA's Programmable Vision Accelerator (PVA) chips and enhance the functionality of currently shipping products. Design and write custom embedded software for PVA engine to meet product and hardware requirements at the SoC level. Help defining forward-looking strategy and improvements to the PVA algorithms and system architecture. Review hardware specifications and map algorithms to the architecture. Participate in the bring-up of the new generation of the world's most advanced SoC. Collaborate closely with other teams and software/hardware architects across NVIDIA to support the architecture, design, creation, integration, and validation of PVA software under a common SoC umbrella. Provide technical support and guidance for internal and external customers. Mentor and guide technical development of the less experienced team members What we need to see: College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience 10+ years of working experience in embedded industry, including 5+ years in technical leadership role Deep understanding of SoC principles, general systems architectures, operating systems, device drivers, memory management, multithreading, and real-time scheduling. Deep understanding and working experience with embedded technologies including DSP, computer vision and image/signal processing. Excellent software development skills (C, C++) and outstanding problem-solving capabilities. Proven expertise in architecting embedded software and development of highly optimized code for DSP, SIMD and/or VLIW processors Experience with embedded Linux and/or QNX. Outstanding interpersonal skills with ability to work in a global and diverse team operating in a fast-paced environment. Good understanding of safety-critical software principles with experience in automotive or other highly regulated industries Ways to stand out from the crowd: Experience with ISO 26262 and IEC 61508 or equivalent quality/safety processes. Understanding of software safety and safety development processes is a major plus. Consistent record to effectively guide and influence in a technically strong dynamic environment. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking people in the world working for us. If you're creative and autonomous, we want to hear from you. NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. NVIDIA is looking for great people like you to help us accelerate the next wave of artificial intelligence. Qualification : College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 4000 employees, offices in 34 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. Our R&D division is growing globally, as a IoT/IoE Firmware Engineer, you will be a crucial member of the SolarEdge India R&D team in Bangalore, responsible for developing embedded systems and firmware for our advanced solar energy products. You will play a key role in designing, implementing, and testing embedded software, ensuring its reliability, performance, and seamless integration with our hardware platforms. Responsibilities: Design, develop, test and maintain code for modern embedded Linux based IOT devices, both in low level and system level development. Collaborate with cross-functional teams, including Embedded firmware/hardware engineers, software developers, and product managers, to define system requirements and architect innovative embedded solutions. Develop and deploy secure, scalable, and reliable IoT/IoE architectures. Interface with sensors, actuators, and microcontrollers, Collect, process, and analyze sensor data using advanced tools Develop and implement efficient and reliable embedded software in C and C++ for Embedded Linux system used in SolarEdge products" Troubleshoot and debug embedded software and hardware interactions, identifying and resolving issues throughout the product development lifecycle. Participate in code reviews, providing constructive feedback to team members and ensuring code quality and adherence to coding standards. Job Requirements Bachelor's (B.E./B.Tech.) or master s degree (M.E./M.Tech.) in Electrical/Electronics Engineering, Computer Science, or a related field. 2+ years of experience in IoT/IoE embedded systems design and firmware development. Strong programming skills in both C and C++ Experience with Python is desirable. Proven experience in building complex, high-performance systems and applications. Proficiency in using modern development tools and version control systems (e.g., Git, Docker) Experience in user space application development in Linux Ability to identify, troubleshoot hardware and software technical problems. Strong debugging and Analytical thinking, problem-solving skills Excellent communication and teamwork skills to collaborate effectively with cross-functional teams. Experience in the renewable energy or power electronics industry is an added advantage. Provide technical support and troubleshooting assistance during product development. Stay up to date with the latest advancements in power electronics and firmware technologies. Drive results within constraints of Product life cycle development and production at scale. Results-oriented mindset with a focus on achieving tangible and measurable results. SolarEdge recognizes its talented and diverse workforce as a key competitive advantage. Our business success is a reflection of the quality and skill of our people. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance. Qualification : Bachelor's (B.E./B.Tech.) or masters degree (M.E./M.Tech.) in Electrical/Electronics Engineering, Computer Science, or a related field.

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Engineer will be working on Embedded Firmware which involves feature development, integration, and bug fixing and maintenance. Experience in embedded architecture, external interfaces, product constraints, along with ability to develop architectures/features that meet these constraints while providing new value for the platform. Strong Experience in C\C++ Strong Experience in embedded Systems Strong Experience in RTOS System level design Experience in low level programming in ARM or ARC architecture Experience in debugging Embedded system software with Innovative techniques Experience in capturing and debugging based on HW Signals. Experience in Requirement understanding and designing solution with good presentation skills.Add-on:- Experience in USB Protocol- Experience in PCI System flows- Experience in Bluetooth Controller / Host protocols( BR\EDR) and Bluetooth Low Energy- Exposure to Python scripting.- Agile and scrum practices Qualifications Bachelor's or Master s degree in computer science, Electronics and communication Engineering or a related field with 4 years of experience. Proven experience in Embedded system software / Firmware development in RTOS environment with strong system knowledge in understanding the requirements and making the design, development and deployment in embedded products. Solid understanding of software development life cycle (SDLC) and Agile methodologies. Excellent problem-solving skills and attention to detail. Strong written and verbal communication skills. Experience in maintaining and managing codebases, ensuring high standards of code quality. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Bachelor's or Masters degree in computer science, Electronics and communication Engineering or a related field with 4 years of experience.

General Summary: Join the Qualcomm AI Systems Solution CoE (Center of Excellence) team to develop cutting-edge products and solutions leveraging Qualcomm s high-performance inference accelerators for cloud, edge, and hybrid AI applications. This role focuses on designing and delivering AI/ML system software solutions for diverse industries, including automotive, cloud, and industrial IoT. You will work on optimizing ML models (including GenAI, LLMs, LVMs, and LMMs) for deployment across a variety of devices, including phones, AI PCs, and edge appliances. This is your opportunity to contribute to Qualcomm s energy-efficient AI compute systems and collaborate with cross-functional teams to develop solutions that exceed industry standards. Key Responsibilities: Develop system solutions for AI/ML requirements, including model optimization, inference graph tuning, and scalable deployment across various devices. Work with deep learning frameworks like PyTorch, TensorFlow, and ONNX. Optimize AI/ML models using techniques such as quantization, pruning, and compression. Define and evaluate performance and accuracy metrics for neural network models, including CV, NLP, and multi-modal architectures. Collaborate across functional teams to ensure scalable, efficient deployments on inference accelerators and edge devices. Monitor and analyze industry trends and competitor toolchains to innovate and enhance system solutions. Develop and debug high-quality software in Python and C++, leveraging object-oriented design principles. Lead projects to improve toolchains and develop innovative product features. Required Skills and Experience: Hands-on experience with deep learning frameworks: PyTorch, TensorFlow, and ONNX. Strong understanding of model architectures (CV, NLP, LLMs, and multi-modal networks). Proficiency in Python and C++ (skill level: 7/10 or higher). Expertise in data structures and algorithms (skill level: 7/10 or higher). Experience in inference graph optimization, quantization-aware training, and deployment of AI/ML models. Knowledge of AI edge and server systems, infrastructure, and industry standards. Familiarity with ONNX Runtime, PyTorch runtime, and TensorFlow runtime. Experience in competitor toolchain surveys and emerging trends in AI/ML. Excellent debugging, analytical, and development skills. Desirable Skills: Experience with GPUs, machine learning accelerators, and related software. Familiarity with ML compilers like TVM, GLOW, and XLA. Hands-on use of version control tools like Git and GitHub. Knowledge of LLM fine-tuning and advanced training techniques. Qualifications: Bachelor s, Master s, or PhD degree in Engineering, AI/ML, Computer Science, or a related field. Work Experience: Bachelor s degree with 3+ years of relevant experience. Master s degree with 2+ years of relevant experience. PhD with 1+ year of relevant experience. Qualification : Bachelor's / Masters/ PHD degree in Engineering, Machine learning/ AI, Information Systems, Computer Science, or related field.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.