LOW Level Programmer Jobs in Bengaluru

Job Title: Embedded Developer Location: Bangalore Experience: 2 5 Years Responsibilities Debug embedded systems efficiently to identify and resolve issues. Develop embedded software for microprocessor/microcontroller-based systems. Design, develop, test, and maintain embedded software modules. Work independently with guidance from the business team to meet product objectives. Take ownership of planning and delivering components/modules within schedule and quality standards set by the product owner. Design and build highly scalable, available, and resilient cloud solution architectures related to embedded systems. Demonstrate strong analytical skills and proactively learn new technologies to enhance product capabilities. Requirements Proficient in C/C++ programming for embedded systems development. Experience in developing SDKs and libraries using C/C++. Strong Linux programming skills. Familiarity with V4L2 and LibCamera libraries. Hands-on experience in developing device drivers. Experience programming on RTOS (Real-Time Operating Systems). Proven track record in designing, coding, and testing embedded systems. Practical experience working with hardware platforms such as Raspberry Pi and other microcontroller-based boards. Excellent debugging skills for embedded software. Working knowledge of communication protocols: SPI, UART, I2C. Experience with image processing libraries such as OpenCV. Knowledge of software release management processes. Familiarity with source code management tools like GitHub and Bitbucket. Experience using CI/CD tools such as Jenkins for automated build and deployment.

Job Title: C/C++ Engineer Location: Bangalore Experience: 3 5 Years Qualification: Bachelor s or Master s Degree in Computer Science or a related field Job Description Hands-on experience with Boot Loader, Linux BSP, Linux kernel development, Linux porting, and application development. Proficient in Buildroot, Yocto, and OpenEmbedded build systems. Skilled in device driver development. Experience working on Linux BSP for platforms such as NXP, TI Sitara, or Qualcomm. Proficient in shell scripting and writing Makefiles. Strong debugging and problem-solving abilities. Excellent communication skills to collaborate effectively within teams. Qualification : Bachelors or Masters Degree in Computer Science or a related field

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 4000 employees, offices in 34 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. Our R&D division is growing globally, as a IoT/IoE Firmware Engineer, you will be a crucial member of the SolarEdge India R&D team in Bangalore, responsible for developing embedded systems and firmware for our advanced solar energy products. You will play a key role in designing, implementing, and testing embedded software, ensuring its reliability, performance, and seamless integration with our hardware platforms. Responsibilities: Design, develop, test and maintain code for modern embedded Linux based IOT devices, both in low level and system level development. Collaborate with cross-functional teams, including Embedded firmware/hardware engineers, software developers, and product managers, to define system requirements and architect innovative embedded solutions. Develop and deploy secure, scalable, and reliable IoT/IoE architectures. Interface with sensors, actuators, and microcontrollers, Collect, process, and analyze sensor data using advanced tools Develop and implement efficient and reliable embedded software in C and C++ for Embedded Linux system used in SolarEdge products" Troubleshoot and debug embedded software and hardware interactions, identifying and resolving issues throughout the product development lifecycle. Participate in code reviews, providing constructive feedback to team members and ensuring code quality and adherence to coding standards. Job Requirements Bachelor's (B.E./B.Tech.) or master s degree (M.E./M.Tech.) in Electrical/Electronics Engineering, Computer Science, or a related field. 2+ years of experience in IoT/IoE embedded systems design and firmware development. Strong programming skills in both C and C++ Experience with Python is desirable. Proven experience in building complex, high-performance systems and applications. Proficiency in using modern development tools and version control systems (e.g., Git, Docker) Experience in user space application development in Linux Ability to identify, troubleshoot hardware and software technical problems. Strong debugging and Analytical thinking, problem-solving skills Excellent communication and teamwork skills to collaborate effectively with cross-functional teams. Experience in the renewable energy or power electronics industry is an added advantage. Provide technical support and troubleshooting assistance during product development. Stay up to date with the latest advancements in power electronics and firmware technologies. Drive results within constraints of Product life cycle development and production at scale. Results-oriented mindset with a focus on achieving tangible and measurable results. SolarEdge recognizes its talented and diverse workforce as a key competitive advantage. Our business success is a reflection of the quality and skill of our people. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance. Qualification : Bachelor's (B.E./B.Tech.) or masters degree (M.E./M.Tech.) in Electrical/Electronics Engineering, Computer Science, or a related field.

Engineer will be working on Embedded Firmware which involves feature development, integration, and bug fixing and maintenance. Experience in embedded architecture, external interfaces, product constraints, along with ability to develop architectures/features that meet these constraints while providing new value for the platform. Strong Experience in C\C++ Strong Experience in embedded Systems Strong Experience in RTOS System level design Experience in low level programming in ARM or ARC architecture Experience in debugging Embedded system software with Innovative techniques Experience in capturing and debugging based on HW Signals. Experience in Requirement understanding and designing solution with good presentation skills.Add-on:- Experience in USB Protocol- Experience in PCI System flows- Experience in Bluetooth Controller / Host protocols( BR\EDR) and Bluetooth Low Energy- Exposure to Python scripting.- Agile and scrum practices Qualifications Bachelor's or Master s degree in computer science, Electronics and communication Engineering or a related field with 4 years of experience. Proven experience in Embedded system software / Firmware development in RTOS environment with strong system knowledge in understanding the requirements and making the design, development and deployment in embedded products. Solid understanding of software development life cycle (SDLC) and Agile methodologies. Excellent problem-solving skills and attention to detail. Strong written and verbal communication skills. Experience in maintaining and managing codebases, ensuring high standards of code quality. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : Bachelor's or Masters degree in computer science, Electronics and communication Engineering or a related field with 4 years of experience.

IBM India Systems Development Lab is looking for Software Engineer / Developer to be integral part of a team responsible for Product Development/testing of PowerVC Platform on Power. The product is built on the Openstack cloud computing platform using Python. In addition, there is an opportunity to work on several OpenSource communities and front end/back end development as well. Your role and responsibilities As a python cloud development engineer you will Design, development and test Power Private Cloud software. Able to understand the architecture and turn the requirements into high level and low level designs Active open source contributions and participation and open source tools knowledge is preferred Software development in Cloud Domain, OpenStack, Virtualization, Linux OS Internals, Networking / Storage/ Security / Infrastructure as a Service is preferred Understanding of any cloud based virtualization software [GCP, Azure] and Openstack concepts. Work with OpenSource community and contribute towards open source development / Testing. Good understanding and hands on with full stack cloud development is preferred. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of experience in the IT industry 4+ years of experience working as a developer well versed with feature enablement on private/public cloud platforms or in an equivalent role supporting partners and enterprises 4+ years of experience with solutions development or implementation in Unix or Linux environments using python programming language. 2+ years of experience working with Ansible [ Nice to have ]. Proficient in Python programming and scripting experience and Openstack concepts. Experience working in Open Source communities is a big plus. Proven experience architecting, designing, and developing complex customer solutions in a rapidly evolving technology domain Ability to perform customer-facing activities in a fast-paced environment with short timeframes Experience with concepts of Openstack cloud computing platform. Ability to uncover business challenges and develop custom solutions to solve these challenges Working knowledge of object-oriented design and design patterns applicable to modern software development Applied knowledge of working with agile, scrum, and DevOps teams Clear understanding of cloud service and deployment models Comfortable working with highly distributed teams, including interaction with open source communities Ability to study on your own, learn quickly, and put new knowledge into practice Any commercial experience with technologies like Openstack, virtualization and public cloud services, e.g., Amazon Web Services (AWS), Microsoft Azure, or Google Cloud Platform (GCP) Ability to quickly learn new technologies, frameworks, and techniques; ability to facilitate technical conversations within your team and with external stakeholders Keen interest contributing to and building communities in open source Ability to work both on your own and as part of an agile team. Preferred technical and professional experience Hands-on experience on Openstack based clouds, basic concepts of virtualization, strong with Python programming, automation using Ansible Qualification : Bachelor's Degree

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

We are looking for a System Software Architect Programmable Vision Accelerator. As the market leader in deep learning and parallel computing, NVIDIA is seeking an expert system software architect to lead the design and implementation of firmware and driver stack for NVIDIA's Programmable Vision Accelerator (PVA) engine in the Tegra SoC platform. As a Software Architect, you will join a team of software engineers to create and evolve an essential part of the software stack responsible for scheduling and execution of highly optimized computer vision and machine learning kernels for specialized DSP hardware. You will use your design abilities, coding expertise, and creativity to help deliver innovative real-time firmware and kernel mode drivers for a low power, high performance computer vision accelerator engine. You will be architecting and developing new features and improvements to realize the groundbreaking potential of NVIDIA mobile systems, ranging from self-driving cars, intelligent video analytics and autonomous mobile robotics. You will need to demonstrate excellent technical leadership, communication, interpersonal, and analytical skills as well as a real passion for performance-oriented software engineering. If this sounds like a fun challenge, we want to hear from you! What you will be doing: Evolve and define software architecture for future NVIDIA's Programmable Vision Accelerator (PVA) chips and enhance the functionality of currently shipping products. Design and write custom embedded software for PVA engine to meet product and hardware requirements at the SoC level. Help defining forward-looking strategy and improvements to the PVA algorithms and system architecture. Review hardware specifications and map algorithms to the architecture. Participate in the bring-up of the new generation of the world's most advanced SoC. Collaborate closely with other teams and software/hardware architects across NVIDIA to support the architecture, design, creation, integration, and validation of PVA software under a common SoC umbrella. Provide technical support and guidance for internal and external customers. Mentor and guide technical development of the less experienced team members What we need to see: College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience 10+ years of working experience in embedded industry, including 5+ years in technical leadership role Deep understanding of SoC principles, general systems architectures, operating systems, device drivers, memory management, multithreading, and real-time scheduling. Deep understanding and working experience with embedded technologies including DSP, computer vision and image/signal processing. Excellent software development skills (C, C++) and outstanding problem-solving capabilities. Proven expertise in architecting embedded software and development of highly optimized code for DSP, SIMD and/or VLIW processors Experience with embedded Linux and/or QNX. Outstanding interpersonal skills with ability to work in a global and diverse team operating in a fast-paced environment. Good understanding of safety-critical software principles with experience in automotive or other highly regulated industries Ways to stand out from the crowd: Experience with ISO 26262 and IEC 61508 or equivalent quality/safety processes. Understanding of software safety and safety development processes is a major plus. Consistent record to effectively guide and influence in a technically strong dynamic environment. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking people in the world working for us. If you're creative and autonomous, we want to hear from you. NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. NVIDIA is looking for great people like you to help us accelerate the next wave of artificial intelligence. Qualification : College degree (preferably PhD or MS) in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience

Job Overview Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various systems like Digital/Analog/RF/optical systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop world-class products that meet performance requirements. Key Responsibilities Front-End Implementation: Develop and implement MSIP designs, including Temp/Voltage/Security Sensors and Controllers. RTL Development: Design, validate, and ensure the proper functioning of RTL for linting, clock-domain crossing, conformal low power, and DFT (Design for Test) rules. Verification: Work with the functional verification team to create test plans, debug issues, and ensure that all designs meet the required specifications. Timing Constraints: Develop timing constraints, deliver synthesized netlists to the physical design team, and provide support for Physical Design STA (Static Timing Analysis). Low Power Checks: Write UPF (Unified Power Format), perform power-aware equivalence checks, and ensure compliance with low-power design standards. DFT Insertion & Analysis: Perform DFT insertion and ATPG (Automatic Test Pattern Generation) analysis for optimal SAF (Scan Acceptance Fault) and TDF (Transition Delay Fault) coverage. SoC Integration Support: Provide support for SoC integration and pre/post-silicon debugging at the chip level. Minimum Qualifications Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. Skills & Experience Educational Background: MTech/BTech in EE/CS with 3+ years of hardware engineering experience. Technical Experience: Expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debugging is a plus. Collaboration: Ability to work effectively with teams across the globe and possess strong communication skills. Qualification : MTech/BTech in EE/CS with 3+ years of hardware engineering experience.

Technical Requirements: 1. Verification Experience: Strong experience in SoC, sub-system, and block-level verification. Ability to handle different verification stages and methodologies for complex systems. 2. Hands-on Experience with ARM Architecture and AMBA Protocol: ARM architecture familiarity, particularly at the SoC and sub-system level. Expertise in AMBA protocol (e.g., AHB, APB, AXI) and its application in SoC verification. 3. Verification Methodologies: Proficient in UVM/OVM, SystemVerilog, Verilog, and C-based verification methodologies. Solid understanding of testbenches (TB), test cases, and automation methodologies. Experience in test automation scripting with languages such as TCL, Perl, and Python. 4. Exposure to Advanced Verification Techniques: GLS (Gate-Level Simulation) experience is a plus. Power-aware verification knowledge, ensuring low power consumption in designs. 5. Protocol Knowledge: Working knowledge of industry protocols such as PCIe, DDRx, Ethernet, USB, I2C, SPI, among others. Familiarity with AXI, AHB, APB protocols for data communication in embedded systems. 6. RTL Debugging & Tools Proficiency: Strong RTL debugging skills to identify and resolve issues in designs. Well-versed with industry-standard verification tools used in simulation, debugging, and analysis. 7. Building Testbenches & Test Cases: Extensive experience in building testbenches from scratch. Ability to create and implement detailed test cases for different verification scenarios. Expectations from the Role: 1. Communication and Interpersonal Skills: Strong ability to communicate technical concepts effectively both within the team and with other stakeholders. Clear verbal and written communication skills for reporting progress and challenges. 2. Independent and Team-based Work: Ability to work independently on projects or as part of a team. Able to take ownership of tasks and contribute to team discussions effectively. 3. Learning and Adaptability: Ability to learn quickly and adapt to evolving technologies and methodologies. Stay updated with advancements in verification techniques and tools. 4. Ownership and Accountability: Demonstrated ownership of projects, ensuring timely completion and addressing any challenges that arise. Ensuring high-quality results through attention to detail. 5. Leadership & Mentorship: Ability to mentor and lead junior engineers and verification teams. Provide guidance in solving complex problems and ensuring successful project outcomes. 6. Punctuality and Responsibility: Demonstrated punctuality in meeting deadlines and project milestones. Timely execution of tasks and troubleshooting to maintain project timelines. Ideal Candidate Profile: The ideal candidate will have significant experience with SoC verification, ARM architecture, and verification methodologies such as UVM and SystemVerilog. The candidate should possess strong protocol knowledge and be proficient in debugging RTL and automating test scenarios. A key aspect of the role is the ability to work independently, take ownership of tasks, and guide the team in solving technical challenges. Leadership and mentoring abilities are essential, as is the capacity to manage multiple tasks effectively in a distributed work environment.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Role Summary The Senior Solutions Architect owns and drives the architectural vision of the product or solution and ensures the development of efficient solutions to meet current and future needs of clients primarily from the BFSI domain. Responsible for ensuring that business requirements are met and providing technology leadership across all project engagements in the BFSI vertical. Key Responsibilities Own and oversee the technology practice for all projects within the BFSI (India) VBU. Provide technical leadership across a diverse technology stack, encompassing mobile and web applications. Define and review technical architectures, both at high and low levels of design. Ensure the implementation of optimized processes for code review, project output, and adherence to industry best practices. Build, develop, and guide high-performing talent, establishing a long-term talent strategy spanning technology domains. Act as an unblocker in an agile environment, assisting architects, analysts, and developers with challenges and problem-solving. Engage in hands-on coding while mentoring or assisting other team members. Stay abreast of emerging technologies and trends in engineering and development within the BFSI domain. Act as a technology evangelist, representing the company in external forums. Overall experience of 15+ years. Minimum 5 years experience in Solutioning Enterprise Mobile and Web Applications preferably for BFSI products. Extensive hands-on experience in Backend, Web, Mobile, Cloud, Artificial Intelligence technologies. Proficiency with server side languages like Java / Node.js / Python. Proficient in using architecture modeling tools and frameworks. Solid understanding of security, data privacy, and compliance considerations in the BFSI sector. Preferably having a good understanding of regulatory frameworks governing the BFSI sector, such as RBI Guidelines, DPDPA, PCI DSS and industry-specific regulations. Experience in designing and implementing microservices-based architectures. Knowledge of containerization and orchestration tools like Docker and Kubernetes. Proficiency in designing, implementing, and managing APIs for seamless integration of systems. Experience in at least one Cloud (AWS/Azure/GCP) platform. Strong knowledge of native and cross-platform technologies - Android, Kotlin, iOS, Swift, Objective C, React Native, Flutter and working with MVVM, MVP, MVC patterns. Familiarity with JavaScript frameworks such as Node, Angular and React. Familiarity with database technology such as Oracle, MySQL and MongoDB. Qualifications Education: Overall experience of 15+ years. Minimum 5 years experience in Solutioning Enterprise Mobile and Web Applications preferably for BFSI products. Skills Desired TOGAF Certification. AWS Certification. DevSecOps knowledge. Experience in BFSI domain. Competencies Desired Technical / Functional: Relevant certifications in the BFSI domain. Behavioural: Excellent communication skills, Stakeholder management. Qualification : Overall experience of 15+ years. Minimum 5 years experience in Solutioning Enterprise Mobile and Web Applications preferably for BFSI products.

Minimum qualifications: Bachelor s degree or equivalent practical experience. 12 years of experience in IT Industry with building and developing infrastructure or distributed systems. Experience in consulting, IT services and Security Check (SC), security clearance. Preferred qualifications: Experience helping customers decide to make investments in new technologies and projects based on expected value and Return on Investment (ROI). Experience with data center migration strategies and collaborating with channel partners and systems integrators. Experience designing, building, and deploying scalable cloud-based solution architectures. Experience engaging product organization and influencing them to work on product features to drive the overall product strategy and roadmap. Ability to work on a team to design processes, implement strategic projects that solve business problems, and lead or work effectively with cross-functional groups. About the job Google's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers. Using your extensive technical and leadership expertise, you manage projects of various size and scope, identifying future opportunities, improving processes and driving the technical directions of your programs. As a Google Distributed Cloud (GDC) Cluster Lead, you will drive the adoption of Air Gapped and Connected Cloud as a result-driven Trusted Advisor to the largest customers, ultimately responsible for ensuring their overall success and transformation with Google Cloud. You will align at the executive level, building and maintaining strong relationships with business executives and IT stakeholders, both internal and external, and understand their business requirements and goals. Building on this knowledge, you will lead the shared strategic roadmaps to drive customer partnerships through pre-sales and delivery, provide technical guidance and programme leadership, and facilitate customers digital transformation to maximize their value on Google Cloud. Google Cloud accelerates every organization s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems. Responsibilities Manage programs covering customer s GDC program planning, delivery assurance and verification, tracking, reporting, and risk and mitigation planning. Drive the customer partnership for key strategic customers, from a delivery standpoint. Establish executive relationships with business and IT stakeholders to understand their objectives. Accelerate customer s migration to GDC Air-Gapped by influencing all relevant stakeholders and removing roadblocks. Ensure that customers derive maximum value from their investment in Google Cloud. Assess their capabilities, collaborate with other Google stakeholders and prescribe recommendations to help them accelerate GDC deployments and achievement of their business targets. Leverage adoption methodology and transformation framework, conduct customer Quarterly Business Reviews (QBRs), advocate for customers to rapidly knock down adoption blockers, and coordinate across multiple work streams and teams to maintain customer momentum. Qualification : Bachelors degree or equivalent practical experience.

Job Description: Arm s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in today's Enterprise, Auto and Client markets. Responsibilities: As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience : 4-15 years of proven experience in working on IP/Subsystem/Soc Verification Experienced in one or many of these technologies/ protocols - PCIe, CXL, USB, Ethernet. Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs. Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies UVM, formal and low power. Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support. Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers. Nice To Have Skills and Experience : Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture/micro-architectures! In Return: With offices around the world, Arm is a diverse organisation of dedicated, innovative and very hardworking engineers. By enabling a vibrant, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their outstanding contributions to Arm's success in the global marketplace Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arm s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Qualification : 4-15 years of proven experience in working on IP/Subsystem/Soc Verification

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

If you re looking for a career where you can make a real impression, join HSBC and discover how valued you ll be. HSBC is one of the largest banking and financial services organisations in the world, with operations in 62 countries and territories. We aim to be where the growth is, enabling businesses to thrive and economies to prosper, and, ultimately, helping people to fulfil their hopes and realise their ambitions. We are currently seeking an experienced professional to join our team in the role of Site Lead, Global Trade Solutions (GTS) Business Services Business: Digital Business Services Principal responsibilities: Impact on the Business: To deliver superior customer service by driving operational performance, (meeting PLAs, reducing cost, driving operational efficiency, and reducing operational risks). Manage GSC ( Global Service Centers ) /BS ( Business Services ) resources effectively to meet strategic objectives of the business. Support and drive effective cross training programmes across GSC/BS locations to ensure that the GSC/BS are adequately resourced to meet the demands of the business. Typical KPIs and Targets: Meet or Exceed PLAs ( Performance Level Agreement ) , drive OOE ( Overall Operating Efficiency ) , reduce operational risk by raising awareness/ sharing best practice, within Business Services Support other Trade BS locations when required to ensure the BS provide the best possible service to the business and their customers. Drive SELF programme, ensure effective cross training programmes are in place. Keep aware of industry changes and opinions. Customers / Stakeholders: Ensure that the customer is at the heart of everything we do both personally and as an organisation. To partner with Global Businesses, Global Change Delivery and other stakeholders to drive operational change programmes and have oversight of operational change programmes that impact the Business Service To assume overall responsibility for process management and operational integrity of the GSC/BS site. Typical KPIs and Targets: Meeting or exceeding PLAs, going the extra mile to deliver superior customer service. Improving trend in both internal and external customer satisfaction scores Ensure that all operations are handled in accordance with procedures and that the Management Team fully understands the operational and financial risks associated with production processing. Leadership & Teamwork: Lead a highly motivated and skilled team, which allows the GSC/BS to meet the business objectives. Build and maintain good working relationships with Business Partners, operate in an open and transparent way being fully accountable for supporting their business. Support other Business Service Teams, Global Transformation and/or other stakeholders in driving operational change programmes. Typical KPIs and Targets: Ensure that all staff have objectives, regular 1:1s, and that SELF training plans/development plans are in place and being monitored. Monthly BP meetings to discuss performance and clear accountability for follow up actions. Active participation and delivery of Global Change programmes Operational Effectiveness & Control: To provide a platform to enable Group companies to significantly reduce their operating costs whilst maintaining Customer service standards. To continually re-assess the operational risks inherent in the business donor Group companies. Ensure adequate contingency procedures are in place to minimize the impact of partial or total site failure. To be aware of the nature of our customers business/trading patterns and alert to any out of the ordinary transactions, which should be escalated to Senior Management To be fully conversant with FIM ( Functional Instruction Manual ) , anti-money laundering and sanctions and internal procedures/polices and regulatory requirements of our business. Typical KPIs and Targets: Be aware of changing economic or market conditions, legal and regulatory requirements, operating procedures, management restructures, and the impact of new technology in conjunction with the donor Group companies. Identifying potential risks and raising with the appropriate party e.g. Risk. Ensure contingency requirements are continually updated in terms of strategic changes on account of migration growth plans in conjunction with central BCP ( Business Continuity Planning ) team. Major Challenges: The nature of the role requires that highly effective resource management techniques be employed to ensure optimal operational efficiency across a wide variety of processes migrated to the GSC from the GTS business. The complexity of the role also requires the job holder to have an in depth understanding of the Trade business and industry standards such as UCP/URC/ISBP ICC opinions/URR. Staff retention will be a significant challenge due to the increasingly competitive nature of the GTS business and the BPO industry in the countries where some of the Business Services teams are located. It is essential that the GSC/BS management team demonstrates HSBC values and is able to lead and motivate staff with widely differing aspirations working in a high-pressure productivity-based environment where deadlines are critical. Job satisfaction through rotation is a key requirement to aid retention therefore effective training and resource management is essential. In migrating work to the GSC Group companies must feel confident that their business is not being put at a greater risk. Effective business knowledge combined with operational risk management will be essential in developing trust and confidence within the business. Role Context: The establishment of the Global Trade Solutions Business Services locations within Digital Business Services is a key part of Commercial Banking strategy, aimed at allowing them to grow their business, drive global consistency, improve customer service and reduce operational risk. The GSC environment focuses on the delivery of a highly professional custom...

GSK is a place where outstanding people do amazing things. As a science-led global healthcare company, we exist to help people do more, feel better, live longer. With such a diverse global workforce, GSK needs a team of HR experts to support and improve the lives of our patients, consumers and employees. Our values-led, high-performance culture is anchored by our HR team, and you can be part of keeping this momentum. Job Purpose Improving the employee experience is central to our HR mission, and the newly formed Global Experience Owner group needs a senior change professional to translate the initiatives and strategies coming from this group into relevant messages that all employees can relate to. This role is central to how employees perceive HR s offering to them, both from a process and systems standpoint as well as service delivery. This role will ensure the business is engaged appropriately to understand the impact of the change, is readied to receive it, and has the support to adopt and embed the change to plan and quality, with minimal business disruption, ideally leaving them delighted with the change. The role requires close interaction with the impacted business stakeholders, GXOs, Senior HR leaders, and other change professionals across GSK. Role Responsibilities: Looking at annual HRLT priorities, creates a strategy that links various items to be delivered by GXO group into a clear and connected compelling message, underscoring the value HR is giving to GSK s people through these changes. This includes development and delivery of robust Change plans, including supporting communication, that are fully aligned with the ongoing priorities and plans of the function they support. Collaborating with other programmes (across HR, also other functions if needed) to understand and mitigate the cumulative impact of change on individuals and teams Managing a complex stakeholder landscape to ensure understanding, buy in, and a smooth path for delivery. Engagement requirements may also include third party vendors and offshore business services centres. Facilitating change and engagement workshops, including working with the People Experience Network and the UX lab to ensure the business itself is validating the solutions being delivered. Ensuring an appropriate network of change agents in place to support delivery of the change in their area Leveraging tools and capabilities to support leaders, managers, and employees through the change journey, ensuring a high-quality Employee Experience (EE), using Human Centric Design principles and tools Executing business readiness and embedding activities to measure whether impacted employees are ready for the change, and able to confirm the change embeds successfully Ability to craft executive messages for key programmes to educate internal HR colleagues on upcoming changes In times of unexpected system issues, quickly connect with stakeholders to communicate necessary information to impacted people, in short turnaround time Take initiative to build capabilities in GXO teams, so they understand change impacts, draft user stories that are easy to relate to, identify and align stakeholders towards the change and run Communities of Practice. Design and deliver regular communication content that is needed to keep Service Delivery Teams updated on ongoing enhancements to systems and processes. Role Requirements: Total 16+ years of experience Degree level education preferred MBA Business Change Management related experiences in process and tech programmes, focused on narrating the employee experience Excellent communication skills and the ability to work flexibly within a matrix team; Proven understanding and experience in standard business change and adoption tools Able to operate in an environment of high complexity and ambiguity, at a very fast pace Experience of delivering multi-national, large scale change, taking an enterprise mindset (able to see big picture) Ability to put important operational messages into a business context, drawing on global, business unit, and functional communication messages Experience of working in target operating model, process, and/or technology change Effective in an environment with tight deadlines, finite resource and uncertainty. Drives performance against timelines and budget constraints Desirable: Human centric design experience Organisational Development capability & experience of operating model change Prosci Practitioner or other equivalent Change Management certification Agile Practitioner At GSK we value diversity (Gender, LGBTQ +, PwD etc.) and treat all candidates equally. We aim to create an inclusive workplace where all employees feel engaged, supportive of one another, and know their work makes an important contribution. #LI-GSK Uniting science, technology and talent to get ahead of disease together. GSK is a global biopharma company with a special purpose to unite science, technology and talent to get ahead of disease together so we can positively impact the health of billions of people and deliver stronger, more sustainable shareholder returns as an organisation where people can thrive. We prevent and treat disease with vaccines, specialty and general medicines. We focus on the science of the immune system and the use of new platform and data technologies, investing in four core therapeutic areas (infectious diseases, HIV, respiratory/ immunology and oncology). Our success absolutely depends on our people. While getting ahead of disease together is about our ambition for patients and shareholders, it s also about making GSK a place where people can thrive. We want GSK to be a place where people feel inspired, encouraged and challenged to be the best they can be. A place where they can be themselves feeling welcome, valued, and included. Where they can keep growing and look after their wellbeing. So, if you share our ambition, join us at this exciting moment in our journey to get Ahead Together. Importa...

Job Title: Statistical Programming Associate Director Career Level - E Introduction to role The Statistical Programming Associate Director is accountable for the quality, timely, and efficient delivery of project programming work and good information management. This position requires profound programming experience and excellent industry knowledge to independently lead the implementation of programming activities as well as lead other programmers. It is a leadership role that can have a project or technical focus. It will provide subject matter expertise within the Programming discipline. As an expert within their own field, you will act as a specialist within cross-functional teams to deliver continuous improvement. Accountabilities Leads and directs the full scope of project delivery and/or leads a technical project within the TA/Drug Project/study/function Leads implementation of statistical programming aspects of the protocol or clinical development program Responsible for the high quality of all project deliverables, holding partners and providers accountable for the quality of their deliverables and/or technical subject matter expert for aspect(s) of the TA, Project, or function Leads or contributes to cross-functional administrative or process improvement initiative(s) Drives the development of best practices to improve quality, efficiency, and/or effectiveness within the function Drives standards development and implementation Manages and escalates risk in complicated or novel situations within their study and/or projects Provides Programming expertise to the team Provides tactical input and/or drives ideas and improvements Contributes to the function by supporting recruiting and/or providing training and mentorship Identifies opportunities to improve methodology and provides practical solutions for problems Manages activities of our external partners (i.e., Contract Research Organisations) Influences stakeholders by providing subject matter expertise on programming-related items Ensures compliance with standards and automation usage Employs all project management practices in managing drug or technical projects Provides input to capacity management for all projects in scope Maintains expertise in the latest industry and regulatory requirements to stay current Essential Skills/Experience Degree in Mathematics (i.e., Applied Math, Engineering, etc), Statistics, Computer Science, Life Science or equivalent Proven programming expertise Thorough knowledge of the clinical development process Thorough knowledge of industry standards and ability to implement them Ability to apply programming expertise to problem-solving and troubleshooting for teams Current knowledge of technical and regulatory requirements relevant for the role Ability to proactively manage concurrent activities within a project Proficient ability to influence relevant stakeholders on programming-related items Ability to manage risk in complicated or novel situations Project Mindset AstraZeneca embraces diversity and equality of opportunity. We are committed to building an inclusive and diverse team representing all backgrounds, with as wide a range of perspectives as possible, and harnessing industry-leading skills. We believe that the more inclusive we are, the better our work will be. We welcome and consider applications to join our team from all qualified candidates, regardless of their characteristics. We comply with all applicable laws and regulations on non-discrimination in employment (and recruitment), as well as work authorization and employment eligibility verification requirements. Qualification : Degree in Mathematics (i.e., Applied Math, Engineering, etc), Statistics, Computer Science, Life Science or equivalent

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Software Developer C++ Location: Bangalore, Karnataka, India Employment Type: Full-time, Permanent Experience Level: Experienced Professional (6-8 years) Role Overview We are seeking a proactive and skilled Full Stack Developer with deep expertise in C++ to contribute to the development of MR image reconstruction modules integrated with AI. The ideal candidate will actively research and innovate MR reconstruction techniques, improve module performance, and collaborate closely with cross-functional teams to deliver high-quality medical imaging solutions. Key Responsibilities Develop, improve, test, and maintain MR image reconstruction modules. Conduct research to enhance acquisition speed, data extraction, noise/artifact robustness, and overall reconstruction quality. Develop AI inferencing code, prepare data, and support model training activities. Manage code repositories and version control systems such as Git or Azure Repos. Participate actively in design discussions, code reviews, and agile development processes. Troubleshoot and optimize module performance, security, and scalability. Collaborate with product owners and stakeholders to manage backlogs and ensure continuous feature delivery. Required Skills & Qualifications Education: BE/B.Tech/MCA/ME/M.Tech from a recognized institution. Core Expertise: Strong practical experience in C++ development, object-oriented programming, and design patterns. Additional Skills: Python programming experience (advantageous). Knowledge of medical imaging modalities, particularly MRI (preferred). Strong foundation in physics, mathematics, signal processing, linear algebra, probability, and random processes. Understanding of inverse problems, AI, imaging chains, MR reconstruction, and pulse sequences is a plus. Soft Skills: Strong analytical and problem-solving skills, clear communication, and a passion for learning and creative thinking. Tools: Experience with Azure Repos or Git for version control. Experience 6 to 8 years of core development experience with C++. Collaborative work environment fostering professional growth. Challenging projects enhancing technical expertise. Competitive compensation and benefits.