NVH Noise Jobs in Bengaluru

When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose The Senior Application Engineer is responsible for leveraging their experience, subject matter expertise, and customer-relationship skills to assist in growing our software business by proactively helping customers deploy ANSYS technology to deliver on their key business initiatives. This role is focused on the Automotive Industry for applications like crashworthiness, occupant, and pedestrian safety. Key Duties and Responsibilities Collaborate with Sales to create solutions to complex customer problems using LS-DYNA and other Ansys structural simulation software. Support Automotive customers in developing methods for crash and safety-related simulation. Present ANSYS value proposition to executive-level audiences. Lead high-profile business development projects and analysis of complex technical problems. Provide best practices to help customers derive more value from ANSYS solutions. Participate in internal corporate initiatives for product enhancement, consulting, and training. Minimum Education / Certification Requirements and Experience BS in engineering or a related technical discipline. Minimum 5 years of experience in automotive crash-related simulation. Knowledge of LS-DYNA and other Ansys tools. Understanding of Euro-NCAP, G-NCAP, and Bharat N-CAP simulation implementations. Experience in durability, full vehicle crash simulation, dummy positioning, airbag modeling. Strong fundamentals in Structural Mechanics, FEA, Non-Linear Materials, and Dynamics. Strong project management skills, ability to work with cross-functional teams. Preferred Qualifications and Skills MS or PhD in Engineering is preferred. Customer service mindset with a passion for excellence. Ability to travel up to 25%. At Ansys, We Operate as ONE Ansys We fuel new ideas, build relationships, and help each other realize our greatest potential. Our Commitments: Amaze with innovative products and solutions. Make our customers incredibly successful. Act with integrity. Ensure employees thrive and shareholders prosper. Our Values: Adaptability: Be open, welcome what s next. Courage: Move forward passionately. Generosity: Share, listen, serve. Authenticity: Be you, make us stronger. Our Actions: We commit to audacious goals. We work seamlessly as a team. We demonstrate mastery. We deliver outstanding results. Inclusion is at Our Core We believe diverse thinking leads to better outcomes. We are committed to creating a workplace where diversity, inclusion, equity, and belonging thrive. Welcome What s Next in Your Career at Ansys At Ansys, you will work alongside visionary leaders to change the world with innovative technology. We push the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. At Ansys, it s about learning, discovery, and collaboration. It s about the "what s next" as much as the "mission accomplished." It s about forging innovation in an environment built on respect, autonomy, and ethics.

Job/Position Summary Responsibilities Lead and Perform system level testing of Chassis system Brakes, Steer, Suspension in a Hardware In Loop Testing environment Understanding of Chassis features and components involved Mentor and guide team for designing, developing and validation of software applications Collaboration with internal teams and customers within a production program Contribute best practices for System testing and validation Contribute in customer interaction, demonstration and proposal preparation Mandatory Skills: System knowledge of Vehicle Dynamics or Brakes or Suspension system or Steer system Expertise in defining the test strategy for system testing for chassis ECU Expertise in performing Hardware-In-Loop commissioning, testing and analysis Experience in requirement-based testing, diagnostic and fault insertion testing Experience in Test Automation using CAPL/Python for start up sequence, shutdown etc Experience in dSpace/Vector/NI tool chain Experience in Plant model creation and Simulation tools like CarSim, CarMaker Knowledge of CAN, UDS, XCP protocol and Flash bootloader integration Familiarity of functional safety concepts and ISO 26262 is desired Excellent communication, collaboration, analytical and problem-solving skills Familiarity with infrastructure tools like Requirements Management, Change Management and Version Management Requirement ESSENTIAL SKILLS /COMPETENCIES C++ PREFFERED SKILLS /COMPETENCIES C++

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: Qualcomm is at the forefront of technology innovation, constantly pushing the boundaries to enable next-generation experiences and drive digital transformation. As a Hardware Application Engineer at Qualcomm, you will provide technical expertise through product demonstrations, training, and support for the design, debugging, testing, and quality of customer products. You will work closely with cross-functional teams to assess and apply Qualcomm's products, ensuring they meet and exceed customer expectations. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 2+ years of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 1+ year of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR PhD in Electrical/Electronics Engineering, Computer Engineering, or a related field. Key Responsibilities: Engage with customer designs, assist with feature definition, and conduct design reviews. Provide in-depth technical responses to customer inquiries and troubleshoot customer designs. Offer necessary training and technical support to customers. Collaborate with hardware, software, RF systems, and testing teams to deliver comprehensive solutions. Provide hardware design support for customers developing wireless products. Perform block diagram, schematic, placement, and PCB design reviews on customer products. Troubleshoot technical issues and resolve problems through hands-on support. Assist customers in implementing new technology using Qualcomm chipsets and support business teams on new projects. Develop an understanding of RF systems and cellular standards, including GSM, LTE, and 5G. Conduct tests for various technologies such as GSM, C2K, TDSCDMA, WCDMA, LTE, 5G SUB6, and 5G mmW (a strong plus). Desired Skills and Experience: Strong knowledge of cellular technologies like GSM, LTE, and 5G. Understanding of RF component characteristics and behavior. Proficient in problem-solving and analytical skills. Familiarity with PCB CAD tools such as Allegro and PADS for reviewing customer layouts. Experience with digital circuit design, software programming, or power management is a plus. Strong communication skills and the ability to work effectively with cross-functional teams.

Job Title: USS Calibration Engineer / Acoustic Engineer Position Overview: We are seeking a highly skilled USS Calibration Engineer / Acoustic Engineer to join our team. This technical systems role requires a deep understanding of the principles and functioning of ultrasonic sensor technology used in the automotive industry. The role focuses on manipulating automotive-grade ultrasonic sensor settings to achieve precise detection goals. Key Responsibilities: Ultrasonic Sensor Calibration: Calibrate automotive ultrasonic sensors to achieve optimal detection accuracy under varying environmental conditions. Signal Processing and Interpretation: Apply signal processing techniques for the accurate calibration and interpretation of sensor data, ensuring reliable sensor performance. Data Analysis: Analyze data generated by ultrasonic sensors and troubleshoot issues related to sensor calibration and performance. Testing and Troubleshooting: Set up controlled testing environments to calibrate sensors accurately and troubleshoot performance issues. ISO Standards Compliance: Ensure that ultrasonic sensor features meet ISO standards for automotive applications. Essential Skills: Ultrasonic Sensor Technology: In-depth knowledge of ultrasonic sensor technology, including its functioning and application in automotive systems. Sensor Calibration and Performance: Expertise in calibrating sensors and optimizing their performance for various automotive applications. Preferred Skills: Automotive Ultrasonic Features: Experience with automotive ultrasonic features and standards, particularly those related to detection and performance optimization. This position is ideal for candidates with a strong background in ultrasonic sensor technology and sensor calibration, particularly within the automotive industry. If you have a deep understanding of signal processing, data analysis, and calibration techniques, we encourage you to apply!

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Job Overview As a Hardware Engineer at Qualcomm, you'll be part of a dynamic team that plans, designs, optimizes, verifies, and tests cutting-edge electronic systems, including circuits, mechanical systems, digital/analog/RF/optical systems, and more. Your role will focus on SerDes PHY Analog Design, specifically within the BDC SerDes Mixed-Signal Design team. This team is directly involved in delivering next-generation custom PHY designs for SoCs (System on Chips), with a key focus on low-power analog designs to support Qualcomm s wireless products. You ll work with cross-functional teams to meet performance requirements and help bring innovative products to market. Key Responsibilities Analog Circuit Design: Hands-on experience in analog circuit design, working on multiple analog building blocks, including LDO, high-speed TX and RX (Equalizer, Sampler, PI, Deserializer), Bias, and Reference circuits. PLL and Frequency Synthesis: Design and implement Analog and Digital PLLs for frequency synthesis and SerDes applications, including Charge Pumps, Loop Filters, VCO/DCO, PFD/TDC, and high-speed dividers. PLL Loop Dynamics: Model PLL Loop Dynamics, including sources of Jitter (RJ & DJ). Schematic to Post-Layout Verification: Take designs from initial schematic to post-layout verification, and ensure integration sign-off for post-silicon bring-up. Collaboration: Work closely with RTL, DD, PD, DV, and SoC Verification teams to integrate the PHY into SoCs. Minimum Qualifications Educational Background: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 3+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 2+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 1+ year of relevant work experience. Skills & Experience Analog Circuit Design: Hands-on experience with designing analog building blocks such as LDO, high-speed TX/RX, bias, and reference circuits. PLL Design: Strong background in Analog and Digital PLLs for frequency synthesis and SerDes applications. Charge Pump and VCO/DCO: Experience in designing charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers. Jitter and PLL Loop Dynamics: In-depth understanding of PLL loop dynamics, jitter modeling, and frequency synthesis for SerDes systems. Design Verification: Experience in taking designs from schematic through post-layout verification, integration, and post-silicon bring-up. Team Collaboration: Ability to work with cross-functional teams such as RTL, DD, PD, DV, and SoC verification teams to ensure smooth integration.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Job Description You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master s degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor s degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : You must possess a masters degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelors degree with at least 10 years of experience.

Job Description The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams. The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment. Objectives of the position Own and deliver the logic design of Mixed Signal IPs. Continuously drive the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements. Drive area/power of IPs and come up with improvements on IP Area/Power metrics. Critical Decision making on Technical issues. Qualifications The successful candidate will possess a BS, MS degree with a 10-15 years of relevant industry experience. Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation. Experience in the following areas/ skills are desired: DDR Design domain knowledge Strong communicator Git/Perforce/CVS know how Perl/Python/TCL Spyglass Lint, CDC, DFT, VCLP, Logic design using System Verilog Low-power design using UPF and clock gating Multiple clock domain design State machine design Simulation and debug experience using VCS/Verdi Synthesis and speed path debug Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : The successful candidate will possess a BS, MS degree with a 10-15 years of relevant industry experience.

Platform Admin NextGen SIEM Location: Bangalore (Onsite) About ColorTokens At ColorTokens, we re all about helping businesses stay secure and keep running, no matter what cyber chaos hits. Our game-changing Xshield platform stops ransomware and malware from spreading sideways, so companies can keep their critical stuff safe and business uninterrupted. We bring insane visibility into traffic flows between workloads, IoT devices, users basically everything to create super tight security zones that isolate threats fast. We re a Forrester Wave Leader (Q3 2024) for microsegmentation and protect global giants from costly cyber disruptions. Our Culture We love self-starters who bring energy, curiosity, and big ideas. You ll get to own projects, collaborate with passionate teammates, and work on security that actually protects real people from hospitals to cities to entire nations. What You ll Do The Role You ll run and manage our NextGen SIEM platform think Splunk, Sentinel, Exabeam, Stellar Cyber, or similar making sure it s up-to-date, humming smoothly, and packed with the right alerts. Admin & Ops: Install, configure, patch, and keep the SIEM platform running 24/7. Log Boss: Bring in new log sources, troubleshoot ingestion issues, and ensure data is clean and compliant. Rule Maker: Build and tweak detection rules and alerts to catch real threats while cutting down false alarms. Integrate & Automate: Connect SIEM with other security tools and automate incident workflows. Lock It Down: Manage user access, keep the platform secure, and nail compliance requirements. Team Player: Work closely with SOC analysts, threat hunters, and engineers to level up detection and response. Support & Train: Help users get the most from the platform and be the go-to expert when incidents hit. Optimize & Report: Track performance, fix bottlenecks, and share insights to keep the platform sharp. What You Bring Your Skills & Experience 8+ years managing SIEM platforms, especially NextGen ones like Splunk, Sentinel, or Exabeam. Expert in log management, rule creation, and onboarding data from all sorts of sources. Solid scripting skills (Python, PowerShell) to automate and customize workflows. Deep knowledge of log formats (Syslog, JSON, XML), querying languages (KQL, SPL, AQL), and data pipelines. Experience integrating SIEM with EDR, SOAR, NDR, and threat intel platforms. Familiar with security frameworks like MITRE ATT&CK, NIST, or CIS. Bonus points if you know cloud security (AWS, Azure, GCP), machine learning in SIEM, or SOAR tools like Cortex XSOAR or Phantom. Your Credentials Bachelor s degree in Computer Science, InfoSec, or related field (or equivalent experience). Relevant certifications like Splunk Certified Admin, Microsoft Security Operations Analyst, QRadar cert, or CISSP are a major plus. What Success Looks Like Keep SIEM uptime near 100%. Smoothly onboard new log sources and build killer detection use cases. Reduce noise fewer false positives, sharper alerts. Fast, effective fixes when platform issues pop up. Align SIEM capabilities tightly with security and business goals. Qualification : Bachelors degree in Computer Science, InfoSec, or related field (or equivalent experience).

Job Title: Senior Full Stack Engineer Location: Bengaluru, India Employment Type: Full-time Department: Engineering About Commure At Commure, we empower healthcare providers by reducing administrative burdens and enabling more time for patient care. Our suite of software and hardware solutions including AI-powered assistants, RTLS, and workflow automation are used by over 250,000 clinicians across hundreds of care sites. From clinical documentation and staff safety to patient engagement and remote monitoring, we're transforming healthcare through technology. With the industry entering a pivotal phase of AI-driven transformation, Commure is leading the charge. About the Role As a Senior Full Stack Engineer on our Patient Experience Platform team, you'll design and build intuitive, secure, and scalable web applications that enhance patient engagement and streamline healthcare workflows. This is a high-impact role contributing to mission-critical projects with real-world outcomes. Key Responsibilities Design and develop full-stack applications that connect patients and healthcare providers. Lead architectural decisions to scale and evolve the platform. Work closely with product, design, QA, and DevOps teams to gather requirements, define solutions, and deliver features. Optimize system performance, reliability, and observability using logging, monitoring, and tracing tools. Maintain cloud infrastructure using Infrastructure-as-Code (IaC) for reproducibility and reliability. Enhance alerting systems to reduce noise and improve incident response. Develop secure authentication and authorization systems that comply with industry standards. Build and maintain CI/CD pipelines, supporting a robust and compliant deployment process. Participate in on-call rotations and production support. Document processes, configurations, and troubleshooting steps for internal knowledge sharing. Promote a culture of engineering excellence through code reviews, best practices, and mentorship. Qualifications Required Bachelor s or Master s degree in Computer Science, Engineering, or a related field. 3+ years of experience in full-stack software development. Proficiency in: Front-end: TypeScript, React, Next.js Back-end: Python and Node.js Cloud Platforms: AWS, GCP, or Azure CI/CD: GitHub Actions, Google Cloud Build Version Control: Git Containerization: Docker and Kubernetes Monitoring/Logging: Cloud-native tools and observability practices Experience with production incident support and on-call rotations. Strong communication, collaboration, and leadership skills. Preferred Familiarity with serverless architectures and microservices. Knowledge of healthcare data standards like HL7, FHIR, and HIPAA compliance. Experience optimizing performance for large-scale distributed systems. Why Join Commure + Athelas Mission-Driven Impact: Transforming healthcare, the largest sector in the country. Top-Tier Investors: Backed by General Catalyst, Sequoia, Y Combinator, Lux, and more. Exceptional Growth: Combined organizations growing 500% YoY, with Series D funding and strong runway. Comprehensive Benefits: Competitive compensation, flexible PTO, medical/dental/vision insurance, parental leave (location-dependent). Join us and help power the future of patient care. Qualification : Bachelors or Masters degree in Computer Science, Engineering, or a related field.

Machine Learning Engineer - Speech AI (ASR & TTS) Location: Bengaluru, Karnataka, India (On-Site) Department: Engineering Employment Type: Full-Time About Sarvam.ai Sarvam.ai is a pioneering generative AI startup headquartered in Bengaluru, India. We specialize in leading transformative research and development in speech and language technologies. Focused on building state-of-the-art ASR (Automatic Speech Recognition) and TTS (Text-to-Speech) models, particularly for Indic languages, we aim to redefine human-computer interaction with cutting-edge, AI-driven solutions. Join us as we push the boundaries of Speech AI to create inclusive, scalable, and intelligent voice-based applications for diverse communities worldwide. Role Overview We are seeking an experienced Machine Learning Engineer specializing in Speech AI (ASR & TTS). The ideal candidate will work on deep learning-based ASR and TTS models, improving accuracy, efficiency, and multilingual capabilities while deploying them at scale. The role involves developing and optimizing speech recognition and synthesis models with a focus on low-resource languages, real-time inference, and scalability. If you have a passion for speech processing and deep learning, this is a great opportunity to make a significant impact in a rapidly growing field. Key Responsibilities ASR (Automatic Speech Recognition) Develop, train, and optimize speech-to-text models using state-of-the-art architectures like Wav2Vec, Whisper, Conformer, and DeepSpeech. Implement techniques for low-latency ASR inference, including beam search, language model integration, and real-time transcription. Improve speech recognition accuracy for low-resource languages, especially Indic languages, using transfer learning and data augmentation. Optimize ASR pipelines for noise robustness, speaker adaptation, and domain-specific transcription. TTS (Text-to-Speech) Develop and fine-tune neural TTS models such as Tacotron, FastSpeech, VITS, or WaveNet for high-quality, natural-sounding speech synthesis. Implement multilingual and expressive TTS models with prosody and emotion control. Optimize TTS inference for deployment on edge devices, mobile, and cloud platforms. Improve speech synthesis quality through voice cloning, neural vocoders (HiFi-GAN, WaveGlow), and prosody modeling. General Speech AI Responsibilities Benchmark and profile ASR/TTS models to improve latency, efficiency, and deployment performance. Deploy scalable speech AI APIs on AWS, Azure, or GCP for real-world applications. Optimize ASR & TTS models for edge and offline inference. Stay updated with the latest advancements in speech AI, neural vocoders, and real-time inference techniques. Must-Have Qualifications Experience: 2-3 years of experience in speech AI, deep learning, or machine learning, with a focus on ASR & TTS. Education: Bachelor s or Master s degree in Computer Science, AI/ML, Speech Processing, or a related field. ML Frameworks: Proficiency in PyTorch or TensorFlow for training and deploying ASR/TTS models. ASR Expertise: Experience with speech-to-text architectures like Whisper, Wav2Vec, Conformer, or DeepSpeech. TTS Expertise: Experience with speech synthesis models like Tacotron, FastSpeech, or VITS. Speech Signal Processing: Understanding of MFCCs, STFT, phonemes, prosody modeling, and feature extraction. Inference Optimization: Hands-on experience with TensorRT, ONNX, or quantization (INT8, FP16) for ASR/TTS. Cloud & Edge Deployment: Experience deploying speech models on AWS, GCP, or Azure. Preferred Qualifications Experience with speech diarization, speaker recognition, or language modeling for ASR. Familiarity with zero-shot TTS, voice cloning, and multilingual speech modeling. Understanding of CUDA optimization and low-bit quantization for ASR/TTS models. Contributions to open-source speech AI projects or a strong GitHub portfolio showcasing relevant work. Experience with real-time streaming ASR/TTS applications and low-latency inference. Innovative Impact: Work on AI-driven speech solutions that are changing how people interact with technology, especially in low-resource languages. Cutting-Edge Technology: Contribute to the development of state-of-the-art speech AI models in a rapidly advancing field. Collaborative Environment: Work with a team of experts in AI, machine learning, and speech processing, in a startup culture. Growth Opportunities: Sarvam.ai offers exciting career growth in a fast-paced environment with opportunities for personal and professional development. Interested candidates are invited to submit their resume, cover letter, and any relevant project portfolios or GitHub links showcasing their experience in ASR, TTS, or Speech AI. Strong AI-related projects, whether in industry, research, or personal work, will be highly valued. Qualification : Bachelors or Masters degree in Computer Science, AI/ML, Speech Processing, or a related field.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Overview: Collins Aerospace is seeking an experienced Senior Lead Engineer Stress Engineering to join the Aerostructures team. In this critical role, you will leverage your expertise in structural engineering to provide technical solutions for nacelle hardware, ensuring minimal aircraft downtime and compliance with certified type design and airworthiness (FAA/EASA) requirements. You will play a key part in supporting the operational requirements of airline customers and driving solutions in a fast-paced, global environment. Primary Responsibilities: Repair Stress Analysis & Technical Solutions: Perform repair stress analysis and develop analytical methods for medium to complex technical issues, supporting airline operational needs, formal certification reports, and design changes. Engineering Judgments & Repair Solutions: Provide engineering judgments and support margin explorations for nacelle component repairs across various programs, using both metallic and composite structures. Airworthiness Documentation: Prepare airworthiness documents including substantiating analysis and obtain necessary approvals from airworthiness organizations. Customer Communication & Support: Communicate with airline customers to develop rapid technical solutions, collaborating with airframers, engine manufacturers, and suppliers to evaluate and resolve repair data. Collaboration with Cross-functional Teams: Work with the Collins Spares team, Airline/Field Support Managers, and other departments to resolve customer issues effectively. Compliance & Reporting: Ensure compliance with US and country-specific export control requirements. Report to the Aftermarket Technical Services Manager, contributing to the organization s vision of becoming the best aerospace systems company globally. Driving Airline Customer Experience: Work with a diverse global team of engineers, staying at the forefront of improving the airline customer experience. Basic Qualifications: Education: Bachelor s or Master s degree in Mechanical Engineering or Aeronautics. Experience: 6 to 10 years of relevant experience in aerospace structural analysis, including hand analysis and FE tools such as Patran/Nastran. Structural Analysis Expertise: Strong understanding of load paths, load balance, free body diagrams, static and fatigue analyses of metallic and composite aircraft structures. Nacelle Systems Knowledge: Familiarity with nacelle systems for modern aircraft programs (B787, A320Neo, A220, A350). Repair and Inspection Knowledge: Sound knowledge of repair methods for metallic/composite structures and common defects, as well as inspection techniques. Flexible Work Hours: Willingness to work day shifts, weekends, and holidays on rotation as required. Pressure Handling: Ability to work under pressure in a fast-paced environment with short lead times while managing multiple repair tasks. Preferred Qualifications: FEA Expertise: Experience with Patran/Nastran (Sol 101, 106, 111). Customer Support Experience: Previous experience in an aftermarket customer support engineering role. Technical Publications Familiarity: Knowledge of Structural Repair Manual, Component Maintenance Manual, Aircraft Maintenance Manual, Service Bulletins, and Airworthiness Directives. Regulatory Knowledge: Understanding of EASA/FAA requirements and associated repair documentation. About Collins Aerospace: Collins Aerospace is a leader in developing advanced, intelligent solutions for the global aerospace and defense industry. Our Aerostructures business is recognized for its innovative nacelle systems, which improve fuel efficiency, reduce engine noise, and provide critical stopping power during landings. We re continuously evolving to create the next generation of greener, quieter, and more efficient nacelles. Diversity & Inclusion: At Collins Aerospace, we believe diversity drives innovation, and inclusion drives success. We foster a culture that encourages sharing ideas and passion, enabling us to meet the toughest challenges in the aerospace industry and open new paths to possibility. Employee Benefits: Transportation Facility & Meal Coupons Group Term Life Insurance & Health Insurance Group Personal Accident Insurance Employee Scholar Program Work-Life Balance & Car Lease Program National Pension Scheme & Leave Travel Allowance (LTA) Fuel & Maintenance/Driver Wages & Meal Vouchers Ethical & Safety Commitment: Collins Aerospace has a strong commitment to ethics and safety. All positions in India require a background check, which may include a drug screen (only for operations positions). Why Collins Aerospace? At Collins Aerospace, we are redefining aerospace. Join our team of passionate engineers and innovators who are dedicated to creating cutting-edge solutions that push the boundaries of what s possible in air travel. Help us shape the future of aerospace by joining a supportive and inclusive workplace that values growth and creativity. Qualification : Bachelors or Masters degree in Mechanical Engineering or Aeronautics.

Gen AI Support Engineer-2 Location: Bengaluru Experience: 4 7+ years Employment Type: Full-time About Us Exotel is the leading full-stack customer engagement platform and virtual telecom operator for emerging markets. Since its inception in 2011, Exotel has been powering 50 million daily engagements across voice, video, and messaging channels. We provide our unified customer engagement solutions to over 6000 companies globally, including industry leaders like Ola, Swiggy, Flipkart, GoJek, Byjus, Urban Company, HDFC Bank, Zomato, and Oyo. With $100 million in Series D funding and an ARR of $60 million, Exotel is a growth-stage company poised for massive impact. Overview We're seeking a Gen AI Support Engineer-2 to join our team. As an L2 Support Engineer, you will be the highest level of technical escalation within the support organization. Your role will encompass system reliability, platform integrity, troubleshooting mission-critical production issues, and collaborating with engineering teams for architecture feedback. Additionally, you'll help mentor junior engineers and improve operational processes and tools for large-scale environments. If you're passionate about writing clean code with Python and Django and want to contribute to a fast-paced, mission-driven company, this role is for you! Responsibilities Mission-Critical Issue Resolution: Own the resolution of high-priority, time-sensitive production issues. Root Cause Analysis (RCA): Lead RCA reviews and push for systemic improvements in system architecture and processes. Performance Optimization: Identify bottlenecks and propose architectural changes to improve system performance and scalability. Patch Management: Assist in configuring, deploying, and testing patches, releases, and application updates to production environments. SME for Production Systems: Serve as the Subject Matter Expert (SME) for Exotel's production systems and integrations. Cross-Team Collaboration: Work with Delivery, Product, and Engineering teams to influence system design, rollout strategies, and improvement plans. Mentorship: Lead and mentor L1/L2 engineers on troubleshooting best practices and continuous learning. Code Writing & Automation: Write clean, maintainable code for internal tools, scripts, and automation using Python and Django. Support Tooling: Automate recovery workflows and design support tools for proactive monitoring. Operational Excellence: Establish and improve SLAs, monitoring dashboards, alerting systems, and operational runbooks to ensure system reliability. Must Have Skills Backend Development Support: 3+ years of experience in backend development support, production support, or DevOps/SRE roles. Core Technologies: Proficiency in Python, Django, SQL, and troubleshooting in Linux. Web Technologies: Strong understanding of HTML, CSS, JavaScript, and other web technologies. Distributed Systems & Cloud: Experience working with distributed systems, cloud architecture (AWS), Docker, and Kubernetes. Automation: Strong scripting skills with Bash/Python for automation and operational support. CI/CD & Observability: Good understanding of CI/CD, observability tools, and release management workflows. Communication Skills: Excellent communication, leadership, and incident command skills for managing production issues and cross-functional collaboration. Nice to Have Experience with AI-powered systems and machine learning technologies. Familiarity with monitoring systems like Prometheus, Grafana, or Elasticsearch. Knowledge of microservices architectures and scaling distributed systems. Innovative Work: Be at the forefront of cloud-based communications technology and AI-driven customer engagement platforms. Impact: Play a key role in maintaining and optimizing systems that power millions of customer interactions daily. Growth Opportunities: Be part of a fast-growing company with ample learning opportunities and career development. Collaborative Environment: Work in a supportive, inclusive environment where your input and ideas matter. Competitive Benefits: Comprehensive benefits package including health insurance, mental wellness support, and more.

Software Developer C++ Location: Bangalore, Karnataka, India Employment Type: Full-time, Permanent Experience Level: Experienced Professional (6-8 years) Role Overview We are seeking a proactive and skilled Full Stack Developer with deep expertise in C++ to contribute to the development of MR image reconstruction modules integrated with AI. The ideal candidate will actively research and innovate MR reconstruction techniques, improve module performance, and collaborate closely with cross-functional teams to deliver high-quality medical imaging solutions. Key Responsibilities Develop, improve, test, and maintain MR image reconstruction modules. Conduct research to enhance acquisition speed, data extraction, noise/artifact robustness, and overall reconstruction quality. Develop AI inferencing code, prepare data, and support model training activities. Manage code repositories and version control systems such as Git or Azure Repos. Participate actively in design discussions, code reviews, and agile development processes. Troubleshoot and optimize module performance, security, and scalability. Collaborate with product owners and stakeholders to manage backlogs and ensure continuous feature delivery. Required Skills & Qualifications Education: BE/B.Tech/MCA/ME/M.Tech from a recognized institution. Core Expertise: Strong practical experience in C++ development, object-oriented programming, and design patterns. Additional Skills: Python programming experience (advantageous). Knowledge of medical imaging modalities, particularly MRI (preferred). Strong foundation in physics, mathematics, signal processing, linear algebra, probability, and random processes. Understanding of inverse problems, AI, imaging chains, MR reconstruction, and pulse sequences is a plus. Soft Skills: Strong analytical and problem-solving skills, clear communication, and a passion for learning and creative thinking. Tools: Experience with Azure Repos or Git for version control. Experience 6 to 8 years of core development experience with C++. Collaborative work environment fostering professional growth. Challenging projects enhancing technical expertise. Competitive compensation and benefits.

Position: Associate - Logistics Operations Department: Logistics & Linen Operations Location: Bengaluru Employment Type: Full-Time About Laundryheap: Laundryheap is a fast-growing, award-winning startup revolutionizing the laundry and dry cleaning industry. Operating in 14 global markets and expanding rapidly across Europe, Asia, and North America, we re proud to offer one of the quickest services in the business delivering clean clothes within 24 hours. Role Overview: As an Associate in Logistics Operations, you ll play a key role in ensuring the smooth execution of our live delivery operations. Reporting to the Assistant Regional Manager, you will manage real-time driver activity, optimize routes, and provide essential support to our drivers, ensuring operational excellence and customer satisfaction. What You ll Do: 1. Operations & Route Management: Oversee live delivery operations to ensure routes are executed smoothly and orders are completed on time. Provide real-time support to drivers via chat, calls, or internal platforms. Optimize route plans for maximum efficiency and minimal delays. Proactively resolve any on-route issues such as delays, misrouted deliveries, or driver emergencies. 2. Driver Support & Performance: Address inbound driver queries related to payments, schedules, feedback, and general support. Log driver interactions, escalate unresolved issues, and ensure follow-ups are completed. Ensure adequate driver coverage across multiple time zones to meet live operational demand. 3. Operations & Project Support: Contribute to team goals by supporting or initiating projects aimed at streamlining operations. Maintain internal documentation and knowledge bases to ensure up-to-date resources. Monitor KPIs, identify performance bottlenecks, and ensure service level agreements (SLAs) are met. Collaborate with teams across regions (UK, US, Singapore) to ensure smooth cross-functional operations. Required Skills & Experience: Education: Bachelor s degree or equivalent. Experience: 3 5 years in operations, logistics, or support (experience in international environments is a plus). Skills: Strong communication skills, both verbal and written. Ability to handle high-pressure, fast-paced environments with poise. Experience with driver or agent onboarding (calls/video) and live operational support. Proficient in email, chat support tools, and Google Sheets/MS Excel. Flexibility to work night or rotational shifts. Strong stakeholder management skills. A proactive, solution-oriented mindset with a focus on empathy. Preferred Skills: Experience in international support chat (US/EU region preferred). Background in startups, logistics, or last-mile delivery operations. Familiarity with live route planning tools and CRM systems. Analytical mindset with an ability to interpret operational data. Why You Should Join Us: Growth & Impact: Be part of a fast-paced, international startup where your contributions make a tangible impact on day-to-day operations. Global Collaboration: Work alongside teams from across the globe, contributing to innovative solutions and continuous improvement. Career Growth: Enjoy high visibility in a flat team structure and rapid career growth opportunities. Qualification : Bachelors degree or equivalent

Associate Product Designer Job Type: Full-Time Category: Design Location: Bengaluru About Bright Bright is a consumer fintech startup on a mission to help Americans get out of debt and take control of their finances powered by data science, automation, and machine learning. Our mobile app offers a full suite of tools including credit-building, automated debt paydown, smart budgeting, financial planning, and loan refinancing. With over 300,000 users and 100,000+ reviews, Bright is one of the fastest-growing fintech apps in the U.S. Backed by top-tier investors like Sequoia, Falcon Edge, and Hummingbird, we ve raised over $90M in equity and debt funding and are poised to become one of the top 100 financial institutions in the U.S. Built in India for global markets, Bright combines deep domain expertise, world-class design, and cutting-edge technology to deliver life-changing financial outcomes. About the Role We re looking for a Product Designer with a passion for solving real user problems through smart, user-first design. You ll play a key role in shaping the user experience across Bright s core products working closely with product managers, engineers, and other designers to turn insights into innovative, intuitive, and impactful user journeys. You ll be part of a collaborative, fast-paced, high-growth environment where great design is central to product success. What You ll Do Conduct market, user, and competitor research to identify opportunities and user pain points. Translate research findings into actionable ideas, wireframes, and design solutions. Collaborate cross-functionally with senior designers, PMs, and engineers to deliver user-centric and business-aligned experiences. Use design tools like Figma to create high-quality wireframes, mockups, and prototypes. Build interactive prototypes to showcase user flows, product interactions, and animations. Apply usability testing and feedback loops to refine designs. Stay updated on design trends, tools, materials, and techniques relevant to mobile and web UX. Present and advocate for your design ideas with data-backed rationale. What You ll Bring 2 3 years of experience in UI/UX design for mobile apps, web applications, or software products. Strong design craft across interaction, visual, and service design. Proficiency in tools like Figma, Adobe Creative Suite, and prototyping platforms. Hands-on experience across the full design lifecycle: user research, wireframing, prototyping, visual design, and usability testing. A solid understanding of mobile and web design guidelines and best practices. A strong product mindset, with the ability to collaborate effectively with PMs and engineers. A portfolio showcasing creative problem-solving and user-centered design. Passion for working in a dynamic, fast-paced startup environment. What You ll Get Mentorship and training from experienced consumer product leaders. Hands-on experience building products from 0 to 1 in a high-impact, user-focused environment. Deep exposure to cutting-edge work in AI, financial technology, and global product design. The opportunity to build products that make a real difference in people s lives. The skills and foundation to one day become a product founder yourself. At Bright, design isn't just how it looks it's how it works for the user. If you're ready to craft intuitive, elegant, and impactful experiences that help people achieve financial freedom, we d love to meet you.