Physical Design Engineer Sram Jobs in Bengaluru

Position: Data Architect Location: Remote/Hybrid | Bengaluru, IND We're searching for a highly skilled and experienced Data Architect to join our team. If you have a deep understanding of big data technologies and extensive experience with Hadoop, Python, Snowflake, and Databricks, you're the ideal candidate. You'll be responsible for designing, implementing, and managing complex data architectures that support our critical business needs and objectives. What You'll Do: Design & Architecture Leadership: Design scalable and efficient data architecture solutions that meet current and future business data needs. Lead the development of data models, schemas, and databases, ensuring alignment with business requirements. Architect and implement robust data solutions on leading cloud platforms (AWS, Azure, or GCP). Data Management & Governance: Develop and maintain robust data pipelines and ETL processes using Hadoop, Databricks, and other essential tools. Oversee data integration and quality efforts to ensure consistency and reliability across the organization. Implement data governance best practices, focusing on data security, privacy, and compliance. Collaboration & Mentorship: Work closely with data engineers, data scientists, and business stakeholders to translate data requirements into effective technical solutions. Provide technical leadership and mentorship to junior data engineers and architects. Collaborate with cross-functional teams to ensure data solutions align perfectly with overall business goals. Optimization & Innovation: Optimize existing data architectures for peak performance, scalability, and cost-efficiency. Monitor and troubleshoot data systems to ensure high availability and reliability. Continuously evaluate and recommend new tools and technologies to improve our data architecture. What You'll Bring: Experience: 10+ years in data architecture, data engineering, or a related field. Big Data Expertise: Proven experience with Hadoop ecosystems (HDFS, MapReduce, Hive, HBase). Programming Prowess: Strong programming skills in Python for data processing and automation. Data Platform Mastery: Hands-on experience with Snowflake for data warehousing and Databricks for analytics. Cloud Fluency: Extensive experience with cloud platforms (AWS, Azure, GCP) and their data services. Data Modeling: Familiarity with data modeling tools and methodologies. Core Skills: Deep understanding of big data technologies and distributed computing. Strong problem-solving skills to design solutions for complex data challenges. Excellent communication skills, able to explain complex technical concepts clearly to diverse audiences. Proficient in SQL and database performance tuning. Experience with CI/CD pipelines and automation in data environments. Education: Bachelor's degree in Computer Science, Information Technology, or a related field. Preferred Qualifications: Advanced Degree: A Master's degree in a related field. Cloud Certifications: Certifications like AWS Certified Data Analytics, Google Professional Data Engineer, or Microsoft Certified: Azure Data Engineer Associate. Additional Languages: Experience with other programming languages like Java or Scala. Machine Learning Integration: Knowledge of machine learning frameworks and their integration with data pipelines.

Job Title: Robotics Solution Engineer Location: Bengaluru Key Focus Areas: The ideal candidate will have experience and expertise in 40-60% of the following domains: Task Development: Breaking down complex robotic tasks (e.g., pick, orient, place) and designing efficient workflows. Simulation and Validation: Using advanced physics-based simulation tools to model and validate robotic systems and interactions. System Integration: Seamless integration of hardware, software, and sensors tailored to customer environments. Customer-Centric Solutions: Customizing robotic solutions to fit specific customer requirements and constraints. Foundational R&D and ML Development: Supporting research and machine learning algorithm development to enhance robotic perception, autonomy, and decision-making. Roles and Responsibilities: Physics-Based Simulation Development: Develop comprehensive physics-based models for robots, environments, and their interactions. Create and validate dynamic models involving rigid body dynamics, contact physics, material properties, and compliance, especially for multi-arm robotic systems. Build and maintain digital twins of physical robots and real-world environments. Algorithm Development & Implementation: Design, implement, and validate control and motion planning algorithms for multi-arm robots, focusing on manipulation and grasping. Optimize kinematics, dynamics, and force-based control strategies for real-time robotic applications. Support learning-based algorithm implementation for real-time perception and manipulation, including simulation-based testing and validation. Machine Learning Applications: Apply machine learning techniques to robotic perception and decision-making. Implement learning-based algorithms for perception and manipulation tasks. Testing, Validation & Optimization: Develop protocols to validate simulation accuracy by bridging virtual and real-world performance. Create automated test sequences and metrics for robust validation across various scenarios. Analyze simulation results to enhance system performance, safety, and reliability, suggesting design improvements. Collaboration & Cross-Functional Support: Work closely with controls engineers to validate and tune control systems in simulation. Collaborate with algorithm, software, and hardware teams to refine systems and resolve issues. Provide insights from simulation analyses to guide product improvements. Documentation & Reporting: Document simulation approaches, assumptions, and validation outcomes clearly. Prepare detailed reports on system performance, testing results, and optimization opportunities. Skills and Experience: Core Expertise: Advanced physics-based modeling and numerical simulation techniques. Deep understanding of robot kinematics, dynamics, and control theory. Experience with simulation validation and verification methodologies. Sensor modeling for cameras, force/torque sensors, etc. Motion planning algorithm knowledge. Familiarity with machine learning frameworks (PyTorch, TensorFlow) and real-time control implementation. Software & Tools: Experience with physics simulation platforms like NVIDIA Isaac Sim/Omniverse, CoppeliaSim, Mujoco, PyBullet, PhysX, Gazebo, or equivalents. Proficient in Python and C++ for scripting and automation tasks. Comfortable integrating CAD software and managing version control with Git. Engineering & Analysis: Skills in system dynamics modeling and error analysis. Developing test plans and performing root cause analysis. Conducting feasibility studies and model validation. Required Qualifications: Bachelor s or Master s degree in Robotics, Mechanical Engineering, or related fields. Minimum 3 years of professional experience in robotics engineering, with a focus on simulation and modeling. Strong foundation in robot kinematics, dynamics, and control systems. Proficient in Python and C++ programming. Experience with physics engines (PhysX, Bullet, PyBullet) and validating simulation results with real-world data. Preferred Qualifications: Master s or PhD in Robotics, Computer Science, or a related discipline. Hands-on experience with NVIDIA Isaac Sim/Omniverse or similar simulation platforms. Background in computer graphics, sensor modeling, and digital twin technologies. Qualification : Bachelors or Masters degree in Robotics, Mechanical Engineering, or related fields.

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Job Title: Security Engineer - II Location: Bangalore (On-site; full-time) About Locus: At Locus, we are redefining logistics decision-making with deep-tech solutions that drive efficiency, consistency, and transparency across industries like retail and FMCG/CPG. Founded in 2015 by Nishith Rastogi and Geet Garg, Locus has evolved from a women s safety geo-tracking app into a globally recognized logistics optimization platform. Our technology has empowered enterprises such as Unilever and Nestl to execute over a billion deliveries across 30+ countries. Guided by our commitment to innovation and sustainable growth, we transform complex supply chains into strategic growth enablers. Join us at Locus and be part of a team shaping the future of global logistics. Job Overview: Key Responsibilities: Conduct comprehensive threat modeling for applications, cloud infrastructure, and overall systems architecture. Perform secure code reviews and security assessments for web, Android, and iOS applications, with a strong focus on cloud infrastructure security. Proactively identify and mitigate vulnerabilities across platforms, collaborating with development and DevOps teams to implement secure solutions. Automate and streamline security processes, aligning with the principle that Complexity is the enemy of Security. Oversee Vulnerability Management and Patch Management processes, ensuring timely remediation. Design and implement robust security measures and contribute to Red Team activities, including assessments of cloud, network, wireless, physical, and social engineering scenarios. Take ownership of assigned tasks and drive the continuous improvement of security practices across the organization. Assist in setting up and maintaining monitoring systems to identify and respond to potential incidents in real time. Develop custom tools, scripts, and scanners to address unique security challenges and automate repetitive tasks. Provide architectural guidance for securing cloud-based applications and DevOps pipelines. Continuously stay updated on emerging security technologies and techniques, sharing knowledge with the team. Qualifications: 3-5 yrs experienced Sr security engineer. Expertise in cloud security (AWS, Azure, or GCP) with a strong understanding of securing applications and infrastructure in cloud environments. Proficiency in DevOps and DevSecOps practices, including secure CI/CD pipeline integration and automation. Strong knowledge of OWASP and SANS testing methodologies for identifying and mitigating security vulnerabilities. Good understanding of software security weaknesses, architecture vulnerabilities, and mitigation strategies. Hands-on experience in threat modeling, vulnerability assessments, and penetration testing. Proficiency in any scripting language - Python. Experience in developing or customizing tools, scanners, or extenders for specific security needs. Ability to work independently and collaboratively within a team to solve complex security challenges. Experience in implementing security monitoring systems for early incident detection. Strong problem-solving skills and the ability to think creatively to simulate attack scenarios. Certification in security-related fields (e.g., AWS Certified Security, CISSP, CEH, OSCP). Experience with container security and orchestration platforms like Kubernetes and Docker. Knowledge of Infrastructure as Code (IaC) tools like Terraform or CloudFormation. Familiarity with modern DevOps tools (e.g., Jenkins, GitLab, Ansible). Join Locus and become part of a visionary team that is redefining logistics through innovation and smart distribution. We provide competitive compensation, comprehensive benefits, and a collaborative environment where your expertise will drive both your growth and that of the organization. Locus is an equal opportunity employer dedicated to creating a diverse and inclusive workplace.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Senior ATE Test Engineer Manufacturing & Product Engineering Job Description: Intel is seeking a Senior ATE Test Engineer to drive the testability and manufacturability of integrated circuits from feasibility to high-volume production (HVM). The role involves developing and validating test methodologies, debugging functionality and performance issues, and optimizing test processes for yield and cost efficiency. The engineer will work closely with design, process development, fab, assembly, and manufacturing teams to ensure seamless production ramp-up and quality assurance. Key Responsibilities: Test Development & Debugging: Design, develop, and validate testability circuits and test flows for new products. Debug functionality and performance issues to root cause using Automatic Test Equipment (ATE). Interface with design, DFx (Design for Test, Debug, Manufacturing), and product teams to drive test development. Manufacturability & High-Volume Ramp (HVM): Collaborate with fab, assembly, test factories, and quality/reliability teams to enable smooth production ramp-up. Perform ATE device characterization, define datasheet specifications, and conduct yield analysis. Analyze early customer returns and drive test hole closure activities to enhance quality and reliability. Production Test Optimization: Drive test time reduction by analyzing fallout data and balancing product cost optimizations. Implement bin split and die-level cherry-pick (DLCP) strategies to optimize product supply. Ensure manufacturability through process and spec corner analysis to resolve yield issues before mass production. Hardware & Software Development: Develop and debug complex software programs for test conversion and test automation. Create and validate test hardware solutions for production testing. Optimize component production relative to quality and cost constraints. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields. Technical Expertise: ATE Test Engineering: Strong expertise in Automatic Test Equipment (ATE) development and debug. DFT & Test Methodologies: Knowledge of DFT architectures and methodologies including Analog DFT, JTAG, etc. Understanding of test engineering processes and tester debugging techniques. Debugging & Validation: Hands-on experience with design/validation and advanced debugging skills. Expertise in Advantest 93K, Teradyne Ultraflex, J750, and related test platforms. Manufacturing Process & Yield Analysis: Experience in yield analysis, bin splitting, and test time optimization. Ability to analyze process corners and drive manufacturing readiness. Soft Skills: Excellent problem-solving skills, teamwork, and communication. Strong interpersonal and planning skills for cross-functional collaboration. About Intel s Manufacturing & Product Engineering (MPE) Group: The MPE team is responsible for test development across Intel s product segments, contributing to 95% of Intel s revenue. The team delivers pre-production test suites and physical debug capabilities to enable high-quality, high-volume manufacturing. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates. Intel offers a competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

Job Overview: We are seeking a highly skilled Frontline Senior Technical Solutions Engineer with over 5 years of experience to join our Platform Support team. This role is pivotal in delivering exceptional support for our Databricks Data Intelligence platform, addressing complex technical challenges, and ensuring the seamless operation of our data solutions. As a frontline engineer, you will be the primary point of contact for critical issues, working closely with both internal teams and customers to resolve high-impact problems and drive platform improvements. Key Responsibilities: Frontline Support: Serve as the primary technical point of contact for escalated issues related to the Databricks Data Intelligence platform. Provide expert-level troubleshooting, diagnostics, and resolution for complex problems affecting system performance and reliability. Customer Interaction: Engage with customers directly to understand their technical issues and requirements. Provide timely, clear, and actionable solutions to ensure high levels of customer satisfaction. Incident Management: Lead the resolution of high-priority incidents, coordinating with various teams to address and mitigate issues swiftly. Conduct thorough root cause analyses and develop preventive measures to avoid recurrence. Collaboration: Work closely with engineering, product management, and DevOps teams to share insights, identify recurring issues, and drive improvements to the Databricks Data Intelligence platform. Documentation and Knowledge Sharing: Create and maintain detailed documentation on support procedures, known issues, and solutions. Contribute to internal knowledge bases and create training materials to assist other support engineers. Performance Monitoring: Monitor and analyze platform performance metrics to identify potential issues before they impact customers. Implement optimizations and enhancements to improve platform stability and efficiency. Platform Upgrades: Manage and oversee the deployment of Databricks Data Intelligence platform upgrades and patches, ensuring minimal disruption to services and maintaining system integrity. Innovation and Improvement: Stay abreast of industry trends and advancements in Databricks technology. Propose and drive initiatives to enhance platform capabilities and support processes. Customer Feedback: Collect and analyze customer feedback to drive continuous improvement in support processes and platform features. Qualifications: Experience: Minimum of 5 years of hands-on experience in a technical support or engineering role related to Databricks Data Intelligence platform, cloud data platforms, or big data technologies. Technical Skills: A deep understanding of Databricks architecture and Apache Spark, along with experience in cloud platforms like AWS, Azure, or GCP, is essential. Strong capabilities in designing and managing data pipelines, distributed computing are required. Proficiency in Unix/Linux administration, familiarity with DevOps practices, and skills in log analysis and monitoring tools are also crucial for effective troubleshooting and system optimization. Problem-Solving: Demonstrated ability to diagnose and resolve complex technical issues with a strong analytical and methodical approach. Communication: Exceptional verbal and written communication skills, with the ability to effectively convey technical information to both technical and non-technical stakeholders. Customer Focus: Proven experience in managing high-impact customer interactions and ensuring a positive customer experience. Collaboration: Ability to work effectively in a team environment, collaborating with engineering, product, and customer-facing teams. Education: Bachelor s degree in Computer Science, Engineering, or a related field. Advanced degree or relevant certifications are highly desirable. Preferred Skills: Experience with additional big data tools and technologies such as Hadoop, Kafka, or NoSQL databases. Familiarity with automation tools and CI/CD pipelines. Understanding of data governance and compliance requirements. Innovative Environment: Work with cutting-edge technology in a fast-paced, innovative company. Career Growth: Opportunities for professional development and career advancement. Team Culture: Collaborate with a talented and motivated team dedicated to excellence and continuous improvement. About Databricks Databricks is the data and AI company. More than 10,000 organizations worldwide including Comcast, Cond Nast, Grammarly, and over 50% of the Fortune 500 rely on the Databricks Data Intelligence Platform to unify and democratize data, analytics and AI. Databricks is headquartered in San Francisco, with offices around the globe and was founded by the original creators of Lakehouse, Apache Spark , Delta Lake and MLflow. To learn more, follow Databricks on Twitter,LinkedIn and Facebook . Benefits At Databricks, we strive to provide comprehensive benefits and perks that meet the needs of all of our employees. For specific details on the benefits offered in your region, please visithttps://www.mybenefitsnow.com/databricks. Our Commitment to Diversity and Inclusion At Databricks, we are committed to fostering a diverse and inclusive culture where everyone can excel. We take great care to ensure that our hiring practices are inclusive and meet equal employment opportunity standards. Individuals looking for employment at Databricks are considered without regard to age, color, disability, ethnicity, family or marital status, gender identity or expression, language, national origin, physical and mental ability, political affiliation, race, religion, sexual orientation, socio-economic status, veteran status, and other protected characteristics. Compliance If access to export-controlled technology or source code is required for performance of job duties, it is within Employer's discretion whether to apply for a U.S. government license for such positions, and Employer may decline to pr...

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Job Description HPE Global IT enables enterprise innovation through cutting-edge IT solutions. We develop advanced, scalable, and efficient IT systems that simplify business operations and drive global transformation. As a Senior Middleware Engineer, you will play a key role in designing, developing, and maintaining SnapLogic-based middleware solutions. You will work closely with cross-functional teams, providing technical leadership and ensuring seamless data integration across platforms. Your expertise will drive innovation, optimize performance, and enhance system reliability. Key Responsibilities Technical Leadership: Lead cross-functional teams in designing, developing, and optimizing SnapLogic-based middleware solutions. Integration Development: Build and maintain integrations using SnapLogic, Kafka, SFTP, SFDC, and APIs. Performance Optimization: Debug and optimize existing SnapLogic flows for efficiency and scalability. Automation & DevOps: Implement CI/CD pipelines, GIT version control, and automation scripts to streamline deployments. Testing & Agile Methodology: Ensure high-quality delivery by incorporating testing best practices and adhering to Agile methodologies. Stakeholder Collaboration: Work closely with business, IT, and external vendors to deliver seamless integration solutions. Support & Maintenance: Provide ongoing support, troubleshooting, and monitoring of middleware systems, including handling critical MTP or MI support shifts as needed. Required Qualifications Education & Experience: Bachelor s degree in a technical field (or equivalent experience). 12+ years of relevant experience (10+ years with a Master s degree). Technical Skills: Mandatory: 15+ years of IT experience, with 8+ years of hands-on SnapLogic experience. Expertise in debugging and optimizing SnapLogic flows. Strong experience with Kafka integration and utilization in SnapLogic. Solid understanding of CI/CD pipelines, GIT, and automation scripting. Hands-on experience with SFTP, SFDC, and API integrations. Advanced knowledge of modern software development methodologies, tools, and testing frameworks. Preferred: Strong project management and business analysis skills. Experience with vendor and customer management. Strong analytical and problem-solving abilities. Excellent communication, collaboration, and mentoring skills. Highly motivated, proactive, and eager to learn new technologies. Comfortable with working in shifts when required for critical support. Why Join HPE? Health & Wellbeing Comprehensive benefits package supporting physical, financial, and emotional wellness. Career Growth & Learning HPE invests in professional development through mentorship programs, technical training, and cross-functional career opportunities. Diversity & Inclusion We embrace diverse backgrounds and experiences, fostering an inclusive environment where everyone thrives. If you're passionate about middleware integration, innovation, and cutting-edge technology, join us and shape the future of enterprise IT! Qualification : Bachelors degree in a technical field (or equivalent experience).

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

We are seeking a highly skilled and motivated Python and AWS Automation Engineer to join our dynamic team. In this role you will be responsible to automate infrastructure , deployment, and operational tasks using Python/C# and AWS services. Will play a critical part in developing and optimizing our cloud based analytics, streamlining workflows, and enhancing validation efficiency. As a key member of the automation team, expected to work closely with DevOps, engineering, and validation teams to implement scalable and reliable automation solutions for various WiFi features and validation processes. You will also be instrumental in integrating AWS services, creating efficient scripts, and ensuring seamless automation of cloud-based resources and services. Qualifications Key Responsibilities:* Design, develop, and maintain Python/C#-based automation scripts to process data to develop meaningful analytics for validation using AWS resources. * Leverage AWS services (such as Kubernetes) to automate processing for data analytics* Develop automation scripts and libraries for WiFi features* Collaborate with DevOps engineers to integrate automation processes into CI/CD pipelines (e.g., Jenkins)* Monitor and troubleshoot automation workflows to ensure they are running smoothly and efficiently.* Follow guidelines on best practices for cloud automation, scalability, security, and cost optimization in AWS.* Participate in the design and implementation of logging, monitoring, and alerting systems using AWS CloudWatch and other monitoring tools.* Develop and maintain detailed documentation for automation scripts, processes, and AWS configurations.* Ensure adherence to security best practices and compliance standards for cloud-based applications and infrastructure.Required Skills and Qualifications:* Proven hands on experience in Python and C# programming, with a focus on automation and cloud services.* Hands-on experience with AWS services, including Kubernetes* Strong understanding of cloud infrastructure and best practices for automating, scaling, and monitoring.* Experience in integrating automation with CI/CD pipelines and using tools like Jenkins* Knowledge of containerization and orchestration technologies such as Docker, Kubernetes, and ECS.* Hands on experience with automation using rest APIs and UI automation* Familiarity with version control systems (e.g., Git) and Gerrit* Strong problem-solving and troubleshooting skills.* Ability to work independently and collaborate effectively within a cross-functional team.* Excellent written and verbal communication skills.Domain Knowledge1. Hands on Experience in configuring/handling automation setups with different topologies2. WiFi Experience - Usage / Configuring of WiFi sniffer / Attenuator / Access Point will be helpful3. Fair understanding about test engineering skills, Validation Methodologies, Debugging techniquesSoft skills:1. Ability to work independently and collaborate effectively within a cross-functional team.2. Good written and verbal communication skills.3. Quick learning of new technologies4. Stakeholder management Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

Job Description: As a member of the HPE Global IT team, you will play a crucial role in enabling enterprise-wide IT transformation. This includes driving innovative solutions that help simplify operations for customers and supporting the company s consumption-based IT offerings. You will be tasked with leading and developing complex business applications and information systems, while ensuring compliance with technical and business requirements. Key Responsibilities: Solution Design & Implementation: Lead the design and implementation of Identity and Access Management (IAM) and Privileged Access Management (PAM) solutions, with a strong focus on Zero Trust security models. Design and deploy solutions related to CyberArk, Beyond Trust, HashiCorp Vault, and other PAM technologies. Work closely with business units to assess their needs and create comprehensive solutions that align with HPE s security and technical standards. Technical Leadership & Mentorship: Provide technical guidance and mentoring to junior developers and cross-functional teams. Take ownership of the architecture of complex PAM systems, providing expertise in the integration of cloud access models and IAM technologies. Represent the team to external clients, ensuring effective delivery and implementation of solutions. Process Improvement & Innovation: Suggest and implement process improvements based on industry standards and the Zero Trust security framework. Contribute to the strategic direction of the team, providing innovative solutions to complex technical challenges. Lead proof-of-concept (POC) initiatives and manage the deployment of IAM and PAM solutions. Cross-Functional Collaboration: Collaborate with other departments and vendors to troubleshoot, resolve issues, and ensure smooth integration of solutions. Work closely with security teams to ensure PAM solutions meet the organization s security requirements and compliance standards. Documentation & Reporting: Document technical specifications, procedures, and best practices for implementing IAM/PAM solutions. Contribute to architectural reviews and ensure solutions comply with both internal and external security and technical standards. Requirements: Education & Experience: Typically, a Bachelor's degree in a technical field (Computer Science, Information Technology, etc.) or equivalent experience. Minimum of 10 years of relevant experience or 8 years with a Master s degree. Technical Expertise: Advanced knowledge and hands-on experience with modern IAM/PAM platforms (CyberArk, Beyond Trust, HashiCorp Vault, etc.). Experience with Windows Active Directory, Microsoft Azure AD, and REST API programming. Strong understanding of CyberArk Core PAS, Secure Password Vault, Privileged Session Manager, and other PAM components. Skills & Competencies: Excellent communication skills, both written and verbal, with the ability to explain complex technical solutions to non-technical stakeholders. Strong troubleshooting and problem-solving skills, with the ability to manage multiple tasks effectively. Demonstrated experience leading cross-functional teams, with a focus on developing and deploying complex security solutions. Preferred Skills: Experience with cloud security models and the integration of IAM/PAM solutions in cloud environments. Familiarity with Agile methodology and DevOps principles. Relevant certifications in CyberSecurity (CISSP, CISM, etc.) and IAM/PAM technologies. What We Offer: Health & Wellbeing: A comprehensive suite of benefits to support physical, financial, and emotional wellbeing for you and your loved ones. Personal & Professional Development: Career development programs to help you grow in your field or pivot to other areas within the company. We are committed to providing opportunities to help you reach your career goals. At HPE, we believe in the power of diverse teams and flexible work environments. We are committed to fostering an inclusive culture that drives innovation and makes bold moves to redefine what's next. Whether you re working on cutting-edge technology or collaborating with a global team, HPE offers the perfect environment for you to thrive. Qualification : Bachelor's degree or equivalent experience and a minimum of 10 years of related experience or a Master's degree and a minimum of 8 years of experience.