Physical Layer Jobs in Bengaluru

Red Team Hacker / Pen Tester (Onsite, Bangalore) Who We Are ColorTokens We re on a mission to keep businesses running safe and sound even when cyber attackers try to mess things up. Our next-gen platform, ColorTokens Xshield , stops ransomware and malware from spreading sideways inside companies, so critical stuff stays locked down and working. We ve got mad skills in spotting and controlling traffic between all kinds of devices and users from your typical laptops to IoT and medical gadgets. That means we can slice and dice security zones to keep bad actors contained. Forrester calls us a Leader in Microsegmentation (Q3 2024), and we help global companies avoid big $$$ downtime. Our Vibe We re all about hustling with heart. You ll get to own your projects, work with smart teammates, and solve tough problems that actually protect people from kids in hospitals to entire cities. If you re driven, curious, and ready to make a real impact, you ll fit right in. The Gig What You ll Do Run epic red team ops that mimic real-world hackers trying to break in. Hack (ethically!) into networks, apps (web, mobile, APIs), and cloud setups to find weaknesses. Build your own scripts and tools to level up your tests and dodge detection. Team up with defenders (blue team) to boost how we spot and stop attacks. Write clear, no-fluff reports with proof-of-concept hacks and smart fixes. Keep your finger on the pulse of the latest threats and hacker tricks. Jump into purple teaming and adversary simulations to sharpen our edge. Bachelor s in Cybersecurity, CS, or you ve got real-world chops that match. 6+ years deep in red teaming, pentesting across web, APIs, infrastructure, and cloud. Pro with tools like Cobalt Strike, Metasploit, Nessus, Burp Suite, Nmap, and scripting (Python/PowerShell/Bash). Solid grasp of MITRE ATT&CK, threat modeling, and adversary emulation. Know Windows & Linux inside out, Active Directory, plus cloud platforms (AWS, Azure, GCP). Bonus points if you re into social engineering, phishing, or physical security. Skilled at writing docs that actually make sense. Must-have certifications: OSCP is a must; CRTP, OSCE, OSEP, CRTE, GPEN, GXPN are pluses. Qualification : Bachelor's degree in Cybersecurity, Computer Science, or related field (or equivalent experience).

Position: Business Technology Data Engineer Location: Bengaluru, India (Hybrid 3 days onsite) Company: Samsara Technologies India Pvt. Ltd. About Samsara Samsara (NYSE: IOT) is a leader in the Connected Operations Cloud, enabling businesses across industries like transportation, logistics, manufacturing, and field services to harness IoT data for safety, efficiency, and sustainability improvements. Samsara helps organizations digitize physical operations at scale, improving outcomes that impact global infrastructure. Role Overview Samsara is seeking a Business Technology Data Engineer to join its Data & Analytics team within the Business Technology division. In this role, you will design, build, and optimize end-to-end data pipelines and infrastructure for various business-critical systems across CRM, marketing, support, and product platforms. You'll collaborate with teams across the company to build reliable and scalable data solutions that power reporting, automation, and analytics. This hybrid role requires working 3 days per week from the Bengaluru office and 2 days remotely, with working hours aligned to India Standard Time (IST). Key Responsibilities Data Engineering & Platform Development Design and maintain ETL/ELT pipelines that integrate and transform data across business systems. Build scalable data infrastructure to support advanced analytics and real-time reporting needs. Write Python and SQL scripts for data ingestion, transformation, and validation. Data Integration & Enablement Work with diverse data sources: CRM, product telemetry, marketing automation, support ticketing, and order flow systems. Develop and support data lake and data warehouse solutions using Snowflake, Redshift, Databricks, or BigQuery. Ensure interoperability between applications and data layers. Performance & Quality Monitor and optimize pipeline performance, implement observability and alerting. Improve data quality, lineage, and governance across systems. Partner with internal stakeholders (e.g., Sales Ops, Marketing Ops, Analytics) to deliver reliable data products. Minimum Qualifications Bachelor s degree in Computer Science, Data Engineering, or related field. 5+ years of professional experience in data engineering. 3+ years experience building and maintaining end-to-end pipelines in a modern data stack. Strong in SQL and Python. Hands-on experience with: ETL tools: Fivetran, dbt Cloud: AWS (preferred), GCP, or Azure Databases: MySQL, PostgreSQL, Oracle, or similar Data Warehouses: Snowflake, Redshift, BigQuery, Databricks Preferred Qualifications Familiarity with API-based ingestion, serverless architecture (Lambda, API Gateway, SQS, etc.). Experience with monitoring tools (DataDog, CloudWatch, Splunk). Comfortable engaging stakeholders to translate business needs into data solutions. Proficiency in Docker, Kubernetes, or AWS Fargate is a plus. Qualification : Bachelors degree in Computer Science, Data Engineering, or related field

Senior Product Manager Location: Bangalore, Karnataka | Department: Product & Design About the Team At Meesho, Product Management mirrors our rocketship growth. By obsessively understanding customer behavior, we ve carved out a unique e-commerce niche in Tier 2/3/4 towns across Bharat. Our remarkable growth is a testament to how we think about product for our customers those who have barely shopped online but now can thanks to Meesho. Fun Fact: Nearly 7% of India s households shop with us! We operate with a user-first mindset and prioritize execution with rigor to deliver impactful solutions. We focus on problem discovery & delivery, aiming for high impact, not just building features. We believe in having fun while working hard. Whether you're into movies or sports, we have a diverse and energetic team. If a game of badminton after work sounds exciting, this is the place for you! About the Role We are looking for a passionate Senior Product Manager who thrives in a fast-paced start-up environment and enjoys solving high-impact problems. This cross-functional leadership role will have you collaborating with teams across software engineering, UX design, category management, marketing, operations, and finance to bring new products to life. What You Will Do Market & Customer Understanding: Gain deep insights into the e-commerce market and customer/seller needs through landscape analysis, customer interviews, user research, competition analysis, and other techniques. Problem Identification & Prioritization: Use structured approaches to identify and break down problems. Prioritize what needs immediate attention vs. what can be solved later. Solution Discovery: Lead brainstorming sessions to generate the best technology-driven solutions. Collaborate with design, engineering, and business teams to identify and experiment with new ideas using MVPs, prototypes, etc. Product Delivery: Define detailed product requirements and collaborate with cross-functional teams (design, engineering, business, analytics) to bring the product to life. Ensure high product quality through user acceptance testing and dogfooding. Go-to-Market Planning: Create a comprehensive go-to-market plan in partnership with business and marketing stakeholders to maximize product success. Adoption & Metrics: Define and track product metrics. Analyze usage patterns and create action plans to improve product performance. Roadmap Creation: Develop a product roadmap with a 3-month forward-looking view, solving key customer and business problems. Team Leadership: Manage a small team of product analysts and associate product managers, guiding them toward product execution. What You Will Need 7+ years of overall experience, with at least 4+ years in product management in a tech-led company (consumer internet experience preferred) Exceptional problem-solving skills based on first principles thinking Solid understanding of technology, with familiarity in product management processes like A/B experimentation, writing product requirement documents, managing product backlogs, and creating roadmaps About Us Welcome to Meesho, an e-commerce platform transforming businesses across India. We are not just a platform; we re your partner in turning dreams into realities. Our mission is to democratize internet commerce for everyone. Curious about life at Meesho? Our employees are some of the happiest, which has earned us top ratings as an e-commerce workplace on Glassdoor! Our Mission At Meesho, we aim to democratize internet commerce for everyone. We started with the vision to serve the next billion Indian consumers and enable 100 million small businesses to succeed online. We provide sellers with unique benefits such as zero commission and the lowest shipping costs. Currently, more than 1.75 million sellers are growing their businesses through Meesho s extensive customer base and advanced tech infrastructure. Our model caters to underserved customers, providing affordable and relatable merchandise. Through continuous innovation, we are proud to be India s first horizontal e-commerce company. Culture & Total Rewards At Meesho, we focus on cultivating a dynamic, high-performing workplace. Our people-centric culture emphasizes hiring exceptional talent and fostering growth. Our culture is driven by our 11 guiding principles, or "Mantras," which influence everything from recognition to career development. What We Offer: Market-leading compensation a combination of cash and equity-based rewards tailored to the role and individual experience Comprehensive wellness support through the MeeCare Program, focusing on physical, mental, financial, and social well-being Generous medical insurance benefits for employees and their families, including wellness initiatives like telehealth services and gym discounts Work-life balance support with generous leave policies, parental support benefits, retirement plans, and learning assistance Employee recognition personalized gifts, performance-based rewards, and fun workplace activities Additional benefits like salary advance support, relocation assistance, and flexible benefits plans to further enrich your experience

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Manager - EHS (Environment, Health, and Safety) Location: Bangalore Experience: 7-10 years of experience, preferably in the Pharma Industry Industry: Pharmaceutical Education Qualification: Bachelor s/Master s Degree in Engineering, Health, Industrial Management, Science, Environmental Science, or related field. Certifications Required: OSHA, EHS, CPR, CSP, ASP, CIH, HAZWOPER. Fire Department Certification may be preferred. Role Overview We are looking for a skilled and experienced Manager - EHS to join our pharmaceutical company in Bangalore. The role requires a strong understanding of safety and environmental regulations and a proactive approach to managing health, safety, and environmental risks in the workplace. The Manager - EHS will oversee the development, implementation, and management of EHS programs, ensuring compliance with local, state, and central regulations and company policies. Key Responsibilities EHS Program Development & Implementation: Develop and implement safety and environmental programs that create and maintain a safe work environment for employees. Safety Inspections & Audits: Conduct regular safety inspections and audits to ensure compliance with EHS regulations. Investigate accidents/incidents and develop corrective actions to prevent future occurrences. Risk Assessments: Perform risk assessments for new processes, equipment, and materials. Implement measures to mitigate identified risks and ensure the safety of all employees. Employee Safety Training: Conduct regular training for employees on safety procedures, emergency response, and EHS best practices. Regulatory Compliance: Oversee activities related to permits, environmental regulations, and compliance with safety standards. Ensure documentation is up-to-date and regulatory filings are completed accurately. Documentation & Reporting: Maintain and update safety data sheets, compliance records, and incident reports. Prepare and present EHS performance reports to management and stakeholders. Incident & Emergency Response Management: Ensure the development and maintenance of emergency response plans. Conduct regular emergency drills and training sessions to ensure readiness. Vendor & Contractor Compliance: Ensure that vendors and contractors adhere to EHS standards and company policies. Health & Wellness Programs: Develop and implement health and wellness initiatives that promote physical and mental well-being for employees. Continuous Improvement: Monitor compliance with safety standards and enforce safety regulations. Promote initiatives for continuous improvement in safety practices and performance. Insurance & Claims Management: Coordinate with insurance providers for claims management and risk assessments related to employee safety and workplace hazards. Skills & Qualifications EHS Knowledge: In-depth knowledge of EHS regulations and best practices as mandated by local, state, and central regulatory bodies. Analytical & Problem-solving Skills: Strong ability to analyze data, identify issues, and develop solutions to improve safety and environmental practices. Communication Skills: Excellent written and verbal communication skills to effectively report, train, and communicate with employees and management. Software Proficiency: Proficient in Microsoft Office and EHS management software to track, report, and monitor EHS metrics and documentation. Team Player & Independent Worker: Ability to work independently and as part of a team to achieve EHS objectives. Industry Knowledge: Experience evaluating work procedures and processes to align with industry standards and best practices. Travel Requirements: Willingness and ability to travel extensively for inspections, audits, and compliance checks. This is a fantastic opportunity to work with a leading pharmaceutical company where you will have the chance to make a significant impact on employee safety and environmental compliance. You will work in a dynamic, fast-paced environment, focusing on developing and implementing strategies that drive safety, health, and environmental initiatives across the organization. Qualification : Bachelors/Masters Degree in Engineering, Health, Industrial Management, Science, Environmental Science, or related field.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Position Overview: Android Middleware Technical Lead We are looking for a highly skilled Android Middleware Technical Lead with expertise in Android Automotive to join our team. This role involves leading the design and development of next-generation Software-Defined Vehicle (SDV), eCockpit, and Infotainment systems based on Android Automotive. As a technical lead, you will work closely with cross-functional teams to architect and develop innovative solutions for Android-based automotive systems. You should have hands-on experience in areas such as Audio, Connectivity, Media, Graphics, Projection, Bluetooth, or Camera, along with a deep understanding of Android Automotive System and Car Framework. Key Responsibilities: Middleware/Platform Architecture: Lead the design and development of Android Automotive middleware/platform solutions for SDV, eCockpit, and Infotainment systems. Hands-on Development: Take an active role in hands-on development, ensuring the Android Automotive system components are well-architected and meet performance, scalability, and quality standards. Android Automotive Expertise: Apply your deep understanding of Android Automotive, AOSP, and HAL to deliver robust middleware solutions, working closely with cross-functional teams (e.g., hardware, media, connectivity). System Integration: Integrate Android Automotive components with hardware interfaces and third-party systems in a vehicle environment, ensuring seamless interaction between various subsystems. Emulator/Platform Tools: Work with automotive-specific emulators such as Goldfish or Cuttlefish for testing and validation of the Android Automotive systems. Build and Development Systems: Ensure the Android build system is properly managed, maintaining the Android Automotive software stack. Leadership and Mentorship: Provide technical leadership and mentorship to junior engineers, helping them develop solutions and navigate complex technical challenges. Essential Skills: Infotainment Systems: Extensive experience in Infotainment systems and developing software for automotive applications. Android Automotive & AOSP: In-depth knowledge of Android Automotive system architecture, AOSP, and HAL (Hardware Abstraction Layer). Android Middleware Development: Hands-on experience developing and maintaining Android Middleware for automotive platforms. Automotive Systems Expertise: A strong understanding of Automotive systems and industry standards relevant to SDV, eCockpit, and Infotainment systems. Programming Languages: Proficient in Java and Kotlin for Android platform and middleware development. Preferred Skills: C++ Programming: Experience in C++ programming for automotive platforms. Hands-on Emulator Experience: Familiarity with Goldfish or Cuttlefish emulators for testing Android Automotive applications. This is an exciting opportunity for an experienced technical leader with a passion for Android Automotive to shape the future of automotive middleware and platform development. If you have a deep understanding of Android systems, automotive platforms, and enjoy leading cross-functional teams to build high-performance systems, we encourage you to apply!

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

Job Title: Staff Engineer Embedded Software & Methodologies Job Overview: The Architecture and Technology Group (ATG) at Arm plays a critical role in shaping the future of Arm s architecture roadmap. ATG develops industry-leading secure CPU and system architectures, along with technologies that empower our global ecosystem to build innovative products. As part of this, ATG also creates Architecture Compliance Kits (ACK) a crucial product that ensures CPU implementations adhere to Arm architecture standards. These kits are utilized by both internal and external CPU design teams to validate compliance. The ATG team in Bangalore focuses on developing these ACK products. The Methodology Team, specifically, builds embedded software, methodologies, and tools for the latest Arm cores and system IPs. As a Staff Engineer, you will provide technical leadership and guide junior engineers while actively contributing to product development. You will leverage your software engineering expertise to build scalable, high-quality compliance kits used across Arm s internal teams and external partners. Key Responsibilities: Act as a technical expert, driving the design and development of embedded software, boot flows, and methodologies for architectural compliance. Analyze architecture specifications and define software methodologies that meet industry standards. Provide technical direction to the team while mentoring and guiding junior engineers. Collaborate with cross-functional teams to ensure successful and timely delivery of engineering commitments. Continuously enhance development efficiency through improved methodologies, automation, and process enhancements. Communicate delivery status, technical risks, and mitigation plans effectively to stakeholders. Required Skills & Experience: Bachelor s or Master s degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering. 10+ years of experience in embedded software development, boot flows, firmware development, driver development, or low-level operating system driver development for processors. Strong understanding of software engineering principles, along with excellent analytical, problem-solving, and debugging skills. Strong communication skills both verbal and written with the ability to convey technical information effectively across teams. Self-driven, proactive, and able to take ownership of tasks and responsibilities. Preferred Skills: Familiarity with computer architecture fundamentals, especially Arm or x86 architecture. Proficiency in at least one programming language (C or C++) and one scripting language (Perl or Python). Experience with assembly-level programming. Working knowledge of software verification methodologies, embedded software environments, and toolchains (with preference for GNU toolchains). Join a team that thrives on technical excellence and innovation. Whether it s defining cutting-edge architectures, developing advanced cores, or creating custom physical IPs, Arm offers you a platform to push boundaries and make a lasting impact. Qualification : Bachelors or Masters degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: Senior 5G RAN Developer Location: Bengaluru, India Experience: 4 to 8 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline About Tietoevry At Tietoevry, we are at the forefront of 5G innovation, collaborating with global telecom leaders to design and deliver next-generation wireless solutions. Our inclusive, innovation-driven culture offers the perfect platform to work on cutting-edge technologies and contribute to shaping the future of connectivity. Role Overview As a Senior 5G RAN Developer, you will play a critical role in designing, developing, and maintaining 5G NR protocol software components. You will lead the systemization, development, and verification processes for various RAN subsystems, contributing to the development and optimization of gNodeB solutions. This role requires deep technical expertise in 5G RAN Layer 1, 2, and 3, combined with strong architectural insight and a proactive, problem-solving mindset. You will collaborate closely with clients and global teams, provide technical guidance to peers, and help drive innovation in our 5G product portfolio. Key Responsibilities Contribute to product development, maintenance, and delivery, including requirement analysis, high-level design (HLD), low-level design (LLD), coding, and verification of gNodeB. Analyze and prioritize 3GPP features for development across different subsystems. Lead system integration and testing activities in collaboration with client and internal teams. Provide technical leadership by guiding teams on complex design and architectural decisions. Drive continuous performance improvement and ensure quality deliverables. Identify and implement architectural enhancements to optimize product performance and scalability. Document development processes, system designs, and testing outcomes thoroughly. Mandatory Skills & Experience Proven hands-on experience in developing LTE/5G NR MAC Scheduler and Layer-2 protocols. Deep knowledge of 3GPP specifications, particularly across Layer 1, Layer 2, and Layer 3. Strong understanding of Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Experience debugging complex gNodeB issues, including log file analysis and troubleshooting in live environments. Proficiency in C/C++ programming, with experience implementing complex algorithms. Hands-on experience with any of the following features: MAC, RLC, PDCP, Scheduler, Power Control, SPS, TTI Bundling, Link Adaptation, GTP-C, GTP-U In-depth understanding of 3GPP Radio Access Standards, ORAN split architecture, and radio protocol algorithms. Experience in feasibility studies and simulations related to Layer 1/PHY features and packet scheduler algorithms. Experience in software development and systemization for 5G Layer 1/Layer 2/Layer 3 protocols. Strong grasp of Linux OS and optimization techniques using DPDK. Hands-on expertise with version control tools like Git and Gerrit, and project management tools like Jira. Experience working in Agile environments. Preferred Skills Experience with cloud technologies, such as microservices and containers. Exposure to ORAN/Open RAN ecosystems is a plus. Strong analytical mindset with a self-driven and proactive approach. Soft Skills Excellent communication skills, with the ability to work in a dynamic, multicultural environment. Strong collaboration skills to work closely with cross-functional teams across geographies. Ability to mentor and guide junior developers, fostering knowledge sharing within the team. Opportunity to work on cutting-edge 5G technology projects in collaboration with global telecom leaders. A Nordic-inspired culture based on trust, transparency, respect, and low hierarchy. Professional growth through continuous learning, training programs, and exposure to emerging technologies. An inclusive workplace that supports work-life balance. Opportunities for global collaboration, contributing to innovative solutions that shape the future of mobile connectivity. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity fuels innovation. We actively encourage applications from all genders (m/f/d) and candidates from diverse backgrounds. We are committed to fostering an open, inclusive, and inspiring workplace where every individual can thrive. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

At Juniper We believe the network is the greatest vehicle for knowledge, understanding, and human advancement. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people a consistent and dedicated practice we call the Juniper Way. Summary This position is part of the L1 Technical Assistance Center (TAC), supporting Juniper s SRX Firewall customers worldwide. About the Role This role offers a unique opportunity to address a wide range of challenging technical issues for global customers, stay ahead in the rapidly evolving security industry, and continuously develop new skills. You will be part of a collaborative, supportive team, working on diverse tasks that ensure each day is engaging and dynamic. Key Responsibilities Work in a highly dynamic Technical Assistance Center (TAC) environment with a strong focus on customer satisfaction. Quickly diagnose and resolve customer issues to deliver a remarkable customer experience. Serve as a customer advocate, ensuring timely problem resolution while understanding the network environment and business impact. Take full ownership of problem resolution, reproduction, and escalation when necessary. Collaborate within a team-oriented environment, demonstrating flexibility to work on weekends/holidays as required. Continuously learn and adapt to emerging technologies. Mandatory Skills VPN Expertise: Strong knowledge of VPN design, implementation, troubleshooting, and encryption algorithms (e.g., DES, 3DES, MD5, SHA, PKI). Core Networking Knowledge: Thorough understanding of the TCP/IP protocol suite, OSI model, and ability to apply this knowledge to network troubleshooting. Security and Firewall Experience: Proven knowledge of network security, access and perimeter control, vulnerability management, and intrusion detection. Familiarity with SYN flood, replay attacks, and related mitigation techniques. Data Network Experience: Proficiency in LAN/WAN hardware, physical layer infrastructure, data transmission facilities, and interconnecting devices. Troubleshooting Tools: Expertise in using utilities such as lookup, traceroute, ping, netstat, and packet analysis tools like Wireshark and tcpdump. Routing Protocols: Deep understanding of OSPF, BGP, RIP, IPSEC VPN, xDSL, and multicast technologies. Layer 2 Technologies: Strong knowledge of VLANs, VLAN tagging (802.1q), LACP, VLAN trunking, and STP (802.1D and other implementations). Requirements B.E. in Electronics Engineering or Computer Science with 1 3 years of experience in supporting, designing, or implementing IP networks. Hands-on experience in troubleshooting, implementation, and support of large-scale IP networks. Preferred Skills Application Layer Protocols: Working knowledge of FTP, DNS, SNMP, HTTP/HTTPS, LDAP, RADIUS, SMTP, and user authentication mechanisms. Security Products: Experience in providing support for security products such as firewalls, IPS/IDS, and Unified Threat Management (UTM) systems (e.g., URL filtering, antivirus, anti-spam). Operating Systems: Understanding and troubleshooting Windows, Unix, and macOS environments, including related technologies like NIS, NFS, Sun-RPC, and MS-RPC in security-enabled settings. Preferred Certifications JNCIA-JUNOS, JNCIS-Security, JNCIA-FWV, JNCIS-FWV, CCNA, CCNP or equivalent certifications are a strong plus. Join us and be part of the Juniper Way, where we encourage you to: Be Bold Build Trust Deliver Excellence Juniper Networks is an equal-opportunity employer, committed to fostering diversity and inclusivity. We do not discriminate based on race, religion, color, gender, sexual orientation, age, disability, or veteran status. Reasonable accommodation will be provided throughout the hiring process for individuals with disabilities. Qualification : B.E. in Electronics Engineering or Computer Science with 13 years of experience in supporting, designing, or implementing IP networks.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design. Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions. Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Qualification : Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

Job Function: As part of the Wireless R&D HW team in Bangalore, the candidate will contribute to the design and development of next-generation WLAN and micro-Wi-Fi subsystems for connectivity solutions in IoT, hearables, and wearables. This includes: Architecture and micro-architecture development. RTL design and integration. Collaboration with cross-functional teams for design convergence. Responsibilities: Develop micro-architecture and implement design using Verilog/SystemVerilog. Execute digital design (RTL) for complex WLAN subsystems involving multiple clock domains and low-power designs. Integrate and deliver WLAN subsystems to SoC-level designs. Collaborate with verification, SoC design, validation, synthesis, and physical design (PD) teams. Perform tasks such as linting (Spyglass), CDC analysis, synthesis, and simulation. Conduct RTL integration and work closely with DFT and PD teams for design-to-GDS convergence. Analyze tool reports (RDC, CLP, CDC, PrimeTime) and ensure compliance with design standards. Contribute to post-silicon debug and validation, when required. Maintain effective communication with global multi-site teams (US, UK, and India). Create and maintain documentation for design and development processes. Skills and Experience: ASIC Front-End Design: 8+ years of experience in digital ASIC design, with expertise in RTL coding using Verilog, VHDL, or SystemVerilog. Clock Domain Crossing (CDC): Strong experience in handling multiple clock domains and low-power design methodologies. Tool Proficiency: Hands-on experience with Spyglass Lint/CDC checks, DC-Compiler, PrimeTime, synthesis, simulation, etc. Protocols: Familiarity with AHB, AXI, and other standard bus protocols. WLAN/Wireless IP Expertise: Experience in 802.11/Wi-Fi subsystems is a plus. Debugging: Exposure to post-silicon debug and validation is desirable. Collaboration: Ability to work closely with multi-disciplinary teams for holistic design and development. Documentation: Strong documentation and communication skills. Minimum Qualifications: Education: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related fields and 3+ years of relevant experience. OR Master s degree in the same fields and 2+ years of experience. OR Ph.D. and 1+ year of experience. Experience Requirements: Strong background in ASIC front-end design, architecture, and RTL integration. Prior experience in WLAN IP/Sub-system design is a significant advantage. Why Join Qualcomm? Work on cutting-edge technologies like Wi-Fi 6/7/8 and next-gen connectivity solutions. Collaborate with diverse teams across geographies. Opportunity to contribute to groundbreaking innovations shaping the future of connectivity. Be part of an inclusive and forward-thinking culture. Qualification : Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communcations or related field.