RF Radio Frequency Engineering Jobs in Bengaluru
903 Jobs Found
Sr. Member Of Technical Staff - Ui Engineering
Aviatrix Systems
Sr. Member of Technical Staff - UI Engineering Location: Bengaluru Company: Aviatrix Experience: 3+ years About Aviatrix: Aviatrix is a leading cloud network security company trusted by over 500 enterprises globally. We specialize in simplifying and securing multi-cloud environments, providing a unified networking solution built specifically for the cloud. Role Overview: UI Engineering (Co-Pilot Team) We are seeking a Senior UI Engineer to join our Co-Pilot product development team. You will design, develop, and maintain high-quality UI solutions that offer customers seamless access to sophisticated cloud management and network security tools. Technical Requirements Core Competencies: Frontend Stack: Advanced proficiency in TypeScript, React, and Node.js. Web Standards: Expert knowledge of HTML5 and CSS3. API Integration: Solid understanding of REST APIs and asynchronous data handling. Version Control: Professional experience with Git and collaborative workflows. Education: BE/B.Tech in Computer Science or related field (or equivalent practical experience). Nice to Have / Bonus Skills: Design Systems: Experience with MUI (Material UI) or in-house design frameworks. Advanced Protocols: Exposure to gRPC, gRPC-web, and Go. Data Visualization: Familiarity with Elasticsearch and high-scale data dashboards. Cloud Domain: Previous experience in cloud networking or security sectors. Key Responsibilities Feature Development: Build efficient, scalable, and well-tested code for the Aviatrix product suite. UX Partnership: Collaborate with UX designers to translate complex requirements into intuitive user interfaces. System Maintenance: Manage bug fixes, UI enhancements, and participate in on-call rotations for field issues. Continuous Improvement: Contribute to the evolution of development processes and product quality. Benefits & Why Aviatrix Comprehensive Health: Private medical coverage, life assurance, and long-term disability. Financial & Growth: Pension scheme and a dedicated annual wellbeing stipend. Time Off: Generous holiday allowance and a flexible approach to work-life balance. Inclusivity: We value unique journeys if you are excited by the role, we encourage you to apply regardless of a perfect "checklist" match.
Engineering Manager
Talview
Engineering Manager Location: Bengaluru Hiring is still shaped by outdated processes manual screening, unconscious bias, and delayed feedback. Talview is transforming this with AI that actually works. We build GenAI-powered hiring and assessment platforms that make recruitment faster, fairer, and scalable. Our AI Products Alvy: The world s first AI Proctoring Agent for intelligent global exam monitoring. Ivy: A conversational AI Interviewer delivering unbiased first-round assessments. Impact: 10M+ assessments delivered across 120+ countries. The Role We re looking for an Engineering Manager to lead high-performing teams, drive architectural excellence, and deliver scalable products globally. You ll guide engineers across backend, frontend, QA, and DevOps, while partnering closely with Product and Design to drive meaningful outcomes. What You ll Do Leadership: Lead, mentor, and grow cross-functional engineering teams. Architecture: Own architecture and system design for cloud-native, distributed systems. Excellence: Champion code reviews, testing, automation, and security practices. Operations: Strengthen engineering processes including CI/CD, observability, and monitoring. Delivery: Own delivery outcomes, sprint planning, and team performance. People: Conduct 1:1s, performance reviews, and career development planning. You Might Be a Fit If You Have Required Qualifications: 6+ years of overall engineering experience; 5+ years in backend (Node.js, Go, or Python). 2+ years with Docker, Kubernetes, and public cloud platforms (AWS, GCP, or Azure). 2+ years in Agile delivery environments (Scrum, Squads, or Chapters). 1+ year experience managing a team of 4+ engineers. Deep understanding of cloud monitoring, deployments, and cost optimization. Bonus Points For: Building SaaS or high-scale distributed systems. Experience with AI-assisted coding tools (Cursor, Windsurf, Codex, etc.). Strong system design and architectural fundamentals. Our Culture: The 5Cs We are guided by Collaboration, Commitment, Credence (trust), Customer-centricity, and Candor. We work together, ship quality, and communicate openly. What You Get Competitive compensation and best-in-class hardware. 5-day work week with flexibility. Monthly team lunches and annual offsites. Accelerated growth in a fast-scaling product organization.
Engineering Manager, Collections
Postman
Engineering Manager, Collections Location: Bengaluru Work Type: Full-Time About Postman Postman is the world s leading API platform, enabling over 40 million developers and 500,000 organizations, including 98% of the Fortune 500, to design, test, and collaborate on APIs efficiently. Founded in Bengaluru and headquartered in San Francisco, Postman simplifies the API lifecycle to help teams build better APIs, faster. The Opportunity The Collections team is at the heart of Postman s platform, enabling seamless API collaboration for millions of users. We manage tier-0/1 critical systems handling ~21M requests daily, supporting pillars like API development, testing, prototyping, discovery, distribution, and change management. We are seeking an experienced Engineering Manager to take Collections to the next level leading technical strategy, scaling systems, improving user experience, and growing a high-performing team. This role combines technical leadership, people management, and product vision, directly impacting Postman s growth and user engagement goals. Key Responsibilities Leadership & Team Development Grow and mentor engineers, aligning career growth with business goals. Participate in recruiting, hiring, and onboarding top engineering talent. Define and measure team performance with clear OKRs and real-time feedback. Technical & Strategic Ownership Drive engineering strategy and roadmap for the Collections team. Lead design and code reviews, ensuring high standards across frontend and backend systems. Ensure product reliability, performance, security, and 99.99% availability. Prioritize multi-quarter roadmaps while balancing technical constraints and business needs. Collaboration & Cross-functional Impact Partner with Product, Design, and Engineering teams to deliver a unified, high-quality API collaboration experience. Champion operational and customer excellence through incident management, performance monitoring, and UX issue resolution. About You Experience & Skills Bachelor s degree in Computer Science or equivalent practical experience. 7+ years of software development experience (C, C++, Java, JavaScript, NodeJS). 3+ years in technical leadership roles building impactful products. 2+ years in people management. Experience with microservices architecture and scalable systems. Exceptional written, verbal communication, and stakeholder management skills. Empathetic, collaborative, and committed to creating a positive team culture. Nice-to-Have Experience building customer-focused products at scale. Familiarity with standardizing engineering processes in a growing organization. Flexible hybrid work model with a collaborative and inclusive team. Full medical coverage, flexible PTO, wellness reimbursement, and monthly lunch stipend. Wellness programs, team-building events, and donation-matching initiatives. Opportunities for growth, ownership, and making a measurable impact on Postman s global platform. Our Values Curiosity: Explore boldly and innovate. Transparency: Communicate openly about successes and failures. Focus: Align work with Postman s larger vision. Inclusion: Every team member s voice matters. Excellence: Deliver high-quality products and experiences. Qualification : Bachelors degree in Computer Science or equivalent practical experience
Data Engineering Lead
Fampay
Data Engineering Lead Bengaluru | Engineering | Full-Time About Fam (formerly FamPay) Fam is India s first payments app designed for everyone aged 11 and above. FamApp enables seamless online and offline payments through UPI and FamCard. Our mission is to empower over **250 million young Indians** to start their financial journey early, becoming financially aware and confident. Founded in 2019 by IIT Roorkee alumni, Fam is backed by top-tier investors including Elevation Capital, Y-Combinator, Peak XV (Sequoia Capital India), Venture Highway, and angels like Kunal Shah and Amrish Rao. About the Role We re looking for a visionary **Data Engineering Lead** to take **end-to-end ownership** of Fam s data ecosystem from data ingestion and storage to processing and delivering actionable insights. You ll **define the data strategy and architecture** that supports both batch and **real-time** use cases, ensuring scalability, reliability, and governance across the organization. You will be instrumental in enabling accurate, complete, and trusted data flow that powers business intelligence, analytics, and product decision-making. This role involves **leadership, strategic thinking**, and hands-on problem solving. What You ll Do Own the full data lifecycle: ingestion, organization, storage, processing, and presentation. Define and execute **data architecture and strategy** aligned with operational and analytical goals. Build **scalable, reliable, and observable data systems** supporting batch and near real-time processing. Ensure **data quality, governance, and compliance**, proactively resolving discrepancies. Collaborate with product, engineering, and business teams to define, track, and optimize key metrics. Anticipate data-related challenges and implement preventive solutions. Lead, mentor, and grow the data engineering team, fostering innovation and accountability. Must-Haves 10+ years experience in data engineering, including proven leadership of teams or projects. Expertise designing, building, and scaling end-to-end data pipelines and systems. Deep understanding of the data lifecycle, from ingestion through business reporting. Strong communication skills and ability to collaborate across technical and business teams. Solid knowledge of **data governance, quality assurance, and compliance standards**. Experience with observability and proactive monitoring for data systems. Proficiency in Python and SQL; familiarity with Scala or Java. Hands-on experience with streaming and batch data frameworks. Experience designing large-scale data lakes and warehouses with best practices for schema evolution and partitioning. Strong background with **cloud platforms (AWS, GCP, or Azure)**. Fintech or regulated industry experience is a plus. Good to Have Fintech-specific data experience, including regulatory compliance and reporting. Deployment experience with **real-time analytics** and event-driven architectures. Familiarity with containerization and infrastructure tools like Docker, Kubernetes, Terraform. Knowledge of data observability tools (Monte Carlo, Databand, etc.). Exposure to **ML pipelines** and model deployment. Solve challenging problems at the intersection of big data, real-time processing, and fintech. Lead impactful data initiatives at a rapidly growing startup. Collaborate with a world-class team of engineers, data scientists, and product leaders. Competitive compensation, equity, and benefits. Clear career growth opportunities in leadership and innovation. Perks That Go Beyond the Paycheck Relocation assistance for a smooth move. Free office meals (lunch & dinner). Generous leave policies (birthday, period, parental support, and more). Salary advances and loan policies for financial support. Quarterly rewards, recognition, and referral incentives. Access to the latest gadgets and tools. Comprehensive health insurance with mental health support. Tax benefits like food coupons, phone allowances, and leasing options. Retirement benefits including PF contribution, leave encashment, and gratuity. About FamApp FamApp focuses on financial inclusion for the next generation by offering UPI and card payments to users aged 11+. Our flagship product, FamX, integrates UPI and card payments seamlessly, helping users manage, save, and learn about their finances effortlessly. With over **10 million users**, FamApp is revolutionizing how young Indians transact eliminating the need to carry cash and offering customizable FamX cards with personal doodles for a fun, unique payment experience. Join Our Dynamic Team At Fam, we foster a people-first culture with flexible work schedules, generous leave, comprehensive health benefits, and mental health support. You ll be part of a passionate, talented, and fun team shaping the future of fintech for India s youth.
Principal Electronics Engineer - Embedded Hardware
Ultraviolette Automotive
Job Title: Principal Electronics Engineer Embedded Hardware Location: Bengaluru Experience: 8 14 years Industry: Automotive / EV / Manufacturing Employment Type: Full-time About Ultraviolette Join the Charge. Create the Future. At Ultraviolette, we are more than just a company we re a movement that s reshaping the future of electric mobility. From building India s fastest electric motorcycle to designing the world s most advanced electric scooter, we thrive on pushing the boundaries of what s possible. We are a team of engineers, designers, and trailblazers united by a passion to craft machines that are sustainable, intelligent, and exhilarating. Every bolt, every line of code, and every component is designed with a singular mission: to accelerate the global shift toward next-generation mobility. Role Overview We are looking for a Principal / Lead Electronics Engineer Embedded Hardware to take ownership of vehicle electronics architecture, embedded systems design, diagnostics, and system-level validation for our next-gen electric vehicles. In this role, you will be at the forefront of developing high-performance electronic control units, telematics, and connected systems for future-ready vehicles. You will drive architecture decisions, system integration, and compliance, working alongside cross-functional teams to bring innovation from concept to the street. Key Responsibilities 1. Vehicle Electronics Architecture Design and bring to production electronic hardware including ECUs, display clusters, and telematics modules. Develop high-speed embedded designs with RF, sensor integration, and communication interfaces (CAN, LIN, UART, SPI, I2C). Create and maintain system schematics, architecture documentation, and interface definitions. 2. Embedded Hardware Design Develop embedded platforms with high-performance microcontrollers/processors to support vision systems, graphics, radar/LiDAR, audio, and OS-based applications. Architect and validate connected systems involving GNSS, LTE, BLE, Wi-Fi. Lead the design and integration of vehicle subsystems like lighting, clusters, IMUs, and more. Collaborate closely with firmware teams on hardware-software integration, bootloaders, and OTA functionality. 3. Diagnostics & Compliance Implement UDS-based diagnostics, fault logging systems, and service tools. Ensure compliance with AIS-004, ISO 26262, and other automotive design standards. 4. Testing & Validation Define and execute component-level and vehicle-level validation test plans. Utilize tools like Vector CANoe, CANalyzer, ETAS INCA, oscilloscopes, and spectrum/network analyzers for debugging and validation. 5. Cross-functional Collaboration Partner with teams across mechanical, software, UX, powertrain, and wire harness for holistic system integration. Work with mobile and cloud teams to enable real-time data streaming, diagnostics, and OTA updates. Actively contribute in design reviews, DFMEAs, and root cause analyses of field issues. Required Qualifications & Skills B.E. / M.E. / B.Tech / M.Tech in Electronics, Electrical, Mechatronics, or related disciplines. 8+ years of embedded hardware design experience, preferably in 2W/EV/automotive domain. Strong understanding of embedded C and scripting languages (e.g., Python, MATLAB, Octave). Experience with circuit simulation tools (e.g., PSPICE, LTSPICE, SIMPLIS, Simetrix). Hands-on expertise in RF design, signal/power integrity, EMI/EMC compliant layouts. Proficiency in PCB design tools (e.g., OrCAD, Altium, Mentor Graphics). Demonstrated experience in designing systems with multi-core processors, memory chips, SoMs, and high-speed interfaces (USB, Ethernet, LVDS, MIPI). Deep knowledge of embedded communication protocols (CAN, LIN, SPI, UART, I2C). Strong debugging and problem-solving skills in hardware validation and field testing. Nice to Have Hands-on experience in vehicle electronics development for 2W, 4W, or electric vehicles. Familiarity with DFT/DFA (Design for Testing/Assembly) methodologies. Experience with manufacturing and compliance testing for embedded hardware. Background in developing connected vehicle ecosystems with OTA capabilities. Passionate about emerging technologies in mobility, EVs, and embedded systems. Be part of India s electric mobility revolution where engineering meets adrenaline. Work on world-class technologies that are pushing global boundaries. Join a culture that encourages innovation, learning, and ownership. Collaborate with passionate teams building next-gen mobility experiences. Qualification : B.E. / M.E. / B.Tech / M.Tech in Electronics, Electrical, Mechatronics, or related disciplines
Senior System Engineer
Accord Software & Systems
Job Title: Senior System Engineer Job Type: Full-Time Location: Bangalore Experience Required: 5 10 Years Education: B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation Job Summary: We are looking for an experienced and technically proficient Senior System Engineer to lead the design, analysis, and testing of RF systems. The ideal candidate will have a strong background in RF principles, hardware testing, and system-level design, along with the capability to manage projects and mentor junior engineers. Key Responsibilities: Design, develop, and analyze RF systems from concept through to production. Perform system-level analysis including link budgets, acquisition, and tracking especially in applications like GPS satellite systems. Use simulation tools to model and optimize RF system performance. Conduct testing using RF test equipment such as signal generators, oscilloscopes, and spectrum analyzers. Lead and support hardware qualification processes, including environmental testing. Ensure adherence to hardware lifecycle quality processes. Collaborate with cross-functional teams across hardware, software, and testing domains. Mentor junior engineers and assist in technical project management and execution. Required Skills & Qualifications: Strong foundation in RF design principles and system architecture. Hands-on experience with RF simulation tools and measurement equipment. Knowledge of GPS systems including acquisition and tracking techniques. Familiarity with environmental and qualification testing for hardware components. Understanding of hardware lifecycle and quality standards. Proven ability to mentor and guide junior team members. Strong analytical, documentation, and communication skills. Qualification : B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation
System Engineer
Accord Software & Systems
Job Title: System Engineer Job Type: Full-Time Location: Bangalore Experience Required: 2 3 Years Education: B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation Job Summary: We are looking for a motivated System Engineer with a foundational understanding of RF systems and hands-on experience working with electronic hardware. The ideal candidate should be capable of interpreting schematics and working with standard lab equipment to support system integration and validation tasks. Key Responsibilities: Assist in the design, testing, and validation of RF-based systems. Interpret and analyze hardware block diagrams and schematics. Support schematic reviews and perform basic schematic design activities. Operate and utilize test equipment such as spectrum analyzers, multi-meters, and oscilloscopes. Work on basic concepts of acquisition and tracking, especially in systems like GPS satellite receivers. Collaborate with the hardware and system teams to support integration, debugging, and testing activities. Required Skills & Qualifications: Educational background in ECE, EEE, or Instrumentation. Basic knowledge of RF systems and principles. Familiarity with electronic schematics and hardware block diagrams. Ability to use electronic test instruments (Spectrum Analyzer, Oscilloscope, Multi-Meter). Understanding of GPS signal acquisition and tracking is a plus. Good communication skills and willingness to learn and grow in a technical environment. Qualification : B.E / B.Tech in Electronics & Communication (ECE), Electrical & Electronics (EEE), or Instrumentation
Sales Engineer GNSS Modules
Accord Software & Systems
Job Title: Sales Engineer GNSS Modules Job Type: Full-Time Location: Bangalore Experience Required: 3 5 Years Education Qualification: B.E / B.Tech in Electronics & Communication (ECE) or Electrical & Electronics (EEE) Job Summary: We are seeking a dynamic and driven Sales Engineer with a strong background in GNSS modules, electronic components, or embedded solutions. The ideal candidate will be responsible for driving sales growth, managing customer relationships, and collaborating with both internal and external stakeholders to ensure successful product delivery and support. Key Responsibilities: Lead sales efforts for GNSS modules, from lead generation and customer acquisition to closure and post-sales support. Develop and manage relationships with key stakeholders in customer organizations including engineering, procurement, and finance teams. Identify and pursue new business opportunities in the embedded systems, IoT, electronics, and telecom segments. Work closely with internal manufacturing, logistics, and finance teams to ensure timely and efficient product delivery. Conduct technical presentations, product demos, and commercial negotiations to convert leads into long-term customers. Monitor market trends, customer needs, and competitor activity to identify growth opportunities. Ensure accurate sales forecasting, pipeline management, and regular reporting to management. Meet or exceed sales targets with a proactive, disciplined, and strategic sales approach. Required Skills & Qualifications: Proven experience in technical sales of GNSS modules, electronic components, or related embedded/IoT solutions. Strong understanding of B2B sales cycles, especially in electronics, telecom, or embedded systems domains. Excellent communication, presentation, and negotiation skills. Ability to build and maintain long-term client relationships. Self-motivated, target-driven, and result-oriented with a focus on customer success. Highly organized with a structured and disciplined approach to sales execution. Qualification : B.E / B.Tech in Electronics & Communication (ECE) or Electrical & Electronics (EEE)
Lead - Satellite Design & Development
Larsen & Toubro (l&t)
Job Title: Lead Satellite Design & Development Location: Bengaluru Experience Required: 10 to 15 years Minimum Qualification: Bachelor s or Master s degree in Engineering (BE/BTech/ME/MTech) or Science (MSc) Specialization in Aerospace, Mechanical, Electronics, or Systems Engineering preferred Key Skills Satellite Systems Engineering System Architecture & Integration Flight Mechanics & Control Systems NX and Concept Design Tools Project & Resource Management Systems Engineering Lifecycle (V&V, Risk, Interfaces) Strategic & Technical Leadership Stakeholder Management Job Summary We are seeking a seasoned and visionary Lead Satellite Design & Development to lead end-to-end execution of satellite programs. The role requires deep technical expertise, hands-on project management skills, and a proven ability to lead multidisciplinary engineering teams. The ideal candidate will be instrumental in shaping system architecture, ensuring technical excellence, and aligning with organizational goals in the dynamic field of space systems. Key Responsibilities Team Leadership Lead and mentor a multi-functional engineering team across systems, mechanical, electronics, aerospace, software, and reliability disciplines. Foster a collaborative, innovation-driven work culture aligned with project objectives and company strategy. Project Management Manage full project lifecycle: from concept development through design, integration, testing, and deployment. Define project plans, budgets, schedules, and resource allocations using Agile, Waterfall, or hybrid methodologies. Conduct regular project reviews to monitor performance, identify risks, and implement mitigation strategies. Systems Engineering & Integration Drive system architecture and engineering processes: requirements definition, interface control, verification & validation, and risk management. Balance trade-offs between performance, cost, risk, and reliability throughout the development lifecycle. Ensure all engineering documentation is maintained in line with industry standards and internal processes. Quality Assurance & Risk Management Champion adherence to quality benchmarks and reliability targets. Develop and enforce comprehensive risk mitigation plans across design, development, and integration phases. Stakeholder Engagement Interface with internal teams (R&D, QA, Production, Finance, Executive Leadership) for cross-functional alignment. Engage external partners clients, suppliers, regulators to ensure compliance, clarity, and project alignment. Represent the organization in technical forums, industry panels, and client briefings. Innovation & Continuous Improvement Drive adoption of emerging technologies and design innovations to strengthen competitive edge. Lead process optimization initiatives to improve development efficiency, product quality, and team performance. Preferred Qualifications & Experience Proven leadership in full-cycle satellite or satellite bus development from mission planning and architecture to launch and mission control. In-depth knowledge of satellite sub-systems and technology providers. Familiarity with international standards and best practices in satellite design and development. Strong strategic acumen in planning, budgeting, and resource management for complex aerospace projects. Qualification : Bachelors or Masters degree in Engineering (BE/BTech/ME/MTech) or Science (MSc)
Application Engineer, IP&E
Einfochips
Position: Application Engineer, IP&E Job Overview: We are looking for an Application Engineer specializing in IP&E (Interconnect, Passive, and Electro-Mechanical systems) to provide advanced engineering design services and support to our regional engineering team. In this role, you will align with suppliers and technology strategies to maximize business growth while supporting product development across a range of industries. Your expertise will help guide the team in identifying and promoting components such as connectors, terminal blocks, headers, and high-power connectors. Key Responsibilities: Provide advanced engineering design support for interconnects, passive devices, and electro-mechanical systems, collaborating with suppliers to maximize business growth. Identify and recommend component applications tailored to specific technologies and industries. Offer hardware support by identifying, cross-referencing, and promoting components like connectors, terminal blocks, headers, sockets, EV connectors, and high-power/high-speed connectors for product development. Ensure all designs comply with relevant industry standards and customer specifications. Leverage strong technical knowledge of interconnects, passives, and electro-mechanical systems to support the regional engineering team. Stay up to date with current technology trends through technical and sales training. Develop product performance specifications and product development roadmaps. Ensure the accurate documentation of engineering designs and solutions for future reference. What We Are Looking For: Bachelor s Degree or higher in Mechanical, Electrical Engineering, or a related field. At least 7 years of experience in IP&E component applications and product development. Proven experience working in R&D environments and product design processes. Knowledge of interconnect technologies such as board-to-board, wire-to-board, connectors, cables, terminal blocks, headers, sockets, backplane systems, flex circuits, and high-speed or high-density systems. Experience with innovative cable products and cable assembly products. Excellent problem-solving skills with a keen attention to detail. Strong communication and collaboration skills to work effectively with internal teams and customers. A passion for innovation and a commitment to delivering high-quality engineering solutions. What s In It For You: Training and professional development opportunities. Performance coaching and growth support. Opportunity to work with a fun and supportive team. Be part of a strong and growing company. Community involvement opportunities. About Arrow: Arrow Electronics, Inc. (NYSE: ARW), a Fortune 133 company and one of Fortune Magazine s Most Admired Companies, is a global leader in technology solutions. With 2023 sales of USD $33.11 billion, Arrow develops innovative technology solutions that improve business and daily life. Our broad portfolio helps customers create, make, and manage forward-thinking products that make technology accessible to more people. Location: Bangalore, India Employment Type: Full-time Job Category: Engineering and Technology Qualification : Bachelors Degree or higher in Mechanical, Electrical Engineering, or a related field.
Rf Hw Engineer, Senior
Qualcomm
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: Qualcomm is at the forefront of technology innovation, constantly pushing the boundaries to enable next-generation experiences and drive digital transformation. As a Hardware Application Engineer at Qualcomm, you will provide technical expertise through product demonstrations, training, and support for the design, debugging, testing, and quality of customer products. You will work closely with cross-functional teams to assess and apply Qualcomm's products, ensuring they meet and exceed customer expectations. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 2+ years of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field, with 1+ year of experience in Hardware Applications Engineering, Hardware Design, or a related field. OR PhD in Electrical/Electronics Engineering, Computer Engineering, or a related field. Key Responsibilities: Engage with customer designs, assist with feature definition, and conduct design reviews. Provide in-depth technical responses to customer inquiries and troubleshoot customer designs. Offer necessary training and technical support to customers. Collaborate with hardware, software, RF systems, and testing teams to deliver comprehensive solutions. Provide hardware design support for customers developing wireless products. Perform block diagram, schematic, placement, and PCB design reviews on customer products. Troubleshoot technical issues and resolve problems through hands-on support. Assist customers in implementing new technology using Qualcomm chipsets and support business teams on new projects. Develop an understanding of RF systems and cellular standards, including GSM, LTE, and 5G. Conduct tests for various technologies such as GSM, C2K, TDSCDMA, WCDMA, LTE, 5G SUB6, and 5G mmW (a strong plus). Desired Skills and Experience: Strong knowledge of cellular technologies like GSM, LTE, and 5G. Understanding of RF component characteristics and behavior. Proficient in problem-solving and analytical skills. Familiarity with PCB CAD tools such as Allegro and PADS for reviewing customer layouts. Experience with digital circuit design, software programming, or power management is a plus. Strong communication skills and the ability to work effectively with cross-functional teams.
Junior 5g Ran Developer
Tietoevry
Job Title: Junior 5G RAN Developer Location: Bengaluru, India Experience: 1 to 4 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or equivalent. About Tietoevry At Tietoevry, we are committed to driving innovation in Wireless Telecommunications and shaping the future of connectivity. As part of our global R&D initiatives, we collaborate with industry leaders to develop state-of-the-art solutions for 5G networks. We foster an inclusive and collaborative environment, offering opportunities for growth, learning, and cutting-edge development in next-generation technologies. Role Overview As a Junior 5G RAN Developer, you will play a key role in the design, development, and testing of software components across multiple layers of the 5G NR protocol stack. You will work on gNodeB development, collaborating with global teams in an agile environment, delivering high-performance solutions for future wireless networks. Key Responsibilities Contribute to the development and verification of features within the 5G NR Radio Access Network (RAN), focusing on gNodeB. Develop Low-Level Design (LLD) and implement new features for 5G RAN software, ensuring compliance with 3GPP standards. Collaborate with cross-functional teams, including system integrators, to ensure smooth integration across different RAN components. Analyze and resolve complex issues, including log file analysis and debugging in live environments. Continuously work towards improving system performance and delivering high-quality solutions. Document development processes, test cases, and outcomes comprehensively for future reference. Mandatory Skills & Experience Hands-on experience in LTE/5G NR Layer-1, Layer-2, and Layer-3 protocol software development. Expertise in 3GPP specifications, particularly related to Layer-1, Layer-2, and Layer-3 protocols. Strong understanding of MAC Scheduler and Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Proficiency in C/C++ programming, with experience in software debugging and troubleshooting complex RAN-related issues. Familiarity with Agile methodologies and hands-on experience with Jira and similar project management tools. Experience working with Git, Gerrit, or equivalent version control tools. Prior experience with cloud technologies (e.g., microservices, containers) is an added advantage. Strong communication skills, with the ability to work effectively in a global, multicultural environment. Work on pioneering 5G technology projects in a dynamic, collaborative environment. A global culture built on Nordic values transparency, low hierarchy, respect, and trust. Opportunities for ongoing learning and professional development in cutting-edge technologies. A supportive environment where innovation and work-life balance are actively encouraged. Inclusive workplace where diversity, equity, and inclusion are valued and celebrated. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity drives innovation. We welcome applications from candidates of all backgrounds, genders (m/f/d), and walks of life, fostering an inclusive and inspiring work environment where everyone feels valued and empowered to contribute. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or equivalent.
Senior 5g Ran Developer
Tietoevry
Job Title: Senior 5G RAN Developer Location: Bengaluru, India Experience: 4 to 8 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline About Tietoevry At Tietoevry, we are at the forefront of 5G innovation, collaborating with global telecom leaders to design and deliver next-generation wireless solutions. Our inclusive, innovation-driven culture offers the perfect platform to work on cutting-edge technologies and contribute to shaping the future of connectivity. Role Overview As a Senior 5G RAN Developer, you will play a critical role in designing, developing, and maintaining 5G NR protocol software components. You will lead the systemization, development, and verification processes for various RAN subsystems, contributing to the development and optimization of gNodeB solutions. This role requires deep technical expertise in 5G RAN Layer 1, 2, and 3, combined with strong architectural insight and a proactive, problem-solving mindset. You will collaborate closely with clients and global teams, provide technical guidance to peers, and help drive innovation in our 5G product portfolio. Key Responsibilities Contribute to product development, maintenance, and delivery, including requirement analysis, high-level design (HLD), low-level design (LLD), coding, and verification of gNodeB. Analyze and prioritize 3GPP features for development across different subsystems. Lead system integration and testing activities in collaboration with client and internal teams. Provide technical leadership by guiding teams on complex design and architectural decisions. Drive continuous performance improvement and ensure quality deliverables. Identify and implement architectural enhancements to optimize product performance and scalability. Document development processes, system designs, and testing outcomes thoroughly. Mandatory Skills & Experience Proven hands-on experience in developing LTE/5G NR MAC Scheduler and Layer-2 protocols. Deep knowledge of 3GPP specifications, particularly across Layer 1, Layer 2, and Layer 3. Strong understanding of Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Experience debugging complex gNodeB issues, including log file analysis and troubleshooting in live environments. Proficiency in C/C++ programming, with experience implementing complex algorithms. Hands-on experience with any of the following features: MAC, RLC, PDCP, Scheduler, Power Control, SPS, TTI Bundling, Link Adaptation, GTP-C, GTP-U In-depth understanding of 3GPP Radio Access Standards, ORAN split architecture, and radio protocol algorithms. Experience in feasibility studies and simulations related to Layer 1/PHY features and packet scheduler algorithms. Experience in software development and systemization for 5G Layer 1/Layer 2/Layer 3 protocols. Strong grasp of Linux OS and optimization techniques using DPDK. Hands-on expertise with version control tools like Git and Gerrit, and project management tools like Jira. Experience working in Agile environments. Preferred Skills Experience with cloud technologies, such as microservices and containers. Exposure to ORAN/Open RAN ecosystems is a plus. Strong analytical mindset with a self-driven and proactive approach. Soft Skills Excellent communication skills, with the ability to work in a dynamic, multicultural environment. Strong collaboration skills to work closely with cross-functional teams across geographies. Ability to mentor and guide junior developers, fostering knowledge sharing within the team. Opportunity to work on cutting-edge 5G technology projects in collaboration with global telecom leaders. A Nordic-inspired culture based on trust, transparency, respect, and low hierarchy. Professional growth through continuous learning, training programs, and exposure to emerging technologies. An inclusive workplace that supports work-life balance. Opportunities for global collaboration, contributing to innovative solutions that shape the future of mobile connectivity. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity fuels innovation. We actively encourage applications from all genders (m/f/d) and candidates from diverse backgrounds. We are committed to fostering an open, inclusive, and inspiring workplace where every individual can thrive. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline
Sr. Engineering Manager
Ness Digital Engineering
Job Title: Sr. Engineering Manager - Data Engineering Level: L5 Experience: 13-16 years Overview We are seeking an experienced Engineering Manager with a strong background in Data Engineering, including ETL/ELT processes and cloud-based data platforms such as Snowflake. The ideal candidate will lead and mentor a team of data engineers, drive data architecture initiatives, and work closely with cross-functional stakeholders to ensure our data infrastructure supports evolving business needs. Key Responsibilities Team Leadership: Lead, mentor, and develop a high-performing data engineering team, fostering a culture of collaboration, innovation, and continuous learning. Data Pipeline Development: Oversee the design, development, and maintenance of robust ETL/ELT pipelines to ingest, transform, and process data at scale. Cloud Data Infrastructure: Drive the architecture and implementation of cloud-based data solutions, especially leveraging Snowflake, ensuring scalability, security, and reliability. Cross-Functional Collaboration: Partner with product managers, analysts, data scientists, and other business stakeholders to gather requirements and prioritize engineering efforts that deliver the most impact. Architecture and Design: Develop and enforce data architecture standards for high-performance data warehousing, ensuring seamless data integration across diverse sources. Performance Optimization: Identify and resolve performance bottlenecks, focusing on query optimization, cost management, and resource efficiency. Data Quality & Governance: Define and implement data quality frameworks and governance practices, ensuring data consistency and reliability across all pipelines. Innovation & Strategy: Stay informed on emerging data technologies and industry best practices, continuously improving processes and aligning solutions with long-term data strategies. Required Skills 8+ years of hands-on experience in data engineering, including 5+ years in a leadership role. Strong expertise in ETL/ELT processes and hands-on experience with tools like Talend, Informatica, or similar platforms. Deep proficiency in Snowflake or comparable cloud data platforms such as Redshift or BigQuery. Advanced SQL skills, including query optimization, performance tuning, data modeling, and schema design. Hands-on experience with Python or Java for data processing and automation. Knowledge of data governance, compliance standards, and data security best practices. Excellent communication and project management skills, with the ability to prioritize and manage multiple projects in parallel. Preferred Skills Exposure to Big Data technologies such as Spark, Hadoop, Databricks, Synapse, etc. Experience with workflow orchestration tools like Apache Airflow or AWS Step Functions. Familiarity with CI/CD pipelines and DevOps practices within data engineering. Experience working with BI tools like Tableau or Power BI, and reporting integrations.
Soc Power And Performance Engineer
Intel Corporation
Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.
Platform Power And Performance Engineer
Intel Corporation
Job Title: Power Optimization & Performance Engineer Windows Platforms Job Description: Intel is seeking a Power Optimization & Performance Engineer to drive power efficiency and responsiveness enhancements across Windows platforms. The role involves deep analysis of software workloads, power-performance tuning, and debugging complex system-level issues to optimize Intel s laptop and desktop platforms. The engineer will work closely with platform architects and cross-functional teams to define power-performance metrics, develop battery life improvement strategies, and drive forward-looking technology readiness initiatives. Key Responsibilities: Power & Performance Analysis: Perform in-depth analysis of software flows at the trace, thread, and process ID levels to identify power optimization opportunities and performance bottlenecks. Platform Power Optimization: Leverage state-of-the-art analysis tools to identify and resolve battery life and performance issues in domains such as Graphics, Multimedia, Display, Imaging, and CPU. Technical Leadership & Troubleshooting: Diagnose complex system-level power and performance issues, demonstrating strong debugging expertise in Windows-based Intel platforms. Cross-Team Collaboration: Work with platform architects and engineers to define power-performance metrics, optimize power delivery across SoC components, and influence next-generation platform architectures. Windows OS & Driver Optimization: Identify and drive power savings features or performance tuning opportunities into current and next-gen Intel platforms. Collaborate with OS and driver teams for power-aware enhancements. Future Technology Readiness: Analyze expected vs. actual platform behavior, propose forward-looking enhancements, and influence SoC and Windows OS architectures. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Electronics or Computer Engineering or related fields. Technical Expertise: Embedded Systems & Software Development: Experience in software/firmware development, integration, or validation. Platform Power Management: Understanding of CPU/SoC architecture, power delivery, sensors, memory, storage, display, multimedia, and imaging subsystems. OS & System Debugging: Strong grasp of Windows OS fundamentals, system-level debugging, and exposure to firmware & device drivers. Windows Debug Tools: Experience with Windows Driver Debugging and Windows Debug tools (preferred). Power & Performance Optimization: Hands-on experience with power-performance measurement, analysis, and benchmarking. Analytical & Problem-Solving Skills: Ability to troubleshoot complex system issues and propose efficient power-saving techniques. Excellent Communication & Collaboration: Strong ability to interact across teams and drive technical discussions. About Intel s Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-ones. As Intel s largest business unit, CCG is dedicated to enhancing PC experiences, fostering innovation, and delivering market-leading computing solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates, regardless of gender, nationality, disability, or other protected status. Intel offers a highly competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Access to cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Electronics or Computer Engineering or related fields.
Senior Post Silicon Ate Test Engineer
Intel Corporation
Job Title: Senior ATE Test Engineer Manufacturing & Product Engineering Job Description: Intel is seeking a Senior ATE Test Engineer to drive the testability and manufacturability of integrated circuits from feasibility to high-volume production (HVM). The role involves developing and validating test methodologies, debugging functionality and performance issues, and optimizing test processes for yield and cost efficiency. The engineer will work closely with design, process development, fab, assembly, and manufacturing teams to ensure seamless production ramp-up and quality assurance. Key Responsibilities: Test Development & Debugging: Design, develop, and validate testability circuits and test flows for new products. Debug functionality and performance issues to root cause using Automatic Test Equipment (ATE). Interface with design, DFx (Design for Test, Debug, Manufacturing), and product teams to drive test development. Manufacturability & High-Volume Ramp (HVM): Collaborate with fab, assembly, test factories, and quality/reliability teams to enable smooth production ramp-up. Perform ATE device characterization, define datasheet specifications, and conduct yield analysis. Analyze early customer returns and drive test hole closure activities to enhance quality and reliability. Production Test Optimization: Drive test time reduction by analyzing fallout data and balancing product cost optimizations. Implement bin split and die-level cherry-pick (DLCP) strategies to optimize product supply. Ensure manufacturability through process and spec corner analysis to resolve yield issues before mass production. Hardware & Software Development: Develop and debug complex software programs for test conversion and test automation. Create and validate test hardware solutions for production testing. Optimize component production relative to quality and cost constraints. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields. Technical Expertise: ATE Test Engineering: Strong expertise in Automatic Test Equipment (ATE) development and debug. DFT & Test Methodologies: Knowledge of DFT architectures and methodologies including Analog DFT, JTAG, etc. Understanding of test engineering processes and tester debugging techniques. Debugging & Validation: Hands-on experience with design/validation and advanced debugging skills. Expertise in Advantest 93K, Teradyne Ultraflex, J750, and related test platforms. Manufacturing Process & Yield Analysis: Experience in yield analysis, bin splitting, and test time optimization. Ability to analyze process corners and drive manufacturing readiness. Soft Skills: Excellent problem-solving skills, teamwork, and communication. Strong interpersonal and planning skills for cross-functional collaboration. About Intel s Manufacturing & Product Engineering (MPE) Group: The MPE team is responsible for test development across Intel s product segments, contributing to 95% of Intel s revenue. The team delivers pre-production test suites and physical debug capabilities to enable high-quality, high-volume manufacturing. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates. Intel offers a competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields.
Msip Digital Design Engineer
Qualcomm
Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering
Asic Power Management Architect
Google Careers
About the Job Join a diverse team that pushes boundaries by developing custom silicon solutions powering the future of Google's direct-to-consumer products. Contribute to the innovation behind products loved by millions worldwide and help shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team blends the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies to make computing faster, seamless, and more powerful, ultimately improving people s lives through technology. Responsibilities Define ASIC power management architecture for an SoC, including image compute, CPU/GPU functions, ensuring maximum performance under power and thermal constraints. Prototype firmware and validate the next-generation SoC power management system at various design stages. Analyze implementation and models, and test the performance of power management solutions. Produce detailed documentation on the proposed power management implementation and conduct trade-off analyses for engineering reviews and product roadmap decisions. Collaborate with software teams and the power architecture team to build system-level designs and methods for optimized power management. Minimum Qualifications Bachelor s degree in Electrical Engineering or equivalent practical experience. 8 years of experience in power management or post-silicon measurements and validation. 3 years of experience with power management validation. Preferred Qualifications Master s degree or PhD in Electronics, Computer Engineering, or Computer Science, with an emphasis on computer architecture and performance/power analysis. Solid knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation strategies. Strong understanding of how software and architectural design decisions affect the power and thermal behavior of systems, including thermal mitigation, scheduling, and cross-layer policy design.
Analog Design Engineer
Qualcomm
Job Overview As a Hardware Engineer at Qualcomm, you'll be part of a dynamic team that plans, designs, optimizes, verifies, and tests cutting-edge electronic systems, including circuits, mechanical systems, digital/analog/RF/optical systems, and more. Your role will focus on SerDes PHY Analog Design, specifically within the BDC SerDes Mixed-Signal Design team. This team is directly involved in delivering next-generation custom PHY designs for SoCs (System on Chips), with a key focus on low-power analog designs to support Qualcomm s wireless products. You ll work with cross-functional teams to meet performance requirements and help bring innovative products to market. Key Responsibilities Analog Circuit Design: Hands-on experience in analog circuit design, working on multiple analog building blocks, including LDO, high-speed TX and RX (Equalizer, Sampler, PI, Deserializer), Bias, and Reference circuits. PLL and Frequency Synthesis: Design and implement Analog and Digital PLLs for frequency synthesis and SerDes applications, including Charge Pumps, Loop Filters, VCO/DCO, PFD/TDC, and high-speed dividers. PLL Loop Dynamics: Model PLL Loop Dynamics, including sources of Jitter (RJ & DJ). Schematic to Post-Layout Verification: Take designs from initial schematic to post-layout verification, and ensure integration sign-off for post-silicon bring-up. Collaboration: Work closely with RTL, DD, PD, DV, and SoC Verification teams to integrate the PHY into SoCs. Minimum Qualifications Educational Background: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 3+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 2+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field, with 1+ year of relevant work experience. Skills & Experience Analog Circuit Design: Hands-on experience with designing analog building blocks such as LDO, high-speed TX/RX, bias, and reference circuits. PLL Design: Strong background in Analog and Digital PLLs for frequency synthesis and SerDes applications. Charge Pump and VCO/DCO: Experience in designing charge pumps, loop filters, VCO/DCO, PFD/TDC, and high-speed dividers. Jitter and PLL Loop Dynamics: In-depth understanding of PLL loop dynamics, jitter modeling, and frequency synthesis for SerDes systems. Design Verification: Experience in taking designs from schematic through post-layout verification, integration, and post-silicon bring-up. Team Collaboration: Ability to work with cross-functional teams such as RTL, DD, PD, DV, and SoC verification teams to ensure smooth integration.
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