Route 53 Jobs in Bengaluru

Position: Associate - Logistics Operations Department: Logistics & Linen Operations Location: Bengaluru Employment Type: Full-Time About Laundryheap: Laundryheap is a fast-growing, award-winning startup revolutionizing the laundry and dry cleaning industry. Operating in 14 global markets and expanding rapidly across Europe, Asia, and North America, we re proud to offer one of the quickest services in the business delivering clean clothes within 24 hours. Role Overview: As an Associate in Logistics Operations, you ll play a key role in ensuring the smooth execution of our live delivery operations. Reporting to the Assistant Regional Manager, you will manage real-time driver activity, optimize routes, and provide essential support to our drivers, ensuring operational excellence and customer satisfaction. What You ll Do: 1. Operations & Route Management: Oversee live delivery operations to ensure routes are executed smoothly and orders are completed on time. Provide real-time support to drivers via chat, calls, or internal platforms. Optimize route plans for maximum efficiency and minimal delays. Proactively resolve any on-route issues such as delays, misrouted deliveries, or driver emergencies. 2. Driver Support & Performance: Address inbound driver queries related to payments, schedules, feedback, and general support. Log driver interactions, escalate unresolved issues, and ensure follow-ups are completed. Ensure adequate driver coverage across multiple time zones to meet live operational demand. 3. Operations & Project Support: Contribute to team goals by supporting or initiating projects aimed at streamlining operations. Maintain internal documentation and knowledge bases to ensure up-to-date resources. Monitor KPIs, identify performance bottlenecks, and ensure service level agreements (SLAs) are met. Collaborate with teams across regions (UK, US, Singapore) to ensure smooth cross-functional operations. Required Skills & Experience: Education: Bachelor s degree or equivalent. Experience: 3 5 years in operations, logistics, or support (experience in international environments is a plus). Skills: Strong communication skills, both verbal and written. Ability to handle high-pressure, fast-paced environments with poise. Experience with driver or agent onboarding (calls/video) and live operational support. Proficient in email, chat support tools, and Google Sheets/MS Excel. Flexibility to work night or rotational shifts. Strong stakeholder management skills. A proactive, solution-oriented mindset with a focus on empathy. Preferred Skills: Experience in international support chat (US/EU region preferred). Background in startups, logistics, or last-mile delivery operations. Familiarity with live route planning tools and CRM systems. Analytical mindset with an ability to interpret operational data. Why You Should Join Us: Growth & Impact: Be part of a fast-paced, international startup where your contributions make a tangible impact on day-to-day operations. Global Collaboration: Work alongside teams from across the globe, contributing to innovative solutions and continuous improvement. Career Growth: Enjoy high visibility in a flat team structure and rapid career growth opportunities. Qualification : Bachelors degree or equivalent

AWS Cloud Architect Location: Bengaluru, Karnataka, India Job Category: Consulting Job Type: Regular Employee Role: Individual Contributor Job Description: The Finergy division within Oracle FSGIU focuses exclusively on the Banking, Financial Services, and Insurance (BFSI) sector. The team provides deep domain knowledge to address complex financial needs and deploys multi-channel delivery platforms, ensuring a reduction in IT intervention and time to market. With several loyal clients over a decade, Finergy also delivers end-to-end banking solutions, offering integrated dashboards and analytics to enhance operational efficiency. As part of the team, you'll be responsible for architecting highly available, scalable, and secure AWS-based solutions while collaborating with both technical and non-technical stakeholders. Responsibilities: Design and architect fault-tolerant, highly available, and scalable solutions on AWS. Utilize services like EC2, S3, Lambda, RDS, Route 53, VPC, etc., for building secure and efficient cloud infrastructure. Lead migration projects from on-premises to AWS, ensuring seamless transitions. Automate provisioning and management of AWS infrastructure using CloudFormation and similar tools. Document best practices and standards for AWS architecture and deployments. Monitor cloud infrastructure performance, resolve bottlenecks, and optimize costs. Implement security measures to meet compliance with industry standards. Stay updated on the latest AWS features and provide guidance on new solutions. Provide technical leadership and mentorship to junior team members. Work in close collaboration with development teams to address AWS-related requirements. Qualifications and Skills: Bachelor's degree in Computer Science, Engineering, or related field. 8-10 years of experience in AWS architecture. AWS Certified Solutions Architect - Professional certification is mandatory. Proven track record in designing and implementing complex AWS solutions. Expertise in networking, security, and system administration concepts. Strong programming skills, preferably in Python. Excellent problem-solving and analytical abilities. Ability to explain technical concepts clearly to both technical and non-technical stakeholders. Strong teamwork and collaboration skills. If you're passionate about leveraging AWS to build innovative, scalable, and secure cloud solutions, this is a fantastic opportunity to join an experienced team in the growing BFSI domain. Qualification : Bachelor's degree in Computer Science, Engineering, or related field.

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Position: AGV Technical Specialist Department: Research & Development Reporting To: General Manager Location: Bengaluru Key Responsibilities AGV Design & Development Lead the design and development of AGV systems, including electrical, electronics, and navigation systems. Design, implement, and troubleshoot **line follower, inductive, RFID, and SLAM (LiDAR)** based navigation systems. Develop and apply communication protocols for **multi-AGV coordination**. Component Selection & Interface Select and interface **safety PLCs, standard PLCs, area scanners, servo motors**, and other AGV components. Hands-on experience with the programming and integration of various hardware components in AGV systems. AGV System Architecture Design and implement **multi-AGV architecture**, ensuring scalability and efficiency. Independently manage AGV platform functions such as **scheduling, health monitoring, and fault management**. Optimize the AGV platform to meet specifications and performance requirements while exploring innovative solutions for indigenization. Peripheral Equipment Integration Manage the integration of peripheral equipment with AGVs and ensure seamless communication. End-to-End Responsibility Oversee the complete AGV design and deployment lifecycle from the control perspective. Ensure the full transition from requirements design to commercial deployment, including coding, testing, and debugging system software. Review and validate new product designs and provide post-production support. Innovation & Documentation Apply innovative design thinking to develop and document AGV solutions. Create layouts, drawings, and implement designs through software or web portals. Prepare and review BOMs, wiring diagrams, and cost estimates for AGV solutions. Skills & Expertise Core Skills Vehicle control system design (essential). Proficiency in Python, C, C++ (essential). Expertise in vehicle-to-base station communication. Strong knowledge of vehicle odometer control. AGV-Specific Skills In-depth experience with **AGV navigation**, including **SLAM, LiDAR, RFID, and inductive systems**. Experience with **safety PLC, PLCs, area scanners, and servo motors** integration. Familiarity with AGV scheduling, fault management, and health monitoring systems. System Integration Expertise in integrating sensors and other vehicle components in AGVs. Familiarity with developing and deploying solutions in an **IIoT/Cloud platform** environment (good to know). Communication & Documentation Strong verbal and written communication skills for customer interaction and requirements gathering. Experience in creating **BOMs, wiring diagrams**, and supporting deployment efforts. Qualifications Essential: BE in Mechatronics, Computer Science, Mechanical Engineering, or equivalent. Experience: 5-6 years of experience in AGV design and development, with a strong understanding of vehicle controls, communication protocols, and multi-AGV systems. Qualification : BE in Mechatronics, Computer Science, Mechanical Engineering, or equivalent

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

Scope: This role is responsible for executing chemical reactions to synthesize required quantities of molecules/compounds according to client specifications, utilizing efficient synthetic routes and techniques. Key Responsibilities: Reaction Setup & Execution: Understand and execute reactions for synthesizing target molecules/compounds according to project specifications. Plan and execute reactions using proper reagents and equipment (e.g., glassware, stirrers, vacuum pumps) while maintaining specified conditions (temperature, pressure). Ensure parallel execution of multiple reactions. Safety & Risk Mitigation: Discuss and understand the Material Safety Data Sheet (MSDS) with team members. Identify and mitigate potential safety risks with supervisor guidance. Follow safety and quality systems, maintaining laboratory housekeeping and proper equipment usage. Analysis & Reporting: Monitor the reaction progress using analytical techniques. Identify and apply appropriate workup and purification techniques to produce high-quality intermediate/final compounds. Analyze, evaluate, and interpret analytical data from synthesis, providing accurate reports. Document reactions, research findings, and observations in lab notebooks to ensure data integrity. Productivity & Compliance: Meet productivity benchmarks regarding the number of reactions, steps, compounds, quality, and timelines. Maintain strict IP confidentiality and adhere to all policies regarding data integrity. Prepare final reports as required by clients and internal stakeholders. Team Development: Foster a learning environment by improving team knowledge in organic chemistry and analytical techniques. Conduct one-on-one discussions, classroom training, and project-based training to enhance skills. Ensure the team s morale and productivity through continuous skill development. Functional/Technical Skills: Chemistry Expertise: Knowledge of organic chemistry, particularly synthesis and execution techniques. Safety Compliance: Strong understanding of safety protocols in laboratory environments. IP & Confidentiality: Awareness of IP protection, confidentiality, and maintaining data integrity. Resource Optimization: Ability to conduct cost-benefit analysis and ensure the optimum usage of resources. Required Qualifications: Educational Requirements: M.Sc. in Organic/Medicinal Chemistry with 1 5 years of relevant experience. Preferred Qualifications: Candidates with research publications in leading journals are preferred. Equal Employment Opportunity Statement: Aragen provides equal employment opportunities to all individuals regardless of age, color, national origin, citizenship status, mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity, genetic information, marital status, veteran status, or any characteristic protected by applicable legislation or local law. Reasonable accommodations will be provided for qualified individuals with disabilities. Qualification : M.Sc. in Organic/Medicinal Chemistry with 15 years of relevant experience.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Job Description You will be part of ACE India, in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets 4. Closely work with SD, Integration and Floor plan teams Qualifications Qualifications You must possess a master s degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelor s degree with at least 10 years of experience. Technical Expertise in Static Timing Analysis is preferred. Should have minimum of 2 years experience in leading the Team of at least 3-4 people Preferred additional skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : You must possess a masters degree in electrical or Electronics Engineering with at least 8 or more years of experience in related field or a bachelors degree with at least 10 years of experience.

Manage an ASIC design team responsible for various blocks, sub blocks and SOC Top. Drive RTL design planning and execution, innovative design methodology development, IP design and SOC integration. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Verification, Modelling, Emulation, and Post-Silicon Validation teams. ASIC Engineering Manager Responsibilities Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, u-Arch, IP design and SOC integration. Participate in silicon architecture, interface with Architecture, SW/FW, Design, Modelling, Emulation, and Post-Silicon Validation teams Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing Build, lead, and support a team of ASIC engineers through strategic hiring, training, and guidance to drive on-time and on-budget product delivery Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs Define, implement and maintain key performance indicators (KPI) for areas of responsibility Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors Minimum Qualifications B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 15+ years experience in ASIC/SoC RTL design 5+ years of experience as a People Manager Clear understanding of complexities involved with various RTL design tools, including Synopsys DC compiler, Cadence LEC, Spyglass. Track record of first-pass success in ASIC Development Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience with interpreting functional specs and creating comprehensive u-Arch Experience in building and growing teams Experience managing tech leads Preferred Qualifications Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip. In depth knowledge of at least one of these areas - NICs, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework Qualification : B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience

Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, IP design and SOC integration. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Verification, Modelling, Emulation, and Post-Silicon Validation teams. Asic Design Engineering Manager Responsibilities Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, u-Arch, IP design and SOC integration. Participate in silicon architecture, interface with Architecture, SW/FW, Design, Modelling, Emulation, and Post-Silicon Validation teams Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing Build, lead, and support a team of ASIC engineers through strategic hiring, training, and guidance to drive on-time and on-budget product delivery Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs Define, implement and maintain key performance indicators (KPI) for areas of responsibility Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors Minimum Qualifications B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience 12+ years experience in ASIC/SoC RTL design 3+ years of experience as a People Manager Clear understanding of complexities involved with various RTL design tools, including Synopsys DC compiler, Cadence LEC, Spyglass. Track record of first-pass success in ASIC Development Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience with interpreting functional specs and creating comprehensive u-Arch Preferred Qualifications Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip. In depth knowledge of at least one of these areas - NICs, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework Qualification : B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Senior Associate Infrastructure L1 (AWS) Location: Bengaluru, India Department: Infrastructure & Cloud Engineering Employment Type: Full-Time About the Role As a Senior Associate Infrastructure L1 (AWS), you will design, implement, and manage secure, scalable, and highly available cloud infrastructure for enterprise digital transformation initiatives. You ll collaborate with cross-functional teams to automate deployments, enable DevOps best practices, and ensure robust observability across systems. Your goal is to reduce time-to-market and optimize performance, cost, and compliance. Key Responsibilities Architect and build immutable infrastructure on AWS and/or other cloud platforms. Implement and maintain infrastructure as code using Terraform, CloudFormation, or similar. Manage containerized environments using Kubernetes (EKS/GKE), ECS, Docker, and Helm. Implement service mesh (e.g., Istio) for advanced traffic management, monitoring, and security. Develop and manage CI/CD pipelines using Jenkins, GitLab, CircleCI, or similar. Automate build/deployment processes using Groovy, Go, Python, Shell, or PowerShell. Integrate DevSecOps and security scanning into the software delivery lifecycle. Configure and maintain monitoring, logging, and observability using: Monitoring: Prometheus, Grafana, Datadog, New Relic Logging: ELK Stack, Fluentd, Splunk Observability: OpenTelemetry, Jaeger, Kiali, CloudTrail, Dynatrace Troubleshoot infrastructure, performance, and deployment issues. Collaborate with application teams and stakeholders to ensure high performance and availability of deployed services. Required Skills & Qualifications 4 to 12 years of experience in Cloud Infrastructure & DevOps roles. Bachelor's or Master s degree in Engineering, Computer Science, or related field. Hands-on experience with AWS (EC2, VPC, IAM, Lambda, RDS, CloudWatch, etc.) Solid experience in container orchestration using Kubernetes (EKS/GKE) and infrastructure management. Expert in IaC tools like Terraform (preferred), ARM templates, Pulumi, etc. Proficiency in CI/CD pipeline automation and scripting. Familiarity with cloud-native security practices and vulnerability scanning tools. Experience with DNS, Load Balancers, and high-volume application infrastructure setup. Hands-on experience with artifact repositories like Nexus or Artifactory. Preferred Certifications (Nice to Have) Associate-level certifications in AWS, Azure, or GCP HashiCorp Certified Terraform Associate Benefits Gender-neutral workplace policies 18 paid holidays per year Generous parental leave and new parent transition support Flexible work arrangements Comprehensive Employee Assistance Program (mental & physical wellness) About Publicis Sapient Publicis Sapient is a global digital transformation partner helping established organizations evolve into their future state through technology, data, consulting, and customer-first experiences. With over 20,000 employees across 53 offices, we combine deep domain knowledge with a start-up mindset and agile methods to solve complex business challenges.

Manager Experience Engineering (React) Location: Bengaluru, India Department: Engineering | Front-End (React) Type: Full-Time About the Role As a Manager Experience Engineering, you will lead and mentor cross-functional teams, architect complex front-end applications, and act as a thought leader in front-end technologies. Your expertise in React, modern JavaScript, and UX engineering will be crucial in crafting seamless user experiences for enterprise-grade solutions. You will also collaborate with clients, designers, and internal teams to deliver innovative and scalable front-end architectures. Key Responsibilities Lead, architect, and deliver scalable front-end solutions using React and modern JavaScript. Mentor developers and guide teams on engineering best practices and SA3 methodologies. Collaborate closely with information architects, designers, and backend teams to ensure high usability and performance. Represent Publicis Sapient s thought leadership with clients and manage peer-level relationships. Own the technical roadmap for front-end implementations and manage risk mitigation strategies. Review and ensure compliance with accessibility, performance, and SEO standards. Contribute to front-end development standards and influence continuous technical improvement. Required Skills & Experience 10+ years of experience in software development with a focus on front-end engineering. Bachelor s degree in Computer Science or related field with strong fundamentals in data structures, algorithms, OS, networking, and graphics. Strong command over HTML5, CSS3, and JavaScript (ES6+). Expertise in React and state management using Redux (Thunk/Saga) or MobX. Solid understanding of OOJS and JavaScript design patterns. Experience in monolithic and micro-frontend architectures. Proficiency in frontend build tools: Node.js, Webpack, Grunt, Gulp. Experience with TDD/Unit Testing in JS using Jest, Mocha, Karma, Jasmine, etc. Familiarity with responsive design, CSS frameworks (Bootstrap), and accessibility standards (ARIA). Experience with client-side templating (Handlebars, Mustache). Comfortable with templating languages, SEO best practices, and performance/security tools. Exposure to MV* frameworks like AngularJS, Backbone.js is a plus. Advantageous: Experience integrating with backend technologies (Java, .NET), CMS, and eCommerce platforms. What Sets You Apart Natural leadership and mentoring skills. Strong communication and stakeholder engagement. Passion for emerging tech and continuous learning. Self-motivated, proactive, and detail-oriented. Proven ability to architect clean, scalable solutions. Benefits Comprehensive Health and Wellness coverage Statutory and financial planning benefits Career advancement through continuous learning & upskilling Flexible work arrangements under the Flexi Work Policy Employee Assistance Programs for mental well-being About Publicis Sapient Publicis Sapient is a global digital transformation partner helping established organizations achieve a digitally-enabled future. Combining strategy, consulting, design, and engineering with agile methods, we help clients build the products and experiences their customers truly value. With over 20,000 employees in 53 offices worldwide, we empower innovation at scale. Qualification : Bachelors degree in Computer Science or related field with strong fundamentals in data structures, algorithms, OS, networking, and graphics.

Manager Adobe AEM Engineering Location: Bengaluru, India Department: Experience Engineering | Adobe AEM Type: Full-Time About the Role As a Manager Adobe AEM, you will lead the delivery of end-to-end digital experience platforms for global clients using Adobe Experience Manager and other Adobe Experience Cloud solutions. You will architect, implement, and optimize scalable enterprise content management solutions, while mentoring technical teams and working directly with clients to understand and translate business requirements into robust, scalable systems. Key Responsibilities Lead design, architecture, and implementation of large-scale AEM projects (Sites, Assets, AEM as a Cloud Service). Architect AEM components, templates, workflows, tagging, publishing, and metadata models. Define and implement cloud-native, SEO-optimized, accessible, secure, and performant digital platforms. Oversee quality processes, including CI/CD (e.g., Jenkins, Bamboo, Cloud Manager), code reviews, SonarQube, and automated testing. Manage infrastructure setup and configurations: Load Balancers, Apache, CDN, DR, and AEM environments. Collaborate across cross-functional teams including frontend (React, Angular, HTL), backend (Java), QA, and DevOps. Support content migration, integrations with eCommerce platforms (Hybris, Magento), and Digital Asset Management systems. Ensure adoption of best practices in performance, scalability, monitoring, and responsive design. Interface directly with clients for technical consulting, requirement gathering, and delivery oversight. Lead and mentor development teams (20+ members) across all project phases in Agile/Scrum environments. Required Skills & Experience 10+ years of experience in software engineering with at least 5+ in AEM development. Deep expertise in AEM architecture (including SaaS/Cloud Service, SDK), deployment (Maven), and migration planning. Proficient in Java 8/11, JCR, OSGi, Sling Models, HTL, JSP, and server-side integrations. Strong understanding of frontend development (ReactJS, Angular, Bootstrap, HTML5, CSS3, JS frameworks). Familiarity with Adobe I/O Runtime, Adobe Events, and cloud platforms (AWS, Azure, GCP). Experience with Adobe Experience Cloud tools: Target, Analytics, Campaign, Launch, Scene7. Proven success in leading full-stack delivery teams including frontend, backend, QA, and PM. Knowledge of SEO, accessibility (WCAG A, AA, AAA), performance monitoring (New Relic, AppDynamics), and analytics integration. Hands-on with monitoring and observability tools: Squid, Nagios, Zabbix, Ganglia, etc. Exposure to Agile methodologies and estimation/planning across digital project lifecycles. Bonus / Preferred Qualifications Experience integrating AEM with eCommerce (Magento, Hybris, ElasticPath). Working knowledge of microservices, containerization, and RESTful services. Adobe certifications (e.g., Adobe Certified Expert AEM Developer/Architect). Familiarity with Adobe I/O integrations and Adobe Dynamic Media. Benefits Gender-Neutral Policy 18 Paid Holidays per year Parental Leave and New Parent Transition Program Flexible Work Arrangements Employee Wellness Programs About Publicis Sapient Publicis Sapient is a premier digital transformation partner helping global enterprises redefine their future with technology. With over 20,000 professionals across 53 offices worldwide, we deliver bold digital solutions across strategy, customer experience, data, and engineering.

Director / Senior Director Business Development Location: Bengaluru | NCR | Hyderabad | Pune Department: Sales & Go-To-Market Type: Full-Time | Leadership Role About the Role As a Director or Senior Director Business Development, you will spearhead strategic sales growth initiatives across India-based Global Capability Centers (GCCs) within verticals such as financial services, healthcare, retail, and automotive. You ll leverage deep industry networks, strategic thinking, and technology insight to drive revenue, build lasting client relationships, and shape Publicis Sapient s digital transformation footprint in India. This is a high-impact leadership role, ideal for someone with a track record of enterprise sales success, particularly within digital services or consulting environments. Key Responsibilities Sales Strategy & Execution Define and lead go-to-market strategies for India-based GCCs. Own the end-to-end sales cycle, including lead generation, RFPs, negotiations, and deal closure. Align business development goals with company vision and revenue objectives. Segment the market and prioritize target accounts (large enterprises, public sector, digital transformation buyers). Client Acquisition & Relationship Building Build and manage a robust pipeline of enterprise clients. Cultivate trusted advisor relationships with senior stakeholders and decision-makers. Represent Publicis Sapient in high-stakes negotiations and strategic engagements. Internal Collaboration & Team Incubation Initially operate in an individual contributor (IC) capacity until business scale demands team expansion. Collaborate with internal teams (growth, marketing, client partners, delivery) to craft tailored value propositions. Lead knowledge sharing and contribute to team culture, mentoring future BD hires. Required Skills & Experience 15+ years in enterprise/technology sales, preferably in digital consulting, tech services, or IT transformation. Proven ability to build a book of business and execute sales in a high-growth or consulting environment. Deep understanding of the India GCC landscape and established network in relevant industries. Strategic thinker with strong execution and account segmentation capabilities. Excellent communication, presentation, and negotiation skills. Self-driven, collaborative, and experienced in handling complex B2B deal cycles. Preferred Qualifications Master s degree in Business, Technology, or a related field (MBA preferred). Experience selling to CIOs, CTOs, Chief Digital Officers, or transformation leaders. Familiarity with cloud, data, engineering, and agile digital services offerings. Understanding of how large enterprises buy digital transformation services. Why Join Publicis Sapient Gender-Neutral Policy 18 Paid Holidays per year Parental Leave & Transition Program Flexible Work Options Wellness and Employee Assistance Programs About Publicis Sapient Publicis Sapient is a global digital transformation partner serving established enterprises through a fusion of strategy, consulting, customer experience, and agile engineering. With over 20,000 professionals in 53 offices worldwide, we drive meaningful change by helping clients modernize how they work and serve their customers. Qualification : Masters degree in Business, Technology, or a related field (MBA preferred).