Speech Synthesis Jobs in Bengaluru

Lead Machine Learning Engineer Location: Bangalore | Employment Type: Full-time About the Role We are seeking a talented and driven Lead Machine Learning Engineer to join Avaamo s Product Engineering team. In this role, you will have the opportunity to shape and enhance the core features of our search technology stack, focusing on areas like search ranking models, query understanding, and natural language question answering. What You ll Do Innovate and expand the capabilities of our search stack, including ranking models, query parsing, and NLP-driven question answering. Gain a deep understanding of search usage patterns and user needs, identifying areas for improvement and growth. Design, prototype, and iterate on cutting-edge ML/NLP/Information Retrieval solutions to enhance our search functionality. Develop and optimize an experimentation framework to evaluate and track improvements to the search stack. Write clean, efficient, and maintainable code that is easy to test and scale. Mentor junior engineers, fostering a collaborative learning environment and sharing your expertise. What You Bring (Qualifications) A BS in Computer Science or a related field. 5+ years of hands-on experience in machine learning, NLP, or related fields. Strong analytical and data-driven mindset, with the ability to extract insights and build effective solutions. Experience in recommendation systems, natural language processing, LLMs, applied machine learning, or large-scale search/ranking systems. Key Skills & Qualities Collaborative, customer-focused, and team-oriented, with a willingness to contribute across multiple areas of the product. Proactive, positive, and self-driven, with the ability to take ownership of both small tasks and large features. Proven experience in designing and building complex search/ranking/recommendation systems. Strong proficiency in Python programming. About Avaamo Avaamo is a deep-learning software company that focuses on creating advanced conversational interfaces to solve high-impact problems in the enterprise space. We are at the forefront of AI technologies, working on neural networks, speech synthesis, and deep learning to transform how enterprises engage with conversational computing. Qualification : BS in Computer Science or a related field

Machine Learning Engineer - Speech AI (ASR & TTS) Location: Bengaluru, Karnataka, India (On-Site) Department: Engineering Employment Type: Full-Time About Sarvam.ai Sarvam.ai is a pioneering generative AI startup headquartered in Bengaluru, India. We specialize in leading transformative research and development in speech and language technologies. Focused on building state-of-the-art ASR (Automatic Speech Recognition) and TTS (Text-to-Speech) models, particularly for Indic languages, we aim to redefine human-computer interaction with cutting-edge, AI-driven solutions. Join us as we push the boundaries of Speech AI to create inclusive, scalable, and intelligent voice-based applications for diverse communities worldwide. Role Overview We are seeking an experienced Machine Learning Engineer specializing in Speech AI (ASR & TTS). The ideal candidate will work on deep learning-based ASR and TTS models, improving accuracy, efficiency, and multilingual capabilities while deploying them at scale. The role involves developing and optimizing speech recognition and synthesis models with a focus on low-resource languages, real-time inference, and scalability. If you have a passion for speech processing and deep learning, this is a great opportunity to make a significant impact in a rapidly growing field. Key Responsibilities ASR (Automatic Speech Recognition) Develop, train, and optimize speech-to-text models using state-of-the-art architectures like Wav2Vec, Whisper, Conformer, and DeepSpeech. Implement techniques for low-latency ASR inference, including beam search, language model integration, and real-time transcription. Improve speech recognition accuracy for low-resource languages, especially Indic languages, using transfer learning and data augmentation. Optimize ASR pipelines for noise robustness, speaker adaptation, and domain-specific transcription. TTS (Text-to-Speech) Develop and fine-tune neural TTS models such as Tacotron, FastSpeech, VITS, or WaveNet for high-quality, natural-sounding speech synthesis. Implement multilingual and expressive TTS models with prosody and emotion control. Optimize TTS inference for deployment on edge devices, mobile, and cloud platforms. Improve speech synthesis quality through voice cloning, neural vocoders (HiFi-GAN, WaveGlow), and prosody modeling. General Speech AI Responsibilities Benchmark and profile ASR/TTS models to improve latency, efficiency, and deployment performance. Deploy scalable speech AI APIs on AWS, Azure, or GCP for real-world applications. Optimize ASR & TTS models for edge and offline inference. Stay updated with the latest advancements in speech AI, neural vocoders, and real-time inference techniques. Must-Have Qualifications Experience: 2-3 years of experience in speech AI, deep learning, or machine learning, with a focus on ASR & TTS. Education: Bachelor s or Master s degree in Computer Science, AI/ML, Speech Processing, or a related field. ML Frameworks: Proficiency in PyTorch or TensorFlow for training and deploying ASR/TTS models. ASR Expertise: Experience with speech-to-text architectures like Whisper, Wav2Vec, Conformer, or DeepSpeech. TTS Expertise: Experience with speech synthesis models like Tacotron, FastSpeech, or VITS. Speech Signal Processing: Understanding of MFCCs, STFT, phonemes, prosody modeling, and feature extraction. Inference Optimization: Hands-on experience with TensorRT, ONNX, or quantization (INT8, FP16) for ASR/TTS. Cloud & Edge Deployment: Experience deploying speech models on AWS, GCP, or Azure. Preferred Qualifications Experience with speech diarization, speaker recognition, or language modeling for ASR. Familiarity with zero-shot TTS, voice cloning, and multilingual speech modeling. Understanding of CUDA optimization and low-bit quantization for ASR/TTS models. Contributions to open-source speech AI projects or a strong GitHub portfolio showcasing relevant work. Experience with real-time streaming ASR/TTS applications and low-latency inference. Innovative Impact: Work on AI-driven speech solutions that are changing how people interact with technology, especially in low-resource languages. Cutting-Edge Technology: Contribute to the development of state-of-the-art speech AI models in a rapidly advancing field. Collaborative Environment: Work with a team of experts in AI, machine learning, and speech processing, in a startup culture. Growth Opportunities: Sarvam.ai offers exciting career growth in a fast-paced environment with opportunities for personal and professional development. Interested candidates are invited to submit their resume, cover letter, and any relevant project portfolios or GitHub links showcasing their experience in ASR, TTS, or Speech AI. Strong AI-related projects, whether in industry, research, or personal work, will be highly valued. Qualification : Bachelors or Masters degree in Computer Science, AI/ML, Speech Processing, or a related field.

Scope: This role is responsible for executing chemical reactions to synthesize the required quantities of molecules/compounds as per client specifications, employing efficient synthetic routes and techniques. Key Responsibilities: Reaction Setup & Execution: Understand and follow project requirements, including the synthetic route as specified by the client. Plan and execute reactions using the appropriate reagents and equipment (glassware, stirrers, vacuum pumps, etc.) while maintaining specified conditions (temperature, pressure, etc.). Ensure the parallel execution of multiple reactions, meeting productivity benchmarks for reactions, steps, compounds, and timelines. Monitor reaction progress using analytical techniques, making adjustments as necessary to ensure high quality and yield. Execute appropriate workup and purification techniques to achieve intermediates and final compounds of desired quality. Safety & Risk Mitigation: Discuss and understand the Material Safety Data Sheets (MSDS) with team members to ensure awareness of safety protocols. Identify potential safety risks and mitigate them with the help of a supervisor, ensuring safe lab practices. Follow all safety and quality control systems and maintain proper equipment use as per SOPs and laboratory housekeeping norms. Data Integrity & Reporting: Maintain strict documentation of reactions, observations, and research findings in lab notebooks to ensure data integrity. Ensure compliance with IP confidentiality policies and document results as per client specifications. Prepare final reports to summarize synthesis processes, results, and quality assessments. Team Development & Morale: Foster a learning environment by improving team members knowledge in organic chemistry (synthesis) and analytical techniques through one-on-one discussions, training programs, and educational sessions. Support team skill development and ensure a positive, productive atmosphere in the lab. Functional/Technical Skills: Chemistry Knowledge: Expertise in organic chemistry, particularly in the execution of synthetic reactions and compound synthesis. Safety Protocols: Proficiency in applying safety protocols and ensuring laboratory safety. Data Integrity & IP Confidentiality: Strong understanding of the importance of data integrity and adherence to IP confidentiality guidelines. Resource Management: Ability to perform cost-benefit analysis, optimizing the use of reagents, resources, and equipment for efficient lab operation. Required Qualifications & Experience: Educational Qualification: M.Sc. in Organic or Medicinal Chemistry with 1-5 years of relevant experience. Preferred Qualifications: Candidates with research publications in leading scientific journals are preferred. Qualification : M.Sc. in Organic or Medicinal Chemistry with 1-5 years of relevant experience.

Scope: This role is responsible for executing chemical reactions to synthesize required quantities of molecules/compounds according to client specifications, utilizing efficient synthetic routes and techniques. Key Responsibilities: Reaction Setup & Execution: Understand and execute reactions for synthesizing target molecules/compounds according to project specifications. Plan and execute reactions using proper reagents and equipment (e.g., glassware, stirrers, vacuum pumps) while maintaining specified conditions (temperature, pressure). Ensure parallel execution of multiple reactions. Safety & Risk Mitigation: Discuss and understand the Material Safety Data Sheet (MSDS) with team members. Identify and mitigate potential safety risks with supervisor guidance. Follow safety and quality systems, maintaining laboratory housekeeping and proper equipment usage. Analysis & Reporting: Monitor the reaction progress using analytical techniques. Identify and apply appropriate workup and purification techniques to produce high-quality intermediate/final compounds. Analyze, evaluate, and interpret analytical data from synthesis, providing accurate reports. Document reactions, research findings, and observations in lab notebooks to ensure data integrity. Productivity & Compliance: Meet productivity benchmarks regarding the number of reactions, steps, compounds, quality, and timelines. Maintain strict IP confidentiality and adhere to all policies regarding data integrity. Prepare final reports as required by clients and internal stakeholders. Team Development: Foster a learning environment by improving team knowledge in organic chemistry and analytical techniques. Conduct one-on-one discussions, classroom training, and project-based training to enhance skills. Ensure the team s morale and productivity through continuous skill development. Functional/Technical Skills: Chemistry Expertise: Knowledge of organic chemistry, particularly synthesis and execution techniques. Safety Compliance: Strong understanding of safety protocols in laboratory environments. IP & Confidentiality: Awareness of IP protection, confidentiality, and maintaining data integrity. Resource Optimization: Ability to conduct cost-benefit analysis and ensure the optimum usage of resources. Required Qualifications: Educational Requirements: M.Sc. in Organic/Medicinal Chemistry with 1 5 years of relevant experience. Preferred Qualifications: Candidates with research publications in leading journals are preferred. Equal Employment Opportunity Statement: Aragen provides equal employment opportunities to all individuals regardless of age, color, national origin, citizenship status, mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity, genetic information, marital status, veteran status, or any characteristic protected by applicable legislation or local law. Reasonable accommodations will be provided for qualified individuals with disabilities. Qualification : M.Sc. in Organic/Medicinal Chemistry with 15 years of relevant experience.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

About NVIDIA NVIDIA has continually reinvented itself. From pioneering the GPU fueling the growth of the PC gaming industry and transforming modern computer graphics to revolutionizing parallel computing, we have consistently shaped the future of technology. Today, NVIDIA GPUs drive innovation in artificial intelligence (AI), providing highly scalable, parallel computation that powers groundbreaking advancements across industries. We are a company that thrives on learning, evolution, and tackling the world s most complex challenges. Join us, and you ll be part of a diverse, innovative, and supportive team that inspires everyone to achieve their best work. About the Role: SOC Design Engineer The System-On-Chip (SOC) group at NVIDIA is expanding! As the complexity of SOCs grows with chips now integrating tens of billions of transistors we are seeking a talented SOC Design Engineer with a passion for RTL integration and chip-level front-end design. This role focuses on padring design, pinmuxing, SOC assembly, and retiming. If you enjoy developing methodologies and automation solutions to optimize SOC creation, this is the opportunity for you. In this role, you will work on NVIDIA s advanced Tegra SOCs, collaborating closely with cross-functional teams, including System Architecture, Physical Design, CAD, and DFT. You will help define and implement scalable and efficient SOC design methodologies for future technologies. What You ll Be Doing Drive SOC assembly and design chip-level functions for Tegra SOCs. Perform front-end design quality checks, reviews, and collaborate with cross-functional teams to resolve issues. Oversee SOC execution across key milestones by defining, tracking, and managing complex dependencies with multiple stakeholders. Develop system-level methodologies, tools, and IPs to enable efficient and scalable SOC design. Identify and address inefficiencies in front-end chip implementation processes, implementing solutions for continuous improvement. What We Need to See B.Tech or M.Tech in Electronics Engineering or a related field. 2+ years of proven experience in chip design, with a focus on SOC integration and design automation. (Experience with padring design and fuse/floorsweep is a plus.) Strong analytical and problem-solving skills. Proficiency in RTL design (Verilog) and knowledge of SOC design/implementation flows. Experience with scripting languages such as Perl, Python, or other industry-standard tools. Exposure to multiple chip design functions, enabling collaboration and problem-solving across diverse teams. Excellent communication and collaboration skills with a team-oriented mindset. Bonus Skills: Experience in SOC verification, synthesis, physical design, and DFT. Familiarity with RTL build flows and Makefiles. At NVIDIA, you ll work on technologies that make a lasting global impact. We believe in fostering a diverse, inclusive work environment where everyone can grow and thrive. NVIDIA is proud to be an equal opportunity employer and does not discriminate based on race, religion, gender identity, age, disability status, or any other protected characteristic. Qualification : B.Tech or M.Tech in Electronics Engineering.

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Job Description The Client DDRPHY team is looking for an energetic and passionate Logic Methodology Engineer who conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the logic/RTL design of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Defines methodologies that produce enhancements in power, performance, and area for designs on the new architectures and process technology nodes and aids high-speed digital design targeted towards low power optimized IP implementations. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing logic/RTL related TFM. Works closely with the logic design teams to create and enhance logic design methodologies that enable fast design convergence and facilitate seamless integration. You will be responsible for setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams. The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.Objectives of the position Own and deliver TFM flows which aid in the logic design of Mixed Signal IP Continuously drive the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements Drive area/power of IPs and come up with improvements on IP Area/Power metrics Critical Decision making on Technical issues. Qualifications The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience. Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation. Experience in the following areas/ skills are desired: Strong communicator Self-starter with a penchant for creative problem solving through quick thinking Good aptitude for automation Git/Perforce/CVS know how Perl/Python/TCL Spyglass Lint, CDC, DFT, VCLP, Open Latch Multiple clock domain design Synthesis and speed path debug Below experience is desirable, but not a must: Logic design using System Verilog Low-power design using UPF and clock gating State machine design Simulation and debug experience using VCS/Verdi Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Qualification : The successful candidate will possess a BS, MS degree with a 5-10 years of relevant industry experience.

Lead Machine Learning Engineer - NLP Location: Bengaluru About Us: Observe.AI Observe.AI is the leading AI agent platform for customer experience. It enables enterprises to deploy AI agents that automate customer interactions, delivering natural conversations for customers with predictable outcomes for the business. Observe.AI combines advanced speech understanding, workflow automation, and enterprise-grade governance to execute end-to-end workflows with AI agents. It also enables teams to guide and augment human agents with AI copilots, and analyze 100% of human and AI interactions for insights, coaching, and quality management. Companies like DoorDash, Affordable Care, Signify Health, and Verida use Observe.AI to transform customer experiences every day by accelerating service speed, increasing operational efficiency, and strengthening customer loyalty across every channel. You will be shaping how AI transforms real-world challenges in the contact center space. As part of our world-class ML team, you ll work on developing cutting-edge LLM-powered solutions & Agentic AI, building end-to-end processing pipelines, and handling production challenges at scale millions of interactions daily. If you are truly an engineer at heart, excited about turning breakthroughs in multi-agent systems, LLMs, NLP, and ML into practical outcomes through applied research, and building scalable production systems, you will feel right at home. You ll also have the opportunity to publish in top conferences, and influence Observe.AI s product and platform strategy. What you ll be doing Design & develop state-of-the-art LLM-powered AI capabilities and Agentic AI/ Multi-agent systems end-to-end, from ideation to production for Observe.AI s product offerings, in a fast-paced startup environment. Work with cutting-edge tools and technologies in Machine Learning, Deep Learning & Natural Language Processing, including LLMs and LLM-powered technologies/ paradigms, including Agentic AI. Build/ maintain highly scalable production systems that power AI capabilities on Observe.AI product/ platform. Optimize ML models and processing pipelines for performance, cost-effectiveness, and scale. Work with a world-class ML team in building exciting stuff, mentor juniors, and influence peers/ stakeholders. Collaborate cross-team with engineers, product managers, customer-facing teams, and customers to understand pain points and business opportunities. Keep up-to-date with the latest ML/ DL/ NLP literature and influence the technological evolution of Observe.AI platform. Contribute to the community through tech blogs and publishing papers in ML/ NLP conferences like EMNLP, ACL, etc. What you ll bring to the role Education: Bachelor s or Master s degree in Computer Science or related disciplines from a top-tier institution with exposure to ML/ DL/ NLP/ NLU. An engineering mindset with the competencies of an applied scientist. 5+ years of industry experience in building large-scale NLP/ NLU systems, with recent experience in building LLM-powered applications and Agentic systems. Strong understanding of the fundamentals of ML and NLP/ NLU, and practical aspects of building ML systems in production. Good understanding of recent advances in building LLM-powered applications, and multi-agent systems at scale. Excellent implementation skills in Python and Machine Learning Frameworks such as Pytorch, Tensorflow, HuggingFace, etc., and deploying/ maintaining scalable machine learning systems in production. Ability to provide thought leadership in one or more technical areas of interest to Observe.AI, and influence product development. Excellent communication, collaboration skills, and presentation skills. Experience with Spoken Language Understanding is a plus. Published papers in top NLP/ NLU conferences or workshops are a plus. Relevant open-source contributions are a plus. Perks & Benefits Medical Insurance: Excellent options and free online doctor consultations. Leave Policies: Yearly privilege and sick leaves as per Karnataka S&E Act, generous holidays (National and Festive) recognition and parental leave policies. Learning & Development fund to support your continuous learning journey and professional development. Fun events to build culture across the organization. Flexible benefit plans for tax exemptions (i.e. Meal card, PF, etc.). Qualification : Bachelors or Masters degree in Computer Science or related disciplines from a top-tier institution with exposure to ML/ DL/ NLP/ NLU

AI-ML Technologist Bangalore, India Location: Bangalore Experience: 3 to 10 Years Job Role: AI-ML Technologist Industry: IT Software / Artificial Intelligence & Machine Learning Job Summary: We are looking for a highly skilled AI-ML Technologist with strong expertise in Artificial Intelligence (AI), Machine Learning (ML), Deep Learning (DL), Natural Language Processing (NLP), and Computer Vision. The ideal candidate will have hands-on experience in developing intelligent solutions using Python and other programming languages and frameworks. Key Responsibilities: Develop and deploy AI/ML models for various applications including Natural Language Processing (NLP), Computer Vision, and Cognitive Computing Design and implement deep learning architectures such as RNN, LSTM, and Reinforcement Learning algorithms Process and analyze diverse data types including text, speech, images, videos, and real-time streams from IoT devices and sensors Collaborate on AI system architecture and design using UML and related tools Utilize AI/ML frameworks such as TensorFlow, PyTorch (Torch), and Caffe for model development and training Apply cognitive search techniques and build scalable AI-driven applications Required Skills: Strong programming skills in Python, with experience in other languages like Java, C/C++, or R Proven experience with AI/ML frameworks: TensorFlow, PyTorch, Caffe, or similar Deep understanding of Deep Learning, Recurrent Neural Networks (RNN/LSTM), and Reinforcement Learning Expertise in Natural Language Processing (NLP) and Computer Vision technologies Experience handling large-scale and multi-modal data from various sources such as text, speech, images, video, and IoT streams Solid foundation in Machine Learning, Cognitive Computing, and Artificial Intelligence principles Preferred Qualifications: Bachelor s or Master s degree in Computer Science, Data Science, Artificial Intelligence, or a related field Experience with data preprocessing, feature engineering, and model evaluation Familiarity with cloud platforms for AI/ML deployment (AWS, Azure, GCP) Work on cutting-edge AI and ML technologies impacting real-world applications Collaborate with a team of experts in a fast-paced, innovation-driven environment Opportunities for continuous learning and career growth in AI/ML domain Qualification : Bachelors or Masters degree in Computer Science, Data Science, Artificial Intelligence, or a related field

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.