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Job Overview As a Hardware Engineer at Qualcomm, you will plan, design, optimize, verify, and test electronic systems including ASICs, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and drive the launch of world-class products. This role involves deep involvement in the micro-architecture development and RTL design process, ensuring high-quality designs that contribute to Qualcomm s cutting-edge technologies. Key Responsibilities Micro-Architecture & RTL Development: Work closely with the Architecture and Systems teams to develop micro-architecture and RTL design. Front-End Design Quality Checks: Perform quality checks on RTL front-end design (e.g., Lint, CDC, low-power checks, Synthesis). Test Plan Development & Debugging: Collaborate with the functional verification team to develop test plans and debug waveforms at the core, sub-system, and SoC levels. Constraint Development & Timing Closure: Hands-on experience with constraint development and achieving timing closure. Design Optimization & Low Power Checks: Ensure designs are PPA (Power, Performance, Area) efficient and perform low power checks. Post-Silicon Debug: Support sub-system, SoC integration, and chip-level debugging. Mentorship: Lead and guide junior engineers in delivering high-quality IPs on schedule. Cross-functional Contribution: Contribute beyond RTL design to support the end product goals in a flexible capacity. Minimum Qualifications Educational Background: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience. Skills & Experience ASIC Design: 7-12 years of experience in ASIC design. Micro-Architecture & RTL Design: Strong knowledge and hands-on experience in micro-architecture development and RTL digital design. Front-End Flows: Exposure to front-end flows such as Lint, CDC, low-power checks, Synthesis. Domain Knowledge: In-depth knowledge of LP/PC DDR 2/3/4/5 and protocols like AXI, ACE, CHI, AHB. Communication Skills: Excellent communication skills, with experience working with global teams. Post-Silicon Experience: Experience in post-silicon bring-up and debug is a plus. Mentorship: Proven experience leading or guiding junior engineers. Flexible Contribution: Must be flexible to contribute beyond RTL design to meet end-product goals.

General Summary: Qualcomm is a global leader in designing and developing advanced semiconductor solutions. We are seeking an experienced CPU Lead Physical Design Engineer to join our world-class team and contribute to the implementation of high-performance CPU designs. You will lead the physical design aspects of next-generation CPU cores, collaborating closely with architecture, RTL, and verification teams to deliver industry-leading solutions. This is an exciting opportunity to work on cutting-edge technology nodes, including 5nm, 3nm, and below, and play a vital role in Qualcomm s advanced CPU product development. Key Responsibilities: Lead and manage the physical design (PD) of high-performance CPU cores from RTL to GDSII. Drive floorplanning, power grid design, and timing closure at block and full-chip levels. Optimize designs for power, performance, and area (PPA) while meeting stringent timing, power, and signal integrity requirements. Collaborate with architecture, RTL, and verification teams to ensure design feasibility and conduct implementation reviews. Ensure delivery of high-quality designs that meet DFT, DFM, and reliability requirements. Perform Static Timing Analysis (STA) and resolve timing violations using industry-standard tools. Drive ECO (Engineering Change Order) implementation to address design issues and ensure successful closure. Mentor and guide junior engineers in physical design methodologies and best practices. Minimum Qualifications: Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience in physical design. A Master s degree is preferred. Proven experience in CPU or high-performance IP physical design at advanced technology nodes (7nm, 5nm, or 3nm). Expertise in place-and-route (PnR) tools such as Synopsys ICC2, Cadence Innovus, or equivalent. Strong understanding of timing analysis, power analysis, signal integrity, and design closure. Experience with physical verification (DRC, LVS) and IR/EM analysis. Proficiency in scripting languages (Tcl, Python, Perl) for design automation. Preferred Qualifications: Knowledge of CPU architecture and microarchitecture. Experience with low-power design techniques such as multi-Vt, power gating, and dynamic voltage scaling. Familiarity with EDA tools for timing, power, and physical verification. Strong leadership and team collaboration skills. Why Join Qualcomm? At Qualcomm, you ll work in a dynamic environment at the forefront of innovation. We offer: Continuous learning opportunities. Flexible working arrangements. Collaboration with some of the brightest minds in the industry. Join us and help shape the future of high-performance computing!