TCL Jobs in Noida

Job Title: Principal Engineer/Manager - CAD General Summary: As a global technology leader, Qualcomm is committed to driving innovation, enabling next-generation experiences, and shaping a smarter, more connected world. Our engineers work on cutting-edge technologies to design, optimize, and verify complex electronic systems, including digital, analog, RF, and optical circuits, FPGA, DSP, and advanced SoCs. We are seeking an experienced Principal Engineer/Manager to lead our CAD team in Noida. This role involves managing a team of 20+ CAD engineers, driving the development of state-of-the-art tools, flows, and methodologies, and ensuring Qualcomm's continued success in designing the industry s most advanced SoCs on leading-edge process nodes. Key Responsibilities: Leadership & Management: Oversee all CAD functions in Noida, covering front-end and RTL-to-GDS (RTL2GDS) tools. Lead and mentor a high-performing team of CAD engineers. Collaborate with global CAD teams to define and implement best practices. Tools, Flows & Methodologies Development: Drive the development and enhancement of EDA tools, workflows, and methodologies. Define and implement strategies to improve RTL, Design Verification (DV), synthesis, PnR, and signoff methodologies. Introduce innovative solutions to enhance design efficiency and quality. Cross-Team & Vendor Collaboration: Act as the primary interface between Qualcomm execution teams in Noida and global stakeholders. Build and manage relationships with EDA vendors, ensuring alignment with Qualcomm s roadmap. Stay ahead of emerging industry trends and technologies to maintain a competitive edge. Required Qualifications: Experience: 15+ years of experience in CAD tool/flow/methodology development in RTL, DV, synthesis, PnR, or signoff. A proven track record of driving innovation in EDA tools and design methodologies. Previous experience managing a medium-sized team with a focus on leadership and technical mentorship. Education: Preferred: Master s degree in VLSI or Computer Science. Minimum: Bachelor s degree in Electronics, Electrical Engineering, or Computer Science. Work on groundbreaking technologies and contribute to next-generation SoCs. Be part of a global, highly collaborative CAD team. Enjoy a competitive compensation package, career growth opportunities, and professional development programs. Qualification : Bachelors degree in Electronics, Electrical Engineering, or Computer Science

Key Responsibilities IP Development: Work on the development of IPs for next-generation Wi-Fi standards, including 802.11bn and future iterations. Verification: Conduct design verification using HVL (Hardware Verification Language) tools like SystemVerilog, UVM/OVM, and SystemC. Technology Lifecycle: Contribute throughout the technology lifecycle, from IP specification to customer deployments. Debugging: Utilize pre and post-silicon debug expertise to ensure the quality and robustness of the IPs and products. Collaboration: Work closely with cross-functional teams to ensure seamless integration and deployment of the technology. Minimum Qualifications Educational Background: Bachelor's degree in Science, Engineering, or related field, with 2+ years of experience in ASIC design, verification, validation, or related fields, or Master's degree in Science, Engineering, or related field, with 1+ year of experience in ASIC design, verification, validation, or related fields, or PhD in Science, Engineering, or related field. Relevant Experience: 2-6 years of relevant experience in Design, Verification, or Implementation in fields such as microarchitecture, computer arithmetic, circuit design, or process technology. Verification Skills: Solid understanding of OOP (Object-Oriented Programming) concepts. Hands-on experience with SystemVerilog, UVM/OVM, and SystemC for design verification. Skills & Experience Wireless Technology: Familiarity with IEEE 802.11 standards, particularly the upcoming Wi-Fi iterations. Core Areas: Strong fundamentals in areas like microarchitecture, computer arithmetic, circuit design, and process technology. Verification Tools: Proficiency in SystemVerilog, UVM/OVM, and SystemC for designing and verifying complex digital systems. Pre/Post Silicon Debug: Expertise in pre and post-silicon debugging to ensure the quality of the technology. Teamwork: Ability to work collaboratively with cross-functional teams to deliver high-quality products. Why Qualcomm? This role provides an exciting opportunity to work at the forefront of wireless technology development, focusing on the next generation of Wi-Fi standards. At Qualcomm, you will be part of a global leader in the semiconductor and telecommunications industry, contributing to the development of cutting-edge wireless solutions used by millions of consumers worldwide.

General Summary: Qualcomm is a global leader in designing and developing advanced semiconductor solutions. We are seeking an experienced CPU Lead Physical Design Engineer to join our world-class team and contribute to the implementation of high-performance CPU designs. You will lead the physical design aspects of next-generation CPU cores, collaborating closely with architecture, RTL, and verification teams to deliver industry-leading solutions. This is an exciting opportunity to work on cutting-edge technology nodes, including 5nm, 3nm, and below, and play a vital role in Qualcomm s advanced CPU product development. Key Responsibilities: Lead and manage the physical design (PD) of high-performance CPU cores from RTL to GDSII. Drive floorplanning, power grid design, and timing closure at block and full-chip levels. Optimize designs for power, performance, and area (PPA) while meeting stringent timing, power, and signal integrity requirements. Collaborate with architecture, RTL, and verification teams to ensure design feasibility and conduct implementation reviews. Ensure delivery of high-quality designs that meet DFT, DFM, and reliability requirements. Perform Static Timing Analysis (STA) and resolve timing violations using industry-standard tools. Drive ECO (Engineering Change Order) implementation to address design issues and ensure successful closure. Mentor and guide junior engineers in physical design methodologies and best practices. Minimum Qualifications: Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience in physical design. A Master s degree is preferred. Proven experience in CPU or high-performance IP physical design at advanced technology nodes (7nm, 5nm, or 3nm). Expertise in place-and-route (PnR) tools such as Synopsys ICC2, Cadence Innovus, or equivalent. Strong understanding of timing analysis, power analysis, signal integrity, and design closure. Experience with physical verification (DRC, LVS) and IR/EM analysis. Proficiency in scripting languages (Tcl, Python, Perl) for design automation. Preferred Qualifications: Knowledge of CPU architecture and microarchitecture. Experience with low-power design techniques such as multi-Vt, power gating, and dynamic voltage scaling. Familiarity with EDA tools for timing, power, and physical verification. Strong leadership and team collaboration skills. Why Join Qualcomm? At Qualcomm, you ll work in a dynamic environment at the forefront of innovation. We offer: Continuous learning opportunities. Flexible working arrangements. Collaboration with some of the brightest minds in the industry. Join us and help shape the future of high-performance computing!