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Senior Customer Success Engineer I Bangalore (EST Shift, Hybrid) Location: Bangalore, India Work Model: Hybrid (3 days office, 2 days remote) Shift Timing: 8:30 PM 5:30 AM IST (EST hours) About Rubrik s Global Customer Support & Success Team Rubrik s Global Customer Support and Success Organization is dedicated to delivering a world-class post-purchase experience. Our team provides expert post-deployment technical support for a broad spectrum of technologies and cloud platforms. We ensure timely activation and adoption of Rubrik s cutting-edge SaaS data management and security products. As a Senior Customer Success Engineer, you will act as a trusted advisor and primary point of contact for our customers and partners, collaborating closely with cross-functional teams to maximize customer value. In today s data-driven world, Rubrik s Customer Support Team is vital to securing customer data. Our team s deep technical expertise, customer-centric approach, and rapid response capabilities safeguard data availability and integrity, no matter the challenges. Key Responsibilities Deliver enterprise-level technical support via phone, web, email, and chat, handling a wide range of customer inquiries and complex cloud deployment issues. Efficiently manage all levels of support cases from basic questions to advanced technical troubleshooting. Analyze customer problems using structured troubleshooting techniques to identify root causes and implement effective solutions. Independently diagnose and resolve issues within the customer environment, escalating unresolved cases appropriately. Provide expert advice on cloud infrastructure services, best practices, and Rubrik product usage. Troubleshoot and resolve escalated customer issues with urgency and precision. Ensure detailed case documentation and timely issue resolution, maintaining high levels of customer satisfaction. Collaborate with internal teams such as engineering and escalations to facilitate clear communication and problem resolution. Contribute to Rubrik s technical knowledge base by developing guides, FAQs, and deployment documentation. Produce technical designs and documentation related to cloud deployment architectures. Required Experience & Skills 6+ years of experience in enterprise technical support, DevOps, or similar roles with expertise in troubleshooting snapshots, replication, data recovery, cloud deployments, networking, and VMware administration. Strong problem-solving skills with the ability to analyze and resolve complex technical issues. Proficient in VMware, Linux, Kubernetes, Google Cloud Platform, AWS, Azure, Office 365 API, database systems (preferably MS SQL), scripting (Python, Perl), automation, microservices architecture, SaaS platforms, and cloud app management. Hands-on experience with cloud deployment technologies and tools. Ability and willingness to continuously learn and adapt across a broad technology stack. Comfortable reporting bugs and collaborating with engineering to recreate and resolve issues. Bachelor s degree in Computer Science, Engineering, or related field. Rubrik (NYSE: RBRK) is on a mission to secure the world s data. Powered by Zero Trust Data Security and advanced machine learning, Rubrik Security Cloud protects data across enterprise, cloud, and SaaS environments. We enable organizations to maintain data integrity, ensure availability despite adverse conditions, monitor risks continuously, and recover quickly from cyberattacks and operational disruptions. Join us and help shape the future of cloud data management and cybersecurity.

Project Manager InfoSec PMO Location: Bengaluru, India Team: Information Security (PMO) About the Team The Information Security team at Rubrik strengthens company-wide security through technology, process optimization, and education. The team leads efforts in secure software development, data protection, monitoring, response, and compliance with third-party data sharing and governance standards. Role Overview Rubrik is looking for a hands-on, high-impact Project Manager to lead multiple overlapping InfoSec initiatives. You will drive outcomes, not just track progress partnering across InfoSec and business teams to define, prioritize, and execute high-stakes security projects. You ll need to blend PM expertise, strategic thinking, and the ability to adapt to startup-style ambiguity. Key Responsibilities Initiative Leadership Own end-to-end delivery of technical and cross-functional InfoSec projects. Bring stakeholders to alignment on scope, timing, and success criteria. Drive remediation and security maturity through project execution. Planning & Execution Define timelines, dependencies, and priorities for multiple projects. Use tools like Jira, Confluence, and standard PM methodologies (Agile/PMBOK). Report regularly to leadership and escalate risks/blockers proactively. Collaboration & Influence Work with InfoSec leaders to shape and maintain the roadmap. Act as an internal consultant, helping teams improve processes and execution. Influence cross-functional stakeholders with clear communication and practical coordination. Ideal Experience Required 5 8 years of PM experience in SaaS or tech-focused environments. Proven ability to lead cross-functional programs with technical and business scope. Hands-on experience with Agile, PMBOK, or blended methodologies. Strong communicator who thrives in ambiguity and fast-moving environments. Bachelor s degree in InfoSec, IT, Engineering, or Business. Preferred Certifications: PMP, PgMP, CISSP, CISA, or CISM. Experience in Information Security programs or initiatives. Bias for action with startup-level flexibility. Process improvement mindset and servant-leader style. Key Traits for Success Results-oriented: Drives outcomes, not just process. Strategic & hands-on: Can plan at the macro level and execute in the weeds. Problem-solver: Anticipates issues and navigates complexity. Stakeholder-focused: Brings teams together and manages expectations smartly. Security-minded: Passion for growing InfoSec expertise. Rubrik is a leader in Zero Trust Data Security , offering next-gen data protection for enterprises. It s a fast-moving environment where PMs can make a real security impact at scale across cloud, SaaS, and enterprise infrastructure. Qualification : Bachelors degree in InfoSec, IT, Engineering, or Business.

Electrical Principal Engineer FPGA Team Location: Bengaluru, India Team: Electrical Engineering Company: Dell Technologies Role Overview As a Principal Electrical Engineer, you will contribute to the architecture, design, and validation of FPGA-based hardware systems for Dell s next-generation enterprise servers. This role involves working across global teams to deliver robust, scalable, and efficient PCBA (Printed Circuit Board Assembly) and logic solutions that align with industry standards and internal requirements. Key Responsibilities Architect and design next-gen hardware features in collaboration with front-end teams and partners. Analyze and recommend trade-offs in design features and costs. Guide global teams with best practices in electronic hardware design. Own and deliver system interfaces and support cross-functional development efforts. Create comprehensive documentation for testing and validation. Essential Requirements 8 12 years of experience in FPGA hardware verification using Verilog, SystemVerilog, VHDL. Expertise in UVM, ABV (Assertion-Based Verification), code coverage, and unit-level simulation. Knowledge in digital design methodologies: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Static timing analysis Experience with x86 or ARM architectures. Familiarity with peripheral protocols: I2C, I3C, SMBus, IPMI, IPMB. Strong background in both analog and digital design. Understanding of hardware/software co-design and debugging complex systems. Desirable Qualifications Experience with Intel/AMD x86 and ARM-based systems. Hands-on with FPGA tools: Xilinx, Lattice, Altera Quartus, ModelSim/QuestaSim. Passion for mentoring and knowledge sharing. Dell Technologies offers a collaborative and innovative environment where hardware engineers work at the forefront of industry advancements. You'll be empowered to lead cutting-edge hardware projects, influence product design, and make a lasting impact on the future of enterprise technology.

Job Title: Global Solutions Partner Manager Location: Madhavanagar, Bengaluru, KA 560001 Mode of Work: At Office Experience: 10 to 20 years No. of Positions: 1 Department: Business Industry: IT Services, Utilities, Telecom, Energy About the Role: We are seeking a highly skilled Global Solutions Partner Manager to focus on establishing and nurturing strategic partnerships in the Utilities sector in India, particularly in Power, Telecom, Water, Gas, Oil, and related domains. The role will require building a network of organizations in the US and Europe who wish to establish design, service, and backend centres in India, while also partnering with System Integrators (SIs) globally who serve the Utilities vertical. This is an exciting opportunity to drive global partnerships, manage client relationships, and contribute to the growth of Pixel s solutions within the industry. Key Responsibilities: Scouting and Partnering: Identify and sign up US/Europe-based companies in the Utilities, Telecom, Broadband, Power, Water, Oil, Gas sectors to transfer their backend work to Pixel in India. Develop strategic partnerships with key players to deliver Network design, process, and delivery services. Global Solutions Delivery: Work with US companies to deliver their Utilities-based solutions in India. System Integrator (SI) Partnerships: Partner with Indian and global IT services companies (SIs) and advisory consultants, managing delivery and partial design of Utilities/Telecom/Broadband/Power accounts and projects. Market Research and Business Development: Collaborate with the Business Excellence and Market Research teams to identify global partnership opportunities. Develop and execute go-to-market strategies for these partnerships. Revenue Growth and KPIs: Drive a revenue goal by developing a defined partner ecosystem. Manage weekly/monthly KPIs/OKRs to ensure the achievement of partnership and revenue targets. Collaboration with Internal Teams: Work closely with internal teams (Sales, Marketing, Product Development) to create joint business plans, strategies, and promotional activities with partners. Training and Support: Develop training materials, presentations, and resources to enable partners to sell and implement Pixel s solutions effectively. Risk Management and Compliance: Ensure all partnerships align with corporate policies, legal requirements, and regulatory standards. Identify and manage potential financial, legal, and operational risks related to partnerships. Industry Relationship Management: Leverage existing relationships with US-based companies providing Utilities services and consulting projects. Build relationships with Indian MNC System Integrators and IT service companies. Skills and Requirements: Qualification: Bachelor s degree in Business, Marketing, Research, or a related field. An MBA is a plus. Experience: 10 to 20 years of experience in partnership management, business development, or related roles within the tech, consulting, or corporate solutions sector. Proven track record in Utilities/Telecom/Broadband/Power sectors, especially with US-based companies. Strong existing relationships with US-based companies looking to outsource Utilities/HFC design projects to India is a must. Experience partnering with Indian MNC System Integrators and IT service companies is a plus. Industry Knowledge: Strong familiarity with the global Utilities landscape and relevant technologies. Knowledge of the latest trends in GIS, Telecom, and Utilities sectors. Skills: Analytical Skills: Ability to analyze market data, understand industry trends, and make informed, data-driven decisions. Communication and Interpersonal Skills: Excellent presentation, negotiation, and relationship-building skills. Problem-Solving: Ability to address and resolve issues quickly and efficiently. Attention to Detail: Ensuring no aspect of partnership or delivery is overlooked. Additional Requirements: Ability to think strategically and execute tactically. Proactive mindset with a focus on achieving both short-term and long-term business goals. Fluency in communication strong written and verbal English skills to manage relationships effectively. Why This Job Might Be for You: You enjoy solving complex challenges and developing creative, actionable solutions. You are detail-oriented and committed to delivering the highest quality solutions, ensuring no task goes unaddressed. You thrive in fast-paced environments, are adaptable to changes, and can quickly learn new things. You re highly motivated, proactive, and always looking for new ways to make an impact. You have a proven ability to communicate clearly, whether in writing or speaking, and can explain complex technical concepts to various stakeholders. Additional Information: Location: Madhavanagar, Bengaluru, KA 560001 No. of Positions: 1 Department: Business Employment Type: Full-time Work Mode: At Office Seniority Level: Senior Qualification : Bachelors degree in Business, Marketing, Research, or a related field.An MBA is a plus.

Job Title: Principal SDET Location: Bangalore (On-site; full-time) About Locus: At Locus, we are redefining logistics decision-making with deep-tech solutions that drive efficiency, consistency, and transparency across industries like retail and FMCG/CPG. Founded in 2015 by Nishith Rastogi and Geet Garg, Locus has evolved from a women s safety geo-tracking app into a globally recognized logistics optimization platform. Our technology has empowered enterprises such as Unilever and Nestl to execute over a billion deliveries across 30+ countries. Guided by our commitment to innovation and sustainable growth, we transform complex supply chains into strategic growth enablers. Join us at Locus and be part of a team shaping the future of global logistics. Job Overview: About the Role As a Principal SDET at Locus, you will play a critical role in driving the quality and reliability of our platform. This role goes beyond traditional testing; you will design, develop, and enhance automated test frameworks, ensure seamless integration of quality engineering practices, and mentor team members to establish a quality-first culture. Key Responsibilities: Automation Framework Design and Development: Architect, develop, and maintain robust test automation frameworks for backend, APIs, and frontend components. Ensure the frameworks are scalable, reusable, and aligned with the latest industry standards. Test Strategy and Planning: Collaborate with product managers, developers, and DevOps to define comprehensive test strategies for new features and system enhancements. Own the end-to-end testing lifecycle, from requirement analysis to test case creation, execution, and reporting. Drive better QA practices (In areas Like: defect creation, Capturing scope of feature, Sign offs , matrix of coverage in functional and automation etc) Quality Advocacy and Best Practices: Drive the adoption of best practices in testing, coding standards, and CI/CD processes across teams. Act as a champion of quality by fostering a quality-first mindset and instilling a culture of rigorous testing. Test Execution and Debugging: Conduct functional, performance, and security testing, ensuring the product meets the highest quality standards. Debug complex issues and work closely with developers to identify and resolve root causes. Continuous Improvement: Analyze test results and metrics to identify areas for improvement in testing processes and product quality. Contribute to the development and enhancement of monitoring and alerting systems to proactively address production issues. Mentorship and Collaboration: Mentor and guide junior SDETs and quality engineers, sharing knowledge and expertise to elevate the team s capabilities. Collaborate effectively with cross-functional teams to ensure quality is integrated into every stage of the development process. Develop a good understanding of velocity in teams and across the org and work towards removing roadblocks to improve release velocity Qualifications: 5-8 years of experience in software testing, with at least 3 years focused on test automation. Proficiency in programming languages such as Java, Python, or JavaScript. Hands-on experience with test automation tools and frameworks for Web and API automation like Selenium, Appium, TestNG, JUnit, or similar. Exp of working on any AI enabled testing tools or frameworks is a plus. Expertise in API testing and automation using tools like Postman, RestAssured, or equivalent. Familiarity with performance testing tools such as JMeter or Gatling. DevOps and CI/CD: Experience with CI/CD pipelines using tools like Jenkins, GitLab CI/CD, or GitHub Actions. Knowledge of Docker, Kubernetes, and cloud platforms (AWS, GCP, or Azure) is a plus. Strong debugging skills and the ability to identify root causes of issues quickly. Excellent communication, collaboration, and leadership skills. Experience in testing large-scale, distributed systems. Knowledge of security testing and tools like OWASP ZAP or Burp Suite. Exposure to machine learning models and their testing challenges. Join Locus and become part of a visionary team that is redefining logistics through innovation and smart distribution. We provide competitive compensation, comprehensive benefits, and a collaborative environment where your expertise will drive both your growth and that of the organization. Locus is an equal opportunity employer dedicated to creating a diverse and inclusive workplace.

Senior Custom Standard Cell Design Engineer Company Arm Location India Job Overview The Solutions Engineering Physical IP team at Arm is home to some of the industry s top experts in deep submicron circuit design. This role offers an exciting opportunity to work with the custom standard cell design engineering team, contributing to cutting-edge technologies. Your work will have a long-lasting impact, as these designs will power Arm s Solutions Engineering products across infrastructure, client, automotive, and IoT market segments. Responsibilities Develop Arm custom standard cells in leading-edge sub-3nm process technology nodes. Collaborate closely with physical design engineers to co-optimize circuit and layout for improved Performance, Power, and Area (PPA) in Arm cores integrated into world-class SoCs. Work with mask design teams to provide optimally tuned layouts. Characterize and model all standard library views. Validate standard cells using comprehensive QA flows across various EDA tools. Required Skills and Experience Bachelor s degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Master s degree in Electrical Engineering with 6+ years of relevant circuit design experience. Proven experience identifying, designing, and verifying cells to optimize core and SoC level PPA. Deep understanding of MOSFET electrical characteristics, transistor-level device physics, and PPA trade-offs, especially at 3nm and below technology nodes. Expertise in designing static circuits, including state-retaining elements such as latches and flip-flops. Hands-on experience with standard cell characterization, modeling, and QA processes. Experience with standard cell characterization tools and SPICE circuit simulators. Proficiency in scripting languages such as Perl or Python. Strong interpersonal skills, with a willingness to mentor and support team members. Demonstrated problem-solving ability, persistence, and creativity in tackling difficult technical challenges. Positive team-oriented attitude, showing respect for all team members. Motivation to continuously develop new skills and take on various responsibilities. Ability to analyze complex data sets and present conclusions effectively. Nice-to-Have Skills and Experience Experience leading engineering teams, including project management and risk communication. Exposure to physical design implementation flows and sign-off processes. What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, meritocratic, and open workplace, Arm empowers every team member to grow, succeed, and make a meaningful contribution to the company's global success. #LI-KR2 Qualification : Bachelors degree in Electrical Engineering with 8+ years of relevant circuit design experience, or Masters degree in Electrical Engineering with 6+ years of relevant circuit design experience.

CPU Verification Engineer Company Arm Location Bengaluru Job Overview Responsibilities Contribute technically as part of project teams to deliver high-quality ARM CPU designs. Execute comprehensive CPU design verification, focusing on improving design quality through stress testing and bug identification. Effectively plan, conduct reviews, provide status updates, and meet delivery expectations. Collaborate with design and architecture teams to ensure effective coverage and provide accurate project planning inputs. Design and develop verification testbenches and components required for effective verification. Maintain knowledge of company processes to work effectively within defined standards and methodologies. Drive efficiency improvements in verification tools and methodologies and mentor team members to support career development. Required Skills and Experience 3+ years of experience in CPU, IP, or SoC product development environments. Experience in design verification/validation, including developing test plans, testbenches, and executing measurable verification processes. Familiarity with processor verification using assembly language and C/C++. Knowledge of microprocessor and/or SoC architecture and microarchitecture, preferably ARM processors and ARM-based systems. Strong problem-solving and debugging skills, with a commitment to continuous improvement. Nice-To-Have Skills and Experience Strong understanding of CPU architecture and microarchitecture. Experience with ARM-based system designs and hierarchical memory systems. Programming languages: Verilog, Assembly, C/C++, Perl, Python. Experience with verification languages such as SystemVerilog. Familiarity with power-aware verification methodologies. What Arm Offers This is a fantastic opportunity to shape the future of CPU verification at Arm while advancing your own career. Join our CPU design verification team and play a key role in delivering Arm's strategic goals! #LI-KR2

Job Description: As a Staff Engineer in Arm's Solutions Engineering group, we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance, and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools, and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design, and implementation of CPU cores, system interconnect, and other Arm IP. Analyze design timing, area, and power to help improve the quality of Arm IP. Develop and deploy new methodologies to improve implementation efficiency and results. Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience: Bachelor s or Master s degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields. 8+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM, and Physical verification. Possess a high level of dedication, initiative, and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies, and promoting their use with international teams. Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Experience working closely in top and block-level Synthesis, Floorplanning, Place and Route, CTS, logical and physical optimization, timing closure, and power analysis flows. Proven programming and scripting skills (e.g., Tcl, Perl, and R). Nice To Have Skills and Experience: Knowledge around Arm-based SoCs! Experience with a wide range of programming, scripting & data presentation languages (e.g., Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, and Ruby). Experience with low-power design techniques (power gating, voltage/frequency scaling). Experience with Verilog RTL design. Experience with ATPG tools and/or production testing. In Return: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate on the basis of any characteristic. #LI-KR2 Qualification : Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering, or other relevant technical fields.

Job Title: Site Reliability Engineer (SRE) Cloud Platform & Production Pipeline Initiatives Location: Bangalore, India (Office-based role) About Couchbase: As industries race to embrace AI, traditional database solutions fall short of rising demands for versatility, performance, and affordability. Couchbase is leading the way with Capella, the developer data platform for critical applications in our AI-driven world. By uniting transactional, analytical, mobile, and AI workloads into a seamless, fully managed solution, Couchbase empowers developers and enterprises to build and scale applications with unmatched flexibility, performance, and cost-efficiency from cloud to edge. Trusted by over 30% of the Fortune 100, Couchbase is unlocking innovation, accelerating AI transformation, and redefining customer experiences. Come join our mission! Job Overview: As a Site Reliability Engineer (SRE), you will play a pivotal role in managing, optimizing, and maintaining Couchbase s cloud infrastructure for Capella, our Database as a Service (DBaaS) platform. You will be responsible for ensuring the reliability and performance of our cloud service while collaborating closely with engineering teams to improve deployment pipelines, security practices, and overall system health. You will work across cloud platforms and multiple tools to provide guidance, mentorship, and contribute to the strategic direction of cloud operations. Responsibilities: Infrastructure Management: Manage, monitor, and maintain the infrastructure for Capella to ensure reliable operations. Security & Compliance: Implement and manage cloud environments in accordance with company security guidelines, including vulnerability management, penetration testing, and compliance requirements (SOC 2, PCI-DSS, GDPR, HIPAA, etc.). CI/CD & Release Pipeline: Collaborate with engineering teams to optimize CI/CD processes, aiming for a highly resilient deployment strategy, ideally with zero downtime. Cloud Optimization: Stay up-to-date with new technologies and industry trends to continuously improve cloud platform architecture and meet the evolving needs of the business. Security Integration: Work with development teams to integrate security scanners within the DevOps lifecycle, enhancing security posture. Leadership & Mentorship: Provide guidance on architecture, code reviews, and technical feedback to improve service reliability, security, cost, and performance. Incident Management: Demonstrate exceptional problem-solving skills, proactively identifying and addressing potential issues before they affect business operations. Collaboration: Partner with development teams, application owners, and stakeholders to integrate best practices and ensure seamless service delivery. Requirements: Experience: 5+ years in Site Reliability Engineering (SRE), DevSecOps, or similar roles, with significant experience working in public cloud environments. Programming & Scripting: Proficiency in languages such as Go, Python, Java, or Ruby. Linux Expertise: High proficiency with Linux operating systems. Kubernetes Management: Experience in managing and maintaining Kubernetes clusters (both self-managed and managed platforms like AWS EKS). Security & Vulnerability Management: In-depth knowledge of security tools and practices (vulnerability management, pen testing, SCA, DAST, SAST), with hands-on experience using tools like Sysdig, Synk, and Blackduck. Cloud Platforms & Tools: Strong experience with cloud platforms (AWS, GCP, Azure) and open-source tools like Artifactory, Jira, Jenkins, Grafana, Prometheus, Datadog, Thanos, etc. Configuration Management: Proficiency with Terraform, Git, and CI/CD platforms (e.g., CircleCI, GitHub, Spinnaker). Networking Security: Solid understanding of TCP/IP, DNS, HTTP, Firewalls, VPNs, and other networking security concepts. Preferred Skills: Availability & Reliability: Knowledge of SLO/SLA, availability, reliability, and performance concepts. Incident Management: Experience with on-call rotations and incident management. Database Experience: Familiarity with databases, particularly Couchbase. Security Certifications: Relevant certifications in security or cloud technologies are a plus. Couchbase reimagines database technology to deliver a fast, flexible, and affordable cloud database platform, empowering developers to build applications with exceptional customer experiences. Trusted by over 30% of the Fortune 100, Couchbase drives innovation and customer success through its Capella platform. Benefits at Couchbase: Generous Time Off Program: Flexibility to care for yourself and your family. Wellness Benefits: Access to world-class medical plans, dental, vision, life insurance, and employee assistance programs. Financial Planning: RSU equity program, ESPP, retirement planning, and business travel insurance. Career Growth: Focused on your career development and success. Fun Perks: Ergonomic and comfortable office setup, food & snacks for in-office employees, and more!

Job Title: Pre-Silicon Validation Engineer SoC/IP Job Description: Join the Devices Development Group (DDG), one of Intel s premier System-on-Chip (SoC) design teams, driving innovation in future Intel SoCs and IPs. As a Pre-Silicon Validation Engineer, you will be part of a dynamic team responsible for ensuring the functionality, performance, and reliability of Intel s cutting-edge designs. Key Responsibilities: Validate IP blocks or features at the SoC level, ensuring compliance with design specifications. Develop validation plans and test strategies based on architectural specifications, RTL code, and existing test methodologies. Analyze microarchitecture and debug failures to identify root causes and improve design quality. Develop and utilize various debugging and validation tools to implement validation plans effectively. Participate in silicon debugging, identifying issues and enhancing testing methodologies for future RTL models. Collaborate with IP providers and internal customers to define, develop, and deliver essential infrastructure while addressing issues identified during execution. Qualifications & Requirements: Educational Qualifications: Bachelor s (B.Tech/BS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 5+ years of experience, OR Master s (M.Tech/MS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 3+ years of experience. Technical Skills & Experience: Minimum 2 years of experience in IP or SoC development, verification, or integration using SystemVerilog and UVM (Universal Verification Methodology). Minimum 2 years of experience in writing validation plans and developing software to execute those plans. Minimum 2 years of experience with object-oriented programming languages. Minimum 2 years of experience working with SystemVerilog and UVM. Minimum 1 year of experience with UNIX/Linux environments. Exposure to Graphics Verification and/or Security Verification is a plus. Preferred Qualifications: Minimum 1 year of experience with computer architecture. Minimum 2 years of experience in validation or testing, particularly in silicon design teams. About the Client Computing Group (CCG): The Client Computing Group (CCG) is at the forefront of Intel s PC product and platform development, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. Through strategic partnerships across the industry, CCG delivers innovative computing experiences that empower users to create, connect, and collaborate. As Intel s largest business unit, CCG drives innovation, scalability, and IP development, helping the company fulfill its mission of enriching lives through technology. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, which includes: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development opportunities to support career growth.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Description Intel is seeking an enthusiastic, motivated, and self-driven engineer specializing in Power Analysis and Signoff. This role involves working on power and performance optimization for complex multi-million gate SoCs, collaborating across teams to ensure low-power design efficiency and successful tape-out. Key Responsibilities: Define and analyze chip power & performance targets. Perform FSDB analysis for various design power scenarios and extract optimal activity windows. Conduct power estimation and analysis at block level and aggregate total power for SoC. Collaborate with architecture, design, and implementation teams for power optimization. Execute low-power (LP) checks at both block and full-chip level, analyze logs/reports, and ensure high-quality results. Work closely with Front-End (FE) and Back-End (BE) teams to achieve overall power convergence and low-power signoff for tape-out. Qualifications & Experience: Educational Requirements: B.E/M.E in Electrical Engineering or a related field. 8+ years of experience in logic design, synthesis, and low-power design/implementation for complex SoCs. Technical Expertise: Proficiency in power analysis tools such as PT-PX/Prime Power. Experience with FSDB analysis using Verdi tool. Knowledge of Power Artist for power analysis (a plus). Hands-on experience with industry-standard LP check tools like PTPX for power estimation. Strong analytical and problem-solving skills. Scripting expertise in Tcl, Perl, and Python (required). About the Xeon and Networking Engineering (XNE) Group: The Xeon and Networking Engineering (XNE) Group focuses on the development and integration of Xeon and Networking SoCs, supporting Intel s Xeon and 5G networking roadmap. XNE drives high-performance computing innovations while ensuring power efficiency and scalability. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : B.E/M.E in Electrical Engineering or a related field.

Job Title: Senior ATE Test Engineer Manufacturing & Product Engineering Job Description: Intel is seeking a Senior ATE Test Engineer to drive the testability and manufacturability of integrated circuits from feasibility to high-volume production (HVM). The role involves developing and validating test methodologies, debugging functionality and performance issues, and optimizing test processes for yield and cost efficiency. The engineer will work closely with design, process development, fab, assembly, and manufacturing teams to ensure seamless production ramp-up and quality assurance. Key Responsibilities: Test Development & Debugging: Design, develop, and validate testability circuits and test flows for new products. Debug functionality and performance issues to root cause using Automatic Test Equipment (ATE). Interface with design, DFx (Design for Test, Debug, Manufacturing), and product teams to drive test development. Manufacturability & High-Volume Ramp (HVM): Collaborate with fab, assembly, test factories, and quality/reliability teams to enable smooth production ramp-up. Perform ATE device characterization, define datasheet specifications, and conduct yield analysis. Analyze early customer returns and drive test hole closure activities to enhance quality and reliability. Production Test Optimization: Drive test time reduction by analyzing fallout data and balancing product cost optimizations. Implement bin split and die-level cherry-pick (DLCP) strategies to optimize product supply. Ensure manufacturability through process and spec corner analysis to resolve yield issues before mass production. Hardware & Software Development: Develop and debug complex software programs for test conversion and test automation. Create and validate test hardware solutions for production testing. Optimize component production relative to quality and cost constraints. Qualifications & Experience: Educational Requirements: B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields. Technical Expertise: ATE Test Engineering: Strong expertise in Automatic Test Equipment (ATE) development and debug. DFT & Test Methodologies: Knowledge of DFT architectures and methodologies including Analog DFT, JTAG, etc. Understanding of test engineering processes and tester debugging techniques. Debugging & Validation: Hands-on experience with design/validation and advanced debugging skills. Expertise in Advantest 93K, Teradyne Ultraflex, J750, and related test platforms. Manufacturing Process & Yield Analysis: Experience in yield analysis, bin splitting, and test time optimization. Ability to analyze process corners and drive manufacturing readiness. Soft Skills: Excellent problem-solving skills, teamwork, and communication. Strong interpersonal and planning skills for cross-functional collaboration. About Intel s Manufacturing & Product Engineering (MPE) Group: The MPE team is responsible for test development across Intel s product segments, contributing to 95% of Intel s revenue. The team delivers pre-production test suites and physical debug capabilities to enable high-quality, high-volume manufacturing. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates. Intel offers a competitive compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive health, retirement, and vacation benefits. Cutting-edge technology and career growth opportunities. Qualification : B.Tech/M.Tech in Computer Science, Electrical, or Electronics Engineering or related fields.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Own the micro-architecture and RTL development of design modules for PCI Express Controllers. Micro-architect features to meet performance, power and area requirements. Work with HW and system architects to define critical features. Help verification teams to verify the correctness of implemented features. Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Enable FPGA and software teams to prototype the design and ensure that software is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 3+ years of design experience. Experience in micro-architecture and RTL design of complex units. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in High Speed IO controllers like PCI Express. Good knowledge of PCI Express Protocol - Gen 3 and above. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a teammate. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid Qualification : BS / MS or equivalent experience.

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology and amazing people. We seek a Senior Power and Thermal Engineer to join our dynamic and fast-paced Silicon Solution Group. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers a unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working, and creative individual to architect and productize next generation power and performance controllers. What You Will Be Doing: Responsible for architecting, developing, characterization of next generation power and thermal management features and solutions working with multi-functional teams across the company. Drive methodologies for deployment of features into products. Drive initiatives for power and thermal optimizations spanning across silicon, platform, software, manufacturing, and product systems; for products ranging from largescale datacenters to low-power client devices. Debug and architect solutions for issues seen by customers in the field across a wide range of industries. Influence next generation SW, chip, board, and platform design of products across SOC, GPU and CPUs in Laptops, Servers, and Datacenters Work alongside system architects, designers, chip and board designers, software/firmware engineers, HW/SW applications engineering, process/reliability authorities, ATE engineers, and silicon operations, in a fast-paced, high-energy, collaborative work environment to bring industry-defining products to market. What We Need to See: B. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience) 4+ years of experience in silicon bring-up, validation, and productization. Experience with power and thermal controllers and management. Expertise and deep understanding in the areas of silicon power, transistor/device physics, power modeling and measurement, active power management is a plus Proficiency in Python, Perl or C programming languages. Self-starter with strong skills in multi-tasking, influencing, communication, presentation, and consensus-building Enthusiastic, responsive, and keen on process improvement With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Qualification : B. Tech or M. Tech in Electronics Engineering, Computer Science, or related field (or equivalent experience)

About NVIDIA NVIDIA has continuously reinvented itself. From inventing the GPU, which sparked the growth of the PC gaming market and redefined modern computer graphics, to revolutionizing parallel computing, NVIDIA remains at the forefront of technological innovation. Today, NVIDIA GPUs power the world's most advanced AI research, providing highly scalable and massively parallel computational power. Join us and become part of a diverse, inclusive environment that encourages innovation and empowers everyone to do their best work. NVIDIA is an equal opportunity employer, and we are committed to building a diverse team and supporting your growth and success. About the Role DFT Engineer The Design-for-Test (DFT) Engineering team at NVIDIA is at the cutting edge of innovation, solving complex challenges in DFT architecture, verification, and post-silicon validation for some of the most advanced semiconductor chips in the industry. We are looking for a passionate DFT engineer to join our team and help shape the future of technology. What You ll Be Doing Design and implement state-of-the-art DFT features, including test access mechanisms, IO BIST, memory BIST, and scan compression. Verify and validate Scan ATPG and other DFT features, both in simulation and during silicon bring-up. Develop and deploy DFT methodologies for next-generation products, continuously improving DFT quality and efficiency. Collaborate with cross-functional teams to integrate DFT features into the overall chip design. Occasionally participate in travel and late-hour online meetings during critical project milestones. What We Need to See BSEE or MSEE from a reputable institution or equivalent experience. 2+ years of experience in DFT, ASIC design, or a related field. Strong understanding of static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design. Experience in RTL and gate-level verification and simulation. Familiarity with BIST architecture, JTAG, and IEEE standards (1149.1/1500). Proficiency in Scan ATPG, compression techniques, and memory tests. Strong analytical and problem-solving skills. Scripting knowledge (Perl or Python) is essential. At NVIDIA, you'll have the opportunity to work on world-changing technology, be part of a diverse and innovative team, and experience continuous learning and growth. We strive to foster a culture of creativity, collaboration, and excellence in everything we do. #LI-Hybrid Qualification : BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

Meet the Team Join the Cisco Silicon One team in shaping the future of networking with a unified silicon architecture designed for web-scale and service provider networks. Cisco s silicon team offers a unique experience for ASIC engineers by combining the extensive resources of a large, multi-geography organization with the dynamic startup culture and growth opportunities typically found in a smaller team. Enjoy the benefits of a large campus that includes on-site amenities such as a gym, healthcare, caf , social interest groups, and philanthropy initiatives, all while working in a collaborative and innovative environment. Your Impact Write detailed micro-architecture specifications and actively participate in design reviews. Implement Verilog RTL to meet stringent timing, performance, and power requirements. Contribute to full-chip integration and collaborate on timing methodology and analysis. Develop and analyze functional coverage to ensure quality and completeness. Help define, evolve, and support our design methodology to maintain high standards. Collaborate with the verification team to address design bugs and improve code coverage. Work closely with the physical design team to resolve design timing and place-and-route issues. Perform triage, debugging, and root cause analysis for simulation, software bring-up, and customer failures. Conduct diagnostic and post-silicon validation tests in the lab to ensure product readiness. Minimum Qualifications: Bachelor s or Master s degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design. Expertise in Verilog or System Verilog programming. Experience with simulation, synthesis, static timing constraints, and related tools (e.g., VCS, DC, PrimeTime). Solid understanding of debugging and verification methodologies. Preferred Qualifications: Understanding of networking technologies and concepts. Scripting experience with Python, Perl, TCL, or shell programming. Familiarity with formal verification tools. Experience with emulation techniques. #WeAreCisco At Cisco, every individual brings their unique skills and perspectives together to pursue our mission of powering an inclusive future for all. Our employees' passion for connection drives our culture of diversity, learning, and growth. With a focus on unlocking potential, Cisconians often experience one company, many careers, where learning and development are encouraged and supported at every stage of their career. Our technology, tools, and culture pioneered hybrid work trends, allowing every individual to perform at their best and be their authentic self. One-third of Cisconians participate in our 30 employee resource organizations, called Inclusive Communities, which foster belonging, allyship, and social impact. Cisco also provides 80 hours of paid volunteer time off each year, and nearly 86% of employees take part in giving back to the causes they care about. At the heart of Cisco s success is our people, driving us to be the worldwide leader in technology that powers the internet. We are committed to helping our customers reimagine their applications, secure their enterprises, transform their infrastructures, and achieve their sustainability goals. Join us and be a part of a forward-thinking company dedicated to creating a more inclusive future for all. Qualification : Bachelors or Masters degree in Electrical or Computer Engineering with 7+ years of experience in ASIC design.