Verification Environments Jobs in Bengaluru

Functional Safety Engineer Location: Bangalore Experience: 3 6 Years Education: B.E / B.Tech / M.E / M.Tech in Electronics, Electrical, Computer Science, or a related field Job Summary We are seeking a skilled and motivated Functional Safety Engineer to join our automotive embedded systems team. The ideal candidate will have hands-on experience with ISO 26262, strong embedded C programming knowledge, and a solid understanding of the software development lifecycle. This role is critical in ensuring that all safety-critical systems are developed in compliance with industry safety standards and regulations. Key Responsibilities Develop and maintain the Functional Safety Management System (FSMS) in line with ISO 26262 standards. Conduct hazard analysis and risk assessments (HARA) for automotive embedded systems. Define, allocate, and manage functional and technical safety requirements across hardware and software components. Support and guide development teams in achieving ASIL (Automotive Safety Integrity Level) compliance. Collaborate with hardware and software teams to ensure safety mechanisms are implemented and validated effectively. Prepare and maintain safety-related documentation, including Safety Plans, Safety Cases, and Safety Analyses (FMEA, FTA, DFA, etc.). Ensure traceability of safety requirements throughout the SDLC, using appropriate tools and processes. Participate in reviews, audits, and assessments to ensure continuous compliance with ISO 26262. Support safety validation and verification activities. Required Skills & Experience 3 6 years of experience in Functional Safety Engineering, with a minimum of 2+ years working specifically with ISO 26262. Proficient in Embedded C programming, with exposure to real-time embedded systems. Strong understanding of the Software Development Life Cycle (SDLC) in safety-critical environments. Good analytical and problem-solving skills. Effective communication and collaboration skills to work with cross-functional teams. Preferred / Added Advantage Experience in the automotive domain (e.g., ADAS, powertrain, or body control modules). Familiarity with automotive communication protocols (CAN, LIN, FlexRay). Exposure to toolchains like DOORS, Polarion, or Jama for requirement and safety management. Knowledge of complementary standards such as ISO 21434 (Cybersecurity) or IEC 61508. Work on innovative and safety-critical projects for global automotive clients. Opportunity to deepen your expertise in functional safety and ISO 26262. Collaborate with a high-caliber team in a technically driven environment. Competitive compensation, learning opportunities, and career advancement paths. Qualification : .E / B.Tech / M.E / M.Tech in Electronics, Electrical, Computer Science, or a related field

Position: RTL Design Engineer Location: Bangalore Education: Engineering Degree in Electronics & Communication (E&C) Experience: 3 to 6 years Job Overview We are seeking a skilled RTL Design Engineer to own the full lifecycle of FPGA design projects from understanding customer requirements to final delivery. You will define DSP, system, and board architecture, partition algorithms between FPGA and software, and lead design, simulation, and verification activities. This role requires hands-on expertise with FPGA technologies, strong problem-solving skills, and the ability to engage closely with customers and production teams. Key Responsibilities Interpret customer requirements, specifications, and tender documents to define system architecture. Take end-to-end ownership of projects including risk assessment, mitigation planning, schedule tracking, and customer discussions. Partition signal processing algorithms for FPGA and software implementation; identify key building blocks. Provide estimates for FPGA resources, computational and memory bandwidth needs. Develop detailed module-level designs including coding, simulation, and peer reviews. Apply design, verification, and validation methodologies rigorously. Prepare and maintain comprehensive project documentation, including design and analysis reports. Support customers during integration and testing phases on-site. Assist production teams with technical support. Define RTL architecture and perform HDL coding, simulation, implementation, board testing, and debugging. Professional Skills & Technical Expertise Proficient in VHDL coding; experience with Verilog or SystemVerilog is a plus. Expertise with Xilinx FPGA devices and associated synthesis and implementation tools. Strong experience in functional simulation and hardware logic design/debugging. Familiarity with FPGA synthesis and place & route (PAR) tools. Experience implementing DSP algorithms in FPGA environments, especially for Radar and Electronic Warfare applications. Skilled in modeling algorithms using MATLAB/Octave, generating test vectors, and data visualization. Working knowledge of interfacing with ADCs and DACs, and analyzing their performance. Good command of configuration and version control tools such as SVN. Excellent communication and presentation skills for technical discussions and customer interactions. What You ll Bring Strong analytical mindset and problem-solving abilities. Ability to work independently and manage multiple tasks effectively. Detail-oriented with a commitment to high-quality design and documentation. Collaborative attitude to work across teams and customer sites. Qualification : Engineering Degree in Electronics & Communication (E&C)

Job Title: Robotics Solution Engineer Location: Bengaluru Key Focus Areas: The ideal candidate will have experience and expertise in 40-60% of the following domains: Task Development: Breaking down complex robotic tasks (e.g., pick, orient, place) and designing efficient workflows. Simulation and Validation: Using advanced physics-based simulation tools to model and validate robotic systems and interactions. System Integration: Seamless integration of hardware, software, and sensors tailored to customer environments. Customer-Centric Solutions: Customizing robotic solutions to fit specific customer requirements and constraints. Foundational R&D and ML Development: Supporting research and machine learning algorithm development to enhance robotic perception, autonomy, and decision-making. Roles and Responsibilities: Physics-Based Simulation Development: Develop comprehensive physics-based models for robots, environments, and their interactions. Create and validate dynamic models involving rigid body dynamics, contact physics, material properties, and compliance, especially for multi-arm robotic systems. Build and maintain digital twins of physical robots and real-world environments. Algorithm Development & Implementation: Design, implement, and validate control and motion planning algorithms for multi-arm robots, focusing on manipulation and grasping. Optimize kinematics, dynamics, and force-based control strategies for real-time robotic applications. Support learning-based algorithm implementation for real-time perception and manipulation, including simulation-based testing and validation. Machine Learning Applications: Apply machine learning techniques to robotic perception and decision-making. Implement learning-based algorithms for perception and manipulation tasks. Testing, Validation & Optimization: Develop protocols to validate simulation accuracy by bridging virtual and real-world performance. Create automated test sequences and metrics for robust validation across various scenarios. Analyze simulation results to enhance system performance, safety, and reliability, suggesting design improvements. Collaboration & Cross-Functional Support: Work closely with controls engineers to validate and tune control systems in simulation. Collaborate with algorithm, software, and hardware teams to refine systems and resolve issues. Provide insights from simulation analyses to guide product improvements. Documentation & Reporting: Document simulation approaches, assumptions, and validation outcomes clearly. Prepare detailed reports on system performance, testing results, and optimization opportunities. Skills and Experience: Core Expertise: Advanced physics-based modeling and numerical simulation techniques. Deep understanding of robot kinematics, dynamics, and control theory. Experience with simulation validation and verification methodologies. Sensor modeling for cameras, force/torque sensors, etc. Motion planning algorithm knowledge. Familiarity with machine learning frameworks (PyTorch, TensorFlow) and real-time control implementation. Software & Tools: Experience with physics simulation platforms like NVIDIA Isaac Sim/Omniverse, CoppeliaSim, Mujoco, PyBullet, PhysX, Gazebo, or equivalents. Proficient in Python and C++ for scripting and automation tasks. Comfortable integrating CAD software and managing version control with Git. Engineering & Analysis: Skills in system dynamics modeling and error analysis. Developing test plans and performing root cause analysis. Conducting feasibility studies and model validation. Required Qualifications: Bachelor s or Master s degree in Robotics, Mechanical Engineering, or related fields. Minimum 3 years of professional experience in robotics engineering, with a focus on simulation and modeling. Strong foundation in robot kinematics, dynamics, and control systems. Proficient in Python and C++ programming. Experience with physics engines (PhysX, Bullet, PyBullet) and validating simulation results with real-world data. Preferred Qualifications: Master s or PhD in Robotics, Computer Science, or a related discipline. Hands-on experience with NVIDIA Isaac Sim/Omniverse or similar simulation platforms. Background in computer graphics, sensor modeling, and digital twin technologies. Qualification : Bachelors or Masters degree in Robotics, Mechanical Engineering, or related fields.

Electrical Principal Engineer FPGA Team Location: Bengaluru, India Team: Electrical Engineering Company: Dell Technologies Role Overview As a Principal Electrical Engineer, you will contribute to the architecture, design, and validation of FPGA-based hardware systems for Dell s next-generation enterprise servers. This role involves working across global teams to deliver robust, scalable, and efficient PCBA (Printed Circuit Board Assembly) and logic solutions that align with industry standards and internal requirements. Key Responsibilities Architect and design next-gen hardware features in collaboration with front-end teams and partners. Analyze and recommend trade-offs in design features and costs. Guide global teams with best practices in electronic hardware design. Own and deliver system interfaces and support cross-functional development efforts. Create comprehensive documentation for testing and validation. Essential Requirements 8 12 years of experience in FPGA hardware verification using Verilog, SystemVerilog, VHDL. Expertise in UVM, ABV (Assertion-Based Verification), code coverage, and unit-level simulation. Knowledge in digital design methodologies: CDC (Clock Domain Crossing) RDC (Reset Domain Crossing) Static timing analysis Experience with x86 or ARM architectures. Familiarity with peripheral protocols: I2C, I3C, SMBus, IPMI, IPMB. Strong background in both analog and digital design. Understanding of hardware/software co-design and debugging complex systems. Desirable Qualifications Experience with Intel/AMD x86 and ARM-based systems. Hands-on with FPGA tools: Xilinx, Lattice, Altera Quartus, ModelSim/QuestaSim. Passion for mentoring and knowledge sharing. Dell Technologies offers a collaborative and innovative environment where hardware engineers work at the forefront of industry advancements. You'll be empowered to lead cutting-edge hardware projects, influence product design, and make a lasting impact on the future of enterprise technology.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Requirements: BE/BTech degree in CS/EE with 8+ years experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus. Qualification : BE/BTech degree in CS/EE

About the Job: Join a diverse team at Google dedicated to pushing boundaries and developing custom silicon solutions that power the future of Google s direct-to-consumer products. You will play a crucial role in shaping the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration across the globe. At Google, we combine the best of AI, software, and hardware to create innovative products that are loved by millions worldwide. Our mission is to organize the world s information and make it universally accessible and useful, and we aim to improve lives through cutting-edge technology. As a Senior Digital Design Verification Engineer, your expertise will contribute to the development of highly complex SoCs (System on Chips) and custom silicon solutions, ensuring they meet Google s high standards for performance and reliability. Responsibilities: Verification Planning & Design: Plan the verification of digital design blocks at the Sub-System level. Work closely with design engineers to fully understand the design specifications and identify important verification scenarios. Verification Environments: Create and enhance constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology). You will also leverage formal verification tools and techniques, including SVA (SystemVerilog Assertions), for design validation. Debugging & Collaboration: Work closely with design engineers to debug and identify functional issues in design blocks, ensuring the delivery of functionally correct designs. Cross-functional Collaboration: Collaborate with architecture, design teams, software teams, and other stakeholders to define and execute the overall verification strategy for SoCs. Verification Ownership: Take ownership of functional verification for intellectual property (IP), serving as the primary point of contact for cross-functional teams to resolve issues and ensure a smooth integration process. Quality Assurance: Drive and contribute to the quality assurance process to ensure a high standard of verification and successful delivery of designs. Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent practical experience). 8 years of experience working with verification methodologies and languages such as UVM and SystemVerilog. Proven experience in developing and maintaining verification testbenches, test cases, and environments. Preferred Qualifications: Master s Degree in Electrical Engineering, Computer Science, or a related field (or equivalent practical experience). Experience with low power verification, debugging, Gate Level Simulation (GLS), and formal verification techniques. Track record in successfully leading design verification for IPs, delivering them to multiple SoCs. Proven experience in driving cross-functional teams to ensure quality tape-outs and navigating dependencies with various stakeholders. Strong expertise in driving or owning sub-system level verification and managing all associated complexities. Innovation at Scale: Contribute to building revolutionary hardware and software products used by millions of people across the world. Growth & Learning: Collaborate with world-class engineers and learn from experts in the field. Cutting-edge Technology: Work at the intersection of AI, software, and hardware to shape the future of computing. If you re passionate about digital design verification and eager to contribute to cutting-edge silicon solutions, we d love to hear from you. Join Google s mission to make people s lives better through technology! Google is an equal opportunity employer.

Senior Memory Design Engineer Company Arm Location Noida, India Job Description This opening is for a Senior Memory Design Engineer in our PHYSICAL IP MEMORY group in Noida. We work on innovative memory architectures in leading-edge technology nodes to enable the best Arm Systems across all markets. As a memory design professional, this position is a rare opportunity to work with our successful circuits, characterization, and layout team, and gain a deep understanding of memory usage in SoCs based on Arm cores. You will discover a wide variety of circuit innovations while working on different types of memories in cutting-edge process technologies. Responsibilities In this role, you will be working in the following areas: Work on memory architecture development in the latest technologies. Transistor-level full-custom design and collaboration with the physical design team for layout realization. Develop new design features and perform circuit/layout optimizations to meet Performance, Power, and Area targets. Lead memory design verification and characterization activities. Ensure high-performance memory designs with the lowest possible power, as needed for Arm CPUs, GPUs, and SOCs. Required Skills and Experience 5-8 years of proven experience in memory design. Strong interest and command of basic electronics (Diodes, RC Circuits, CMOS, etc.). Solid understanding of digital electronics fundamentals (Flip-Flops, Latches, Decoders, Multiplexers). Understanding of setup and hold time concepts. In-depth knowledge of memory fundamentals, especially single-port SRAM: Circuit design (Bitcell, WL decoder, Sense Amp, Self-time, Assist, Low power features, DFT features). Good understanding of technology trade-offs in deep sub-micron technologies. Self-motivated, hardworking, and positive outlook. Strong organizational skills with attention to detail. Nice-to-Have Skills and Experience Understanding of advanced process technology nodes and memory product layout implementation. Experience with shell scripting, machine learning (ML), and automation. Knowledge of statistical simulations (e.g., Monte Carlo). What Arm Offers Arm is committed to global talent acquisition and offers an attractive relocation package. With offices worldwide, Arm is a diverse organization of dedicated, creative, and hardworking engineers. By fostering a dynamic, inclusive, and meritocratic workplace where everyone can grow and succeed, we encourage our people to make exceptional contributions to Arm's success in the global marketplace. Accommodations at Arm If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [email protected]. By sending the requested information, you consent to its use by Arm to arrange appropriate accommodations. All accommodation requests will be treated with confidentiality, and information will only be disclosed as necessary to provide the accommodation. Examples of support include breaks between interviews, having documents read aloud, or office accessibility. Hybrid Working at Arm Arm s hybrid working approach is designed to create an environment that supports both high performance and personal wellbeing. We believe in bringing people together face-to-face to enable faster work while recognizing the value of flexibility. Hybrid working patterns depend on team and role requirements, which will be discussed upon application. Some flexibility might be limited by legal, regulatory, tax, or other considerations. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to fostering an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals and do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.

CPU Verification Engineer Company Arm Location Bengaluru Job Overview Responsibilities Contribute technically as part of project teams to deliver high-quality ARM CPU designs. Execute comprehensive CPU design verification, focusing on improving design quality through stress testing and bug identification. Effectively plan, conduct reviews, provide status updates, and meet delivery expectations. Collaborate with design and architecture teams to ensure effective coverage and provide accurate project planning inputs. Design and develop verification testbenches and components required for effective verification. Maintain knowledge of company processes to work effectively within defined standards and methodologies. Drive efficiency improvements in verification tools and methodologies and mentor team members to support career development. Required Skills and Experience 3+ years of experience in CPU, IP, or SoC product development environments. Experience in design verification/validation, including developing test plans, testbenches, and executing measurable verification processes. Familiarity with processor verification using assembly language and C/C++. Knowledge of microprocessor and/or SoC architecture and microarchitecture, preferably ARM processors and ARM-based systems. Strong problem-solving and debugging skills, with a commitment to continuous improvement. Nice-To-Have Skills and Experience Strong understanding of CPU architecture and microarchitecture. Experience with ARM-based system designs and hierarchical memory systems. Programming languages: Verilog, Assembly, C/C++, Perl, Python. Experience with verification languages such as SystemVerilog. Familiarity with power-aware verification methodologies. What Arm Offers This is a fantastic opportunity to shape the future of CPU verification at Arm while advancing your own career. Join our CPU design verification team and play a key role in delivering Arm's strategic goals! #LI-KR2

Job Title: Staff Engineer Embedded Software & Methodologies Job Overview: The Architecture and Technology Group (ATG) at Arm plays a critical role in shaping the future of Arm s architecture roadmap. ATG develops industry-leading secure CPU and system architectures, along with technologies that empower our global ecosystem to build innovative products. As part of this, ATG also creates Architecture Compliance Kits (ACK) a crucial product that ensures CPU implementations adhere to Arm architecture standards. These kits are utilized by both internal and external CPU design teams to validate compliance. The ATG team in Bangalore focuses on developing these ACK products. The Methodology Team, specifically, builds embedded software, methodologies, and tools for the latest Arm cores and system IPs. As a Staff Engineer, you will provide technical leadership and guide junior engineers while actively contributing to product development. You will leverage your software engineering expertise to build scalable, high-quality compliance kits used across Arm s internal teams and external partners. Key Responsibilities: Act as a technical expert, driving the design and development of embedded software, boot flows, and methodologies for architectural compliance. Analyze architecture specifications and define software methodologies that meet industry standards. Provide technical direction to the team while mentoring and guiding junior engineers. Collaborate with cross-functional teams to ensure successful and timely delivery of engineering commitments. Continuously enhance development efficiency through improved methodologies, automation, and process enhancements. Communicate delivery status, technical risks, and mitigation plans effectively to stakeholders. Required Skills & Experience: Bachelor s or Master s degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering. 10+ years of experience in embedded software development, boot flows, firmware development, driver development, or low-level operating system driver development for processors. Strong understanding of software engineering principles, along with excellent analytical, problem-solving, and debugging skills. Strong communication skills both verbal and written with the ability to convey technical information effectively across teams. Self-driven, proactive, and able to take ownership of tasks and responsibilities. Preferred Skills: Familiarity with computer architecture fundamentals, especially Arm or x86 architecture. Proficiency in at least one programming language (C or C++) and one scripting language (Perl or Python). Experience with assembly-level programming. Working knowledge of software verification methodologies, embedded software environments, and toolchains (with preference for GNU toolchains). Join a team that thrives on technical excellence and innovation. Whether it s defining cutting-edge architectures, developing advanced cores, or creating custom physical IPs, Arm offers you a platform to push boundaries and make a lasting impact. Qualification : Bachelors or Masters degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering.

Job Title: Junior 5G RAN Developer Location: Bengaluru, India Experience: 1 to 4 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or equivalent. About Tietoevry At Tietoevry, we are committed to driving innovation in Wireless Telecommunications and shaping the future of connectivity. As part of our global R&D initiatives, we collaborate with industry leaders to develop state-of-the-art solutions for 5G networks. We foster an inclusive and collaborative environment, offering opportunities for growth, learning, and cutting-edge development in next-generation technologies. Role Overview As a Junior 5G RAN Developer, you will play a key role in the design, development, and testing of software components across multiple layers of the 5G NR protocol stack. You will work on gNodeB development, collaborating with global teams in an agile environment, delivering high-performance solutions for future wireless networks. Key Responsibilities Contribute to the development and verification of features within the 5G NR Radio Access Network (RAN), focusing on gNodeB. Develop Low-Level Design (LLD) and implement new features for 5G RAN software, ensuring compliance with 3GPP standards. Collaborate with cross-functional teams, including system integrators, to ensure smooth integration across different RAN components. Analyze and resolve complex issues, including log file analysis and debugging in live environments. Continuously work towards improving system performance and delivering high-quality solutions. Document development processes, test cases, and outcomes comprehensively for future reference. Mandatory Skills & Experience Hands-on experience in LTE/5G NR Layer-1, Layer-2, and Layer-3 protocol software development. Expertise in 3GPP specifications, particularly related to Layer-1, Layer-2, and Layer-3 protocols. Strong understanding of MAC Scheduler and Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Proficiency in C/C++ programming, with experience in software debugging and troubleshooting complex RAN-related issues. Familiarity with Agile methodologies and hands-on experience with Jira and similar project management tools. Experience working with Git, Gerrit, or equivalent version control tools. Prior experience with cloud technologies (e.g., microservices, containers) is an added advantage. Strong communication skills, with the ability to work effectively in a global, multicultural environment. Work on pioneering 5G technology projects in a dynamic, collaborative environment. A global culture built on Nordic values transparency, low hierarchy, respect, and trust. Opportunities for ongoing learning and professional development in cutting-edge technologies. A supportive environment where innovation and work-life balance are actively encouraged. Inclusive workplace where diversity, equity, and inclusion are valued and celebrated. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity drives innovation. We welcome applications from candidates of all backgrounds, genders (m/f/d), and walks of life, fostering an inclusive and inspiring work environment where everyone feels valued and empowered to contribute. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or equivalent.

Job Title: Senior 5G RAN Developer Location: Bengaluru, India Experience: 4 to 8 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline About Tietoevry At Tietoevry, we are at the forefront of 5G innovation, collaborating with global telecom leaders to design and deliver next-generation wireless solutions. Our inclusive, innovation-driven culture offers the perfect platform to work on cutting-edge technologies and contribute to shaping the future of connectivity. Role Overview As a Senior 5G RAN Developer, you will play a critical role in designing, developing, and maintaining 5G NR protocol software components. You will lead the systemization, development, and verification processes for various RAN subsystems, contributing to the development and optimization of gNodeB solutions. This role requires deep technical expertise in 5G RAN Layer 1, 2, and 3, combined with strong architectural insight and a proactive, problem-solving mindset. You will collaborate closely with clients and global teams, provide technical guidance to peers, and help drive innovation in our 5G product portfolio. Key Responsibilities Contribute to product development, maintenance, and delivery, including requirement analysis, high-level design (HLD), low-level design (LLD), coding, and verification of gNodeB. Analyze and prioritize 3GPP features for development across different subsystems. Lead system integration and testing activities in collaboration with client and internal teams. Provide technical leadership by guiding teams on complex design and architectural decisions. Drive continuous performance improvement and ensure quality deliverables. Identify and implement architectural enhancements to optimize product performance and scalability. Document development processes, system designs, and testing outcomes thoroughly. Mandatory Skills & Experience Proven hands-on experience in developing LTE/5G NR MAC Scheduler and Layer-2 protocols. Deep knowledge of 3GPP specifications, particularly across Layer 1, Layer 2, and Layer 3. Strong understanding of Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Experience debugging complex gNodeB issues, including log file analysis and troubleshooting in live environments. Proficiency in C/C++ programming, with experience implementing complex algorithms. Hands-on experience with any of the following features: MAC, RLC, PDCP, Scheduler, Power Control, SPS, TTI Bundling, Link Adaptation, GTP-C, GTP-U In-depth understanding of 3GPP Radio Access Standards, ORAN split architecture, and radio protocol algorithms. Experience in feasibility studies and simulations related to Layer 1/PHY features and packet scheduler algorithms. Experience in software development and systemization for 5G Layer 1/Layer 2/Layer 3 protocols. Strong grasp of Linux OS and optimization techniques using DPDK. Hands-on expertise with version control tools like Git and Gerrit, and project management tools like Jira. Experience working in Agile environments. Preferred Skills Experience with cloud technologies, such as microservices and containers. Exposure to ORAN/Open RAN ecosystems is a plus. Strong analytical mindset with a self-driven and proactive approach. Soft Skills Excellent communication skills, with the ability to work in a dynamic, multicultural environment. Strong collaboration skills to work closely with cross-functional teams across geographies. Ability to mentor and guide junior developers, fostering knowledge sharing within the team. Opportunity to work on cutting-edge 5G technology projects in collaboration with global telecom leaders. A Nordic-inspired culture based on trust, transparency, respect, and low hierarchy. Professional growth through continuous learning, training programs, and exposure to emerging technologies. An inclusive workplace that supports work-life balance. Opportunities for global collaboration, contributing to innovative solutions that shape the future of mobile connectivity. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity fuels innovation. We actively encourage applications from all genders (m/f/d) and candidates from diverse backgrounds. We are committed to fostering an open, inclusive, and inspiring workplace where every individual can thrive. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline

Job Title: Pre-Silicon Validation Engineer SoC/IP Job Description: Join the Devices Development Group (DDG), one of Intel s premier System-on-Chip (SoC) design teams, driving innovation in future Intel SoCs and IPs. As a Pre-Silicon Validation Engineer, you will be part of a dynamic team responsible for ensuring the functionality, performance, and reliability of Intel s cutting-edge designs. Key Responsibilities: Validate IP blocks or features at the SoC level, ensuring compliance with design specifications. Develop validation plans and test strategies based on architectural specifications, RTL code, and existing test methodologies. Analyze microarchitecture and debug failures to identify root causes and improve design quality. Develop and utilize various debugging and validation tools to implement validation plans effectively. Participate in silicon debugging, identifying issues and enhancing testing methodologies for future RTL models. Collaborate with IP providers and internal customers to define, develop, and deliver essential infrastructure while addressing issues identified during execution. Qualifications & Requirements: Educational Qualifications: Bachelor s (B.Tech/BS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 5+ years of experience, OR Master s (M.Tech/MS) degree in Computer Science, Computer Engineering, or Electrical Engineering with 3+ years of experience. Technical Skills & Experience: Minimum 2 years of experience in IP or SoC development, verification, or integration using SystemVerilog and UVM (Universal Verification Methodology). Minimum 2 years of experience in writing validation plans and developing software to execute those plans. Minimum 2 years of experience with object-oriented programming languages. Minimum 2 years of experience working with SystemVerilog and UVM. Minimum 1 year of experience with UNIX/Linux environments. Exposure to Graphics Verification and/or Security Verification is a plus. Preferred Qualifications: Minimum 1 year of experience with computer architecture. Minimum 2 years of experience in validation or testing, particularly in silicon design teams. About the Client Computing Group (CCG): The Client Computing Group (CCG) is at the forefront of Intel s PC product and platform development, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. Through strategic partnerships across the industry, CCG delivers innovative computing experiences that empower users to create, connect, and collaborate. As Intel s largest business unit, CCG drives innovation, scalability, and IP development, helping the company fulfill its mission of enriching lives through technology. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, which includes: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development opportunities to support career growth.

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Description: We are seeking a highly skilled and experienced CPU Verification Engineer with a focus on ARM and NCC-based ARM architecture. This role requires a deep understanding of CPU microarchitecture, SOC integration, and verification methodologies. The ideal candidate will lead verification efforts, collaborate with cross-functional teams, and mentor junior engineers to ensure high-quality CPU design verification. Key Responsibilities: Lead and execute verification plans for CPU designs based on ARM and NCC-based ARM architecture. Develop and enhance testbenches and verification environments using advanced automation techniques. Collaborate with design and architecture teams to identify and resolve specification gaps, ensuring comprehensive verification coverage. Perform SOC-level verification, including integration and validation of CPU subsystems. Utilize industry-standard verification tools and methodologies such as UVM, SystemVerilog, and simulation/emulation platforms. Mentor and guide junior verification engineers, providing technical leadership and support. Continuously improve verification processes and methodologies to enhance efficiency and effectiveness. Qualifications: Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 8 14 years of experience in CPU verification, with a focus on ARM and NCC-based ARM architecture. Proficiency in verification languages and methodologies, including SystemVerilog, UVM, and scripting languages (Python, Perl, etc.). Strong understanding of CPU microarchitecture, memory hierarchy, and SOC integration. Experience with simulation, emulation, and formal verification tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills, with the ability to work in a collaborative environment. Preferred Qualifications: Experience with low-power design verification and performance verification. Knowledge of hardware security verification techniques. Familiarity with machine learning and AI-based verification approaches. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of hardware engineering or related work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or related field and 1+ year of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Key Responsibilities: QMS Documentation & Activities: Expertise in preparing and managing QMS (Quality Management System) documentation related to facility and engineering activities, including writing SOPs for lab instruments, equipment, and utilities, as well as preparing qualification documents (DQ, IQ, OQ, PQ), deviation handling, change control, risk assessment, CAPA, and commissioning documents. Cross-functional Collaboration: Work closely with both internal teams and external stakeholders to ensure the smooth implementation and execution of engineering maintenance activities. This includes document preparation, process review, implementation, and follow-ups with various functional teams and vendors. Facility Modification & Commissioning: Manage facility modification projects, including overseeing commissioning and qualifications documentation to ensure that changes are aligned with regulatory and operational standards. Lab Equipment Operations & Maintenance: Oversee the operation and maintenance of lab equipment, including CO2 incubators, deep freezers, autoclaves, biosafety cabinets, LAF, stability chambers, cooling incubators, lab centrifuges, water baths, hot air ovens, incubator shakers, water purification systems, bioreactors, cold rooms, and liquid nitrogen systems. Analytical Instrument Operations & Maintenance: Manage the operation and maintenance of analytical instruments such as flow cytometers, spectrophotometers, multimode microplate readers, chemical image systems, gel image systems, osmometers, pH & conductivity meters, weighing balances, and western blot instruments. Utility Equipment Maintenance: Manage the operation and maintenance of HVAC systems (including air handling units, chillers, cooling towers, and BMS monitoring systems), utility equipment such as transformers, DG sets, air compressors, nitrogen generators, and LT panels. Preventive Maintenance Planning: Prepare and review schedules for periodic maintenance of lab instruments, utility equipment, and facility infrastructure. Ensure that all maintenance activities are conducted timely and in accordance with operational needs. Corrective and Preventive Actions: Coordinate and oversee corrective and preventive actions related to observations during internal and external audits, ensuring continuous compliance with quality standards. Vendor and OEM Coordination: Serve as the primary point of contact for external vendors and OEM service providers for periodic preventive maintenance (PM), calibration activities, and addressing breakdown issues. Project & Facility Modification Support: Coordinate and support the execution, verification, and successful completion of new projects or facility modification activities. Safety and Sustainability: Ensure compliance with safety practices and procedures, sustainability programs, and hygiene maintenance standards across the facility. Key Skills: QMS Documentation: In-depth experience in writing and managing SOPs and qualification documents (DQ, IQ, OQ, PQ) for lab instruments and utility systems. Proficient in handling deviations, change controls, risk assessments, CAPA, and commissioning documentation. Lab Equipment Expertise: Strong knowledge in the operation and maintenance of various lab equipment, including incubators, freezers, autoclaves, biosafety cabinets, stability chambers, centrifuges, and water purification systems. Analytical Instruments Management: Expertise in handling and maintaining analytical instruments like flow cytometers, spectrophotometers, microplate readers, and various other lab-based instruments used for experiments and analysis. Utility Systems & HVAC Management: Strong knowledge of utility equipment management, including HVAC systems, transformers, DG sets, air compressors, and nitrogen generators. Preventive & Corrective Maintenance: Ability to plan, schedule, and execute preventive and corrective maintenance tasks for lab instruments and utility systems, ensuring minimal downtime. Vendor Management: Expertise in coordinating with external vendors and OEMs for service contracts, maintenance, calibration, and addressing equipment failures or breakdowns. Project Coordination: Ability to manage and execute facility modification projects, ensuring timely delivery and alignment with operational needs. Safety & Compliance: Sound knowledge of safety practices, hygiene, sustainability programs, and regulatory compliance within facility and equipment operations. Competencies: Attention to Detail: High level of attention to detail in handling documentation, operational processes, and safety practices. Problem Solving: Strong analytical skills to troubleshoot and resolve issues in equipment, systems, and processes. Interpersonal & Communication Skills: Excellent communication and interpersonal skills to effectively collaborate with internal teams, external vendors, and service providers. Project Management: Ability to manage projects efficiently, ensuring all modifications, installations, and maintenance activities are completed on time and within scope. Team Collaboration: Team-oriented mindset with a collaborative approach to work alongside internal departments and external contractors/service providers. Adaptability: Ability to adapt to changing priorities, work in dynamic environments, and manage multiple tasks simultaneously. Qualification : Diploma/BE in electrical and electronics, with QMS related certifications with 10+Years of experience.

Job Overview As a Tools Support & Infrastructure Engineer at Qualcomm, you'll play a vital role in supporting and enhancing the design flows and infrastructure for Qualcomm's Digital Signal Processing (DSP) team. The DSP design team delivers high-performance DSP cores that are integral to Qualcomm's multi-tier SoC roadmap, particularly for mobile applications. This position involves managing DSP design databases, developing automation tools to streamline the verification process, and collaborating with global teams to optimize design efficiency and quality. Key Responsibilities Manage DSP Design Database: Oversee the DSP design database, supporting design and verification teams with infrastructure needs. Build Automation: Create new automation tools to enhance the productivity of design verification teams, making it easier to debug simulation failures. Collaborate with Global Teams: Work with Qualcomm s global DSP design teams (architecture, implementation, post-silicon, and back-end teams) to enhance DSP IP infrastructure. Improve Tool Methodologies: Design and deploy new tool methodologies to continuously improve the quality, efficiency, and effectiveness of design and verification processes. Support Design Flows: Contribute to and improve design flows, ensuring the seamless integration of tools and resources used by design teams. Minimum Qualifications Educational Requirements: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of relevant work experience, or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 5+ years of relevant work experience, or PhD in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant work experience. Skills & Experience Programming & Tools Support: 3-10 years of experience in programming, database management, and providing tools support for complex DSP IP designs. Automation Expertise: Extensive experience in building automation tools that improve design and verification processes. Programming Languages: Expertise in C++ and Java. Scripting & Automation: Proficiency with scripting languages and tools such as Perl, Python, Shell, Makefiles, and TCI. Analytical Skills: Strong analytic, programming, and debugging abilities. Object-Oriented Programming (OOP): Deep understanding of OOP concepts. Web Programming: Familiarity with Java for web programming is a plus. Unix Environment: Solid understanding of the Unix environment. Digital Design Flows: Knowledge of digital design flows is a plus. Communication: Excellent interpersonal and communication skills, with the ability to work collaboratively with global teams.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Job Description Additional Job Description Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm. Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities Design, develop, and maintain CAD infrastructure for silicon design teams enabling bringup, test and debug automations. Collaborate with silicon designers, architects, silicon validation engineer, and other stakeholders to to improve future CPU bringups Define and implement new infrastructure capabilities that can be used to accelerate design utilizing multi-site datacenters. Prepare for CPU bring up through pre-work on emulation and FPGA platforms Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs Troubleshoot and resolve issues related to CAD infrastructure, including hardware and software problems Support design engineers on the flow setup and resolve their queries Develop test contents and testing strategies to assist validation of CPU on silicon Qualifications Must have strong object-oriented programming abilities in Python. Must have knowledge and experience with silicon bringup and debugging Must have worked on Digital flows/methodologies development in the Emulation, pre-silicon and/or post-silicon. Familiarity with firmware and software debug, Silicon bring up and validation of CPU features. MS/BS in Electrical/Computer Engineering with 10+ years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...