Verification Leadership Jobs in Bengaluru

Position: Technical Lead / Project Lead Hardware Design Location: Bangalore Education: B.E./B.Tech. in Electronics & Communication or Electronics & Telecommunication M.E./M.Tech. in Electronics & Communication Experience: 5 to 8 years Job Overview We are seeking a dynamic and experienced Technical Lead / Project Lead Hardware Design to join our engineering team in Bangalore. In this leadership role, you will guide a team of hardware engineers through the end-to-end design and development of advanced embedded and FPGA-based systems primarily for defense and industrial applications. You'll be responsible for ensuring high-quality, defect-free, and timely project deliveries while driving technical excellence and process adherence. Key Responsibilities Technical Leadership Lead hardware design projects from specification to delivery, ensuring robust and scalable solutions. Provide technical guidance to team members in circuit design, schematic development, and board-level design. Finalize board specifications based on customer requirements and prepare detailed technical documentation. Review hardware modules and ensure compliance with design best practices and industry standards. Lead Signal Integrity (SI), Power Integrity (PI), and thermal analysis during design and validation phases. Project Management Plan, monitor, and track project schedules, resource allocation, and delivery milestones. Coordinate with the Project Manager and cross-functional teams to ensure alignment and timely progress. Conduct internal project meetings, present status updates, and recommend process or technical improvements. Ensure adherence to QMS guidelines, project processes, and quality goals. Team Development & Support Mentor junior engineers and support individual learning and development plans. Manage a small team, resolve technical and interpersonal challenges, and promote a collaborative work environment. Assist in performance reviews and team development initiatives. Quality & Process Improvement Drive defect prevention initiatives and participate in continuous improvement of design processes. Coordinate configuration management and quality control activities throughout the project lifecycle. Technical Skill Set Strong hands-on experience in FPGA-based board design and embedded hardware development. Expertise in system-level architecture, processor interfaces, DDR memory design, serial bus protocols, and networking. Proficient in board bring-up and debugging at system level. Experience with embedded hardware design for defense applications and understanding of qualification processes. Tools: Schematic capture/layout: OrCAD, Allegro Signal integrity tools for SI/PI analysis Soft Skills Excellent verbal and written communication skills Strong people management and leadership capabilities Effective time management, organization, and planning Proven ability to manage small teams and drive project success Familiarity with quality systems and engineering best practices Opportunity to work on cutting-edge, high-impact hardware projects Collaborative and technically strong work environment Competitive compensation and benefits package Focus on leadership development and continuous learning Dynamic and inclusive workplace culture Qualification : M.E./M.Tech. in Electronics & Communication

Job Title: Lead Satellite Design & Development Location: Bengaluru Experience Required: 10 to 15 years Minimum Qualification: Bachelor s or Master s degree in Engineering (BE/BTech/ME/MTech) or Science (MSc) Specialization in Aerospace, Mechanical, Electronics, or Systems Engineering preferred Key Skills Satellite Systems Engineering System Architecture & Integration Flight Mechanics & Control Systems NX and Concept Design Tools Project & Resource Management Systems Engineering Lifecycle (V&V, Risk, Interfaces) Strategic & Technical Leadership Stakeholder Management Job Summary We are seeking a seasoned and visionary Lead Satellite Design & Development to lead end-to-end execution of satellite programs. The role requires deep technical expertise, hands-on project management skills, and a proven ability to lead multidisciplinary engineering teams. The ideal candidate will be instrumental in shaping system architecture, ensuring technical excellence, and aligning with organizational goals in the dynamic field of space systems. Key Responsibilities Team Leadership Lead and mentor a multi-functional engineering team across systems, mechanical, electronics, aerospace, software, and reliability disciplines. Foster a collaborative, innovation-driven work culture aligned with project objectives and company strategy. Project Management Manage full project lifecycle: from concept development through design, integration, testing, and deployment. Define project plans, budgets, schedules, and resource allocations using Agile, Waterfall, or hybrid methodologies. Conduct regular project reviews to monitor performance, identify risks, and implement mitigation strategies. Systems Engineering & Integration Drive system architecture and engineering processes: requirements definition, interface control, verification & validation, and risk management. Balance trade-offs between performance, cost, risk, and reliability throughout the development lifecycle. Ensure all engineering documentation is maintained in line with industry standards and internal processes. Quality Assurance & Risk Management Champion adherence to quality benchmarks and reliability targets. Develop and enforce comprehensive risk mitigation plans across design, development, and integration phases. Stakeholder Engagement Interface with internal teams (R&D, QA, Production, Finance, Executive Leadership) for cross-functional alignment. Engage external partners clients, suppliers, regulators to ensure compliance, clarity, and project alignment. Represent the organization in technical forums, industry panels, and client briefings. Innovation & Continuous Improvement Drive adoption of emerging technologies and design innovations to strengthen competitive edge. Lead process optimization initiatives to improve development efficiency, product quality, and team performance. Preferred Qualifications & Experience Proven leadership in full-cycle satellite or satellite bus development from mission planning and architecture to launch and mission control. In-depth knowledge of satellite sub-systems and technology providers. Familiarity with international standards and best practices in satellite design and development. Strong strategic acumen in planning, budgeting, and resource management for complex aerospace projects. Qualification : Bachelors or Masters degree in Engineering (BE/BTech/ME/MTech) or Science (MSc)

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Requirements: BE/BTech degree in CS/EE with 8+ years experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus. Qualification : BE/BTech degree in CS/EE

Job Title: Associate Architect Group: ADAS/AD Business Unit: CARIAD Business Unit India Location: Whitefield, Bangalore Experience: 7 to 12 years About CARIAD (Car, I Am Digital) CARIAD is a forward-thinking automotive software company within the Volkswagen Group, focused on expanding software competencies and innovating within the automotive industry. We are developing a unified technology platform, including a vehicle operating system, cloud platform, and new architecture across all Volkswagen Group brands. CARIAD s goal is to drive the digital transformation of mobility. CARIAD India operates under a brand licensing agreement with Germany-based CARIAD SE. Join a team of 360 talented engineers and developers at CARIAD India, collaborating with over 6,000 CARIDIANs globally, all passionate about automotive innovation. Job Description We are looking for an Associate Architect to join our team and play a crucial role in expanding our ADAS practice. This role involves designing and leading the development of ADAS software integration, testing, and system architecture. You will also be responsible for guiding the technical aspects of the ADAS software development life cycle, ensuring quality, efficiency, and customer satisfaction. Key Responsibilities: ADAS Software Integration & Testing: Own the ADAS software integration, software testing, system integration testing (SIT), and system testing (ST). System & Software Architecture: Design and manage the system and software architecture for integration and testing, ensuring all technical aspects align with project goals. Technical Reviews: Lead technical reviews of work products during the software testing phase to ensure high-quality deliverables. Project Ownership: Take full responsibility for project deliverables, including test schedules, risk management, quality control, and meeting customer commitments. Leadership: Lead or co-lead the ADAS practice within the Automotive Engineering Services BU. Mentor and guide teams to ensure successful project outcomes. Test Ecosystem Development: Build and enhance the test ecosystem by integrating different platforms for fully automated end-to-end testing. Test & Automation Strategy: Define test strategies, automation approaches, and methodologies to solve complex technical problems in ADAS software development. Best Practices & Process Improvement: Refine and define best practices, processes, and workflows to improve efficiency and quality. Test Solutions: Select hardware, controllers, and methodologies to develop robust test solutions. Technical Consultation: Provide technical consultation to engineering teams on implementation and realization of test solutions. Performance & Optimization: Define performance metrics/KPIs, benchmark systems, and drive performance optimization efforts. Customer Solutions: Understand customer requirements and deliver solutions through process changes, tool upgrades, or architecture design. System Reusability: Study existing systems and infrastructure to enable reusability of components. Team Management & Coaching: Manage and coach teams in developing automation frameworks, tools, plant models, simulations, and automated test equipment (ATE). Oversee setting up test racks and interconnections. Business Development Support: Assist business development teams by delivering technical presentations and contributing to business growth. Required Skills and Experience: Experience: 7 to 12 years in software development, system architecture, and ADAS integration, with strong experience in integration testing and test strategy development. Technical Expertise:Expertise in ADAS software integration and testing methodologies. Experience in system architecture design for integration and testing in automotive applications. In-depth knowledge of software testing tools, automation strategies, and methodologies. Familiarity with automotive testing environments and platforms, including hardware controllers and testing solutions. Leadership Skills: Experience leading or co-leading teams, managing technical deliverables, and mentoring engineers. Process Improvement: Proven experience defining and implementing best practices, processes, and workflows. Customer-Focused: Ability to understand customer needs and translate them into technical solutions. People Management: Ability to coach and guide teams to build automation frameworks, tools, and test solutions. Innovative Environment: Be at the forefront of automotive digital transformation, working on cutting-edge ADAS technologies. Career Growth: Engage with global teams and continuously enhance your skills and career path. Impactful Projects: Lead and contribute to impactful projects that shape the future of automotive mobility. Collaborative Culture: Join a diverse and skilled team of engineers, united by a common goal of transforming mobility through technology. About CARIAD India: At CARIAD India, we foster a collaborative and innovative work environment that offers opportunities to work on some of the most advanced and impactful projects in the automotive industry. As part of a global team, you ll help drive the digitalization of the automotive sector while growing your career in a high-tech environment.

Job Title: Staff Engineer Embedded Software & Methodologies Job Overview: The Architecture and Technology Group (ATG) at Arm plays a critical role in shaping the future of Arm s architecture roadmap. ATG develops industry-leading secure CPU and system architectures, along with technologies that empower our global ecosystem to build innovative products. As part of this, ATG also creates Architecture Compliance Kits (ACK) a crucial product that ensures CPU implementations adhere to Arm architecture standards. These kits are utilized by both internal and external CPU design teams to validate compliance. The ATG team in Bangalore focuses on developing these ACK products. The Methodology Team, specifically, builds embedded software, methodologies, and tools for the latest Arm cores and system IPs. As a Staff Engineer, you will provide technical leadership and guide junior engineers while actively contributing to product development. You will leverage your software engineering expertise to build scalable, high-quality compliance kits used across Arm s internal teams and external partners. Key Responsibilities: Act as a technical expert, driving the design and development of embedded software, boot flows, and methodologies for architectural compliance. Analyze architecture specifications and define software methodologies that meet industry standards. Provide technical direction to the team while mentoring and guiding junior engineers. Collaborate with cross-functional teams to ensure successful and timely delivery of engineering commitments. Continuously enhance development efficiency through improved methodologies, automation, and process enhancements. Communicate delivery status, technical risks, and mitigation plans effectively to stakeholders. Required Skills & Experience: Bachelor s or Master s degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering. 10+ years of experience in embedded software development, boot flows, firmware development, driver development, or low-level operating system driver development for processors. Strong understanding of software engineering principles, along with excellent analytical, problem-solving, and debugging skills. Strong communication skills both verbal and written with the ability to convey technical information effectively across teams. Self-driven, proactive, and able to take ownership of tasks and responsibilities. Preferred Skills: Familiarity with computer architecture fundamentals, especially Arm or x86 architecture. Proficiency in at least one programming language (C or C++) and one scripting language (Perl or Python). Experience with assembly-level programming. Working knowledge of software verification methodologies, embedded software environments, and toolchains (with preference for GNU toolchains). Join a team that thrives on technical excellence and innovation. Whether it s defining cutting-edge architectures, developing advanced cores, or creating custom physical IPs, Arm offers you a platform to push boundaries and make a lasting impact. Qualification : Bachelors or Masters degree (or equivalent) in Computer Engineering, Computer Science, or Electronics Engineering.

Job Overview: The Architecture and Technology Group (ATG) at Arm develops technologies and products for Arm s future architecture roadmap. In ATG, we are developing world-leading Secure CPU and System architectures and associated technologies; enabling our ecosystem to build compelling products. Along with the architecture definition, ATG develops products to confirm compliance to the architecture. The ATG team located in Bangalore develops a product called Architecture Compliance Kits (ACK) that are delivered to multiple internal and external CPU design teams to validate that Arm architecture CPU implementations are compliant with the Arm architecture. You will learn Arm Architecture and apply it along with hardware and software verification skills to develop products for verifying the Architecture. You will develop good engineering and technical skills, and a fair understanding of CPU architecture and microarchitecture. You will connect with a wide range of teams within ATG, architects, and with our external partners. In this role, you will also develop solutions for future Arm architecture developments and influence the product offering. Responsibilities: Technical expertise, understanding architecture definitions, carrying out investigations and feasibility studies, defining and developing verification strategies, and contributing to the development of compliance products. Design verification test plans and test cases in assembly, C, HVL, and higher abstraction languages using automation techniques as needed. Strong and continuous communication on deliveries and risks, ensuring that all engineering commitments are delivered successfully. Drive efficiency improvements through adoption of the right development flows and methodologies. Excellent verbal and written communication skills. Required Skills and Experience: B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering. 8+ years of verification experience (CPU/complex IP verification is a plus). Strong understanding of computer architecture. Proficiency in logical programming using C/C++/Assembly with experience in adopting software engineering best practices. Nice To Have Skills and Experience: Experience in CPU verification would be a plus. Knowledge of x86 or Arm processor architecture. We are guided by our core beliefs that reflect our culture and guide our decisions, defining how we work together to surpass ordinary and craft outstanding products and careers. In Return: We promise you endless opportunities to experiment and go even further in hardware! From architecture definition to complex core implementation to full custom physical IPs, here you'll have our backing to push limits in vital areas. #LI-KR2 Qualification : B.Tech/B.S. or M.Tech/M.S./PhD in Computer Engineering, Computer Science, or Electronics Engineering.

Job Title: Lead Engineer Software Test & Release Location: Bangalore Job Summary We are looking for a skilled Security Test and Automation Engineer with 7-9 years of experience in Security Verification and Validation, particularly on Embedded Systems. The ideal candidate will have 3-4 years of leadership experience in managing a team of security test engineers and hands-on expertise in scripting languages like Python, Java, and AI/ML-based tools. The primary responsibility will be to develop and execute security testing strategies across various domains including Devices, Automotive, Medical Devices, and Telecom Infrastructure (Wireless and Wired). Key Responsibilities Security Test Strategy: Develop and execute a comprehensive security test and automation strategy across multiple domains like Devices, Automotive, Medical Devices, and Telecom Infrastructure. Collaborate with project teams to capture best practices, share knowledge about the latest tools and technologies, and identify opportunities for new solution development. Understand client requirements for security testing and prepare proposals related to Security and Penetration Testing. Penetration Testing: Work with clients to understand their testing needs (e.g., number and types of systems for testing). Plan, create, and execute penetration methods, scripts, and tests to assess the security of systems. Perform remote or on-site security testing of a client s network or infrastructure to uncover vulnerabilities. Simulate security breaches to test system vulnerabilities and identify potential threats. Generate detailed reports outlining security issues, the level of risk, and recommendations for remediation. Team Leadership and Development: Lead and mentor a team of security test engineers, providing guidance on technical challenges and professional growth. Conduct reviews of designs, code, and test plans to identify risks and ensure quality deliverables. Identify training needs for the team and provide support for their technical development. Risk Analysis and Requirement Management: Conduct requirement analysis and feasibility studies, considering risk identification and mitigation. Perform system-level work estimation and ensure timely delivery of high-quality work. Ensure traceability of requirements from design to delivery, while optimizing code and ensuring test coverage. Continuous Improvement: Participate in technical initiatives within the project and organization, delivering training and maintaining a high level of technical competence through ongoing self-study and technical assessments. Identify and implement improvements in security testing practices and tools. Required Skills and Experience 7-9 years in Security Verification and Validation on Embedded Systems. 3-4 years of experience leading a team of security test engineers. Hands-on experience with scripting languages like Python, Java, and AI/ML-based tools. Experience in penetration testing and security assessments for embedded systems and network infrastructures. Technical Expertise: Strong knowledge of security testing methodologies, vulnerability assessments, and penetration testing. Proficiency in scripting languages (Python, Java, Perl, Shell scripts, TCL). Experience in Automation Frameworks for security testing. Understanding of network protocols (2G, 3G, LTE, 5G) and security concerns within telecommunications and embedded systems. Certifications: Bachelor s degree in Engineering or equivalent. Certifications in Security Testing (e.g., Certified Ethical Hacker - CEH) are highly desirable. Tools and Technologies: Experience with test and trace/log collection tools such as QXDM, QCAT, QPST, Prism, and other telecom instruments (e.g., Anritsu, Keysight). Familiarity with automation scripting tools like RTD (for Anritsu) or equivalent. Knowledge of Linux host platforms and network simulation tools. Specialization: Expertise in 2G, 3G, 4G, 5G, Interop Testing, and VSAT-SATCOM technologies. Understanding of 3GPP specifications and network vendor tests. Desirable Skills Strong problem-solving and analytical skills to identify vulnerabilities and assess risks in systems. Ability to provide strategic and actionable insights based on security findings. Ability to communicate complex security issues to non-technical stakeholders. Leadership and mentoring capabilities to guide junior engineers and promote team development. Work Environment Location: Bangalore Opportunity to work in a dynamic environment with the latest tools and technologies in the security testing domain. If you have a passion for security testing and automation, along with a desire to lead and contribute to impactful projects, this is the perfect opportunity for you! Apply now to join our team and make a significant impact in the field of security testing.

Job Title: Senior 5G RAN Developer Location: Bengaluru, India Experience: 4 to 8 years Education: B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline About Tietoevry At Tietoevry, we are at the forefront of 5G innovation, collaborating with global telecom leaders to design and deliver next-generation wireless solutions. Our inclusive, innovation-driven culture offers the perfect platform to work on cutting-edge technologies and contribute to shaping the future of connectivity. Role Overview As a Senior 5G RAN Developer, you will play a critical role in designing, developing, and maintaining 5G NR protocol software components. You will lead the systemization, development, and verification processes for various RAN subsystems, contributing to the development and optimization of gNodeB solutions. This role requires deep technical expertise in 5G RAN Layer 1, 2, and 3, combined with strong architectural insight and a proactive, problem-solving mindset. You will collaborate closely with clients and global teams, provide technical guidance to peers, and help drive innovation in our 5G product portfolio. Key Responsibilities Contribute to product development, maintenance, and delivery, including requirement analysis, high-level design (HLD), low-level design (LLD), coding, and verification of gNodeB. Analyze and prioritize 3GPP features for development across different subsystems. Lead system integration and testing activities in collaboration with client and internal teams. Provide technical leadership by guiding teams on complex design and architectural decisions. Drive continuous performance improvement and ensure quality deliverables. Identify and implement architectural enhancements to optimize product performance and scalability. Document development processes, system designs, and testing outcomes thoroughly. Mandatory Skills & Experience Proven hands-on experience in developing LTE/5G NR MAC Scheduler and Layer-2 protocols. Deep knowledge of 3GPP specifications, particularly across Layer 1, Layer 2, and Layer 3. Strong understanding of Layer1-Layer2 and Layer2-Layer3 interfaces. Solid understanding of networking protocols such as TCP/IP, UDP, SCTP, etc. Experience debugging complex gNodeB issues, including log file analysis and troubleshooting in live environments. Proficiency in C/C++ programming, with experience implementing complex algorithms. Hands-on experience with any of the following features: MAC, RLC, PDCP, Scheduler, Power Control, SPS, TTI Bundling, Link Adaptation, GTP-C, GTP-U In-depth understanding of 3GPP Radio Access Standards, ORAN split architecture, and radio protocol algorithms. Experience in feasibility studies and simulations related to Layer 1/PHY features and packet scheduler algorithms. Experience in software development and systemization for 5G Layer 1/Layer 2/Layer 3 protocols. Strong grasp of Linux OS and optimization techniques using DPDK. Hands-on expertise with version control tools like Git and Gerrit, and project management tools like Jira. Experience working in Agile environments. Preferred Skills Experience with cloud technologies, such as microservices and containers. Exposure to ORAN/Open RAN ecosystems is a plus. Strong analytical mindset with a self-driven and proactive approach. Soft Skills Excellent communication skills, with the ability to work in a dynamic, multicultural environment. Strong collaboration skills to work closely with cross-functional teams across geographies. Ability to mentor and guide junior developers, fostering knowledge sharing within the team. Opportunity to work on cutting-edge 5G technology projects in collaboration with global telecom leaders. A Nordic-inspired culture based on trust, transparency, respect, and low hierarchy. Professional growth through continuous learning, training programs, and exposure to emerging technologies. An inclusive workplace that supports work-life balance. Opportunities for global collaboration, contributing to innovative solutions that shape the future of mobile connectivity. Diversity & Inclusion Commitment At Tietoevry, we believe that diversity fuels innovation. We actively encourage applications from all genders (m/f/d) and candidates from diverse backgrounds. We are committed to fostering an open, inclusive, and inspiring workplace where every individual can thrive. Qualification : B.E./B.Tech./M.E./M.Tech. in Electronics & Communication (EC), Electrical Engineering (EE), Computer Science (CS), or an equivalent discipline

Senior Payroll & HR Generalist About Saviynt Saviynt is an identity authority platform designed to power and protect organizations in an era of digital transformation. As businesses navigate growing cybersecurity risks, our Enterprise Identity Cloud provides unparalleled visibility, control, and intelligence, ensuring secure, right-time access to critical digital resources. To support our rapid growth, we are seeking a Senior Payroll & HR Generalist who will play a crucial role in managing payroll processes and leading key HR functions across India and the APAC region. This role will report to the Manager of Payroll & Benefits in El Segundo, CA, for functional leadership, while working locally under the Director of Human Resources in Bengaluru. Key Responsibilities Payroll Processing & Compliance Lead and oversee end-to-end payroll processing for India & APAC, ensuring accuracy, compliance, and timeliness. Partner with global payroll and accounting firms to maintain adherence to international payroll regulations and best practices. Review, analyze, and verify payroll reports to identify discrepancies, processing necessary adjustments before final payroll completion. Maintain and update payroll data in Namely, ensuring accurate records of compensation, tax deductions, bonuses, and statutory contributions. Manage payroll-related benefits administration, including incentives, tax deductions, and retirement contributions. Ensure compliance with local labor laws, taxation policies, and company policies related to payroll and employee benefits. HR Generalist & Employee Lifecycle Management Oversee employee leave management, ensuring accurate payroll integration and compliance with company policies. Support onboarding & offboarding processes, ensuring payroll setup for new hires and accurate termination payouts. Assist with performance evaluation processes, ensuring payroll-related adjustments align with compensation changes. Serve as an HR compliance expert, advising on payroll-related labor laws, employment verification, and unemployment claims. Audit, Reporting & Strategic HR Support Prepare payroll-related reports for internal and external stakeholders. Facilitate payroll audits, pension filings, and employment verifications. Work closely with HR leadership to align payroll strategies with business objectives and drive process improvements. Provide administrative, operational, and strategic HR support to the Director of Human Resources as needed. What You Bring Extensive experience in payroll processing & HR functions for India & APAC. Strong knowledge of Indian labor laws, payroll compliance, taxation, and employee benefits. Experience in full-cycle payroll management, including incentives, tax deductions, and statutory contributions. Proficiency in HR systems (Namely or similar HRIS platforms). Ability to manage audits, reports, and compliance documentation. Excellent attention to detail, problem-solving, and analytical skills. Strong collaboration skills with global teams across multiple time zones. Preferred (Good to Have): Experience working in a fast-paced SaaS or tech-driven organization. Knowledge of global payroll practices (US, Europe, APAC, etc.). Work in a high-growth, technology-driven environment that values innovation and excellence. Gain exposure to global payroll processes & HR strategies in a dynamic, fast-paced setting. Collaborate with industry-leading professionals and contribute to scaling a global workforce. Competitive compensation, benefits, and professional growth opportunities. Saviynt is an equal opportunity employer. We welcome applicants from diverse backgrounds and do not discriminate based on race, gender, age, disability, or veteran status. If you re a detail-oriented payroll and HR expert passionate about process efficiency and compliance, we d love to hear from you!

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Description Intel is seeking an experienced Systems Engineer to drive the design, development, and integration of hardware, firmware, and software solutions for Xeon-based platforms. The role focuses on system architecture, performance optimization, and technical risk assessment while ensuring scalability, reliability, and security in system implementations. The ideal candidate will work on customer-centric solutions, influencing next-generation system design and conducting proof-of-concept experiments to validate new features and technologies. Key Responsibilities: System Architecture & Design: Define, develop, and optimize end-to-end solutions integrating software, firmware, board, and silicon/SoC components. Customer-Centric Solutions: Translate business opportunities into use cases, develop product specifications, and implement solutions based on customer needs and system limitations. Performance & Reliability Optimization: Conduct design analysis, assess technical risks, and optimize for security, scalability, and maintainability. Hardware Validation & Debug: Perform schematic reviews, layout verification, mechanical/thermal analysis, and electrical validation (including Signal Integrity (SI) analysis). System Integration: Ensure smooth hardware-software integration, identifying and resolving hardware issues at the component and system levels. Lab-Based Proof-of-Concept Testing: Conduct real-life environment simulations, prototype testing, and performance benchmarking. Documentation & Knowledge Sharing: Develop technical documents, customer presentations, and training materials to enhance internal and external knowledge sharing. Industry Research & Collaboration: Engage in academic and industry research, driving innovation beyond existing solutions. Qualifications & Experience: Educational Requirements: B.E/B.Tech in Electronics & Communication, Computer Science, or a related field. Minimum of 10 years of relevant industry experience. Technical Expertise: Experience in Xeon platform hardware design and validation. Strong knowledge of schematics, PCB layout, mechanical, and thermal analysis. Experience with electrical validation, signal integrity (SI), and power integrity (PI) analysis (desirable). Expertise in hardware issue validation, debugging, and system integration. Strong problem-solving and analytical skills for complex, multi-layered system architectures. Excellent technical documentation and presentation skills. About Intel Validation Engineering (iVE) Group: The Intel Validation Engineering (iVE) Group plays a pivotal role in Intel s technology leadership, validating, debugging, and optimizing Intel s cutting-edge designs. iVE ensures that Intel's next-generation products meet the highest quality standards, enabling Intel to deliver world-class technology platforms. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer that values diversity and welcomes applications from all qualified candidates, regardless of gender, nationality, disability, or other protected status. Intel offers a top-tier compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Health, retirement, and vacation benefits. Access to cutting-edge technology and career growth opportunities. Qualification : B.E/B.Tech in Electronics & Communication, Computer Science, or a related field.

Job Description: We are seeking a highly skilled and experienced CPU Verification Engineer with a focus on ARM and NCC-based ARM architecture. This role requires a deep understanding of CPU microarchitecture, SOC integration, and verification methodologies. The ideal candidate will lead verification efforts, collaborate with cross-functional teams, and mentor junior engineers to ensure high-quality CPU design verification. Key Responsibilities: Lead and execute verification plans for CPU designs based on ARM and NCC-based ARM architecture. Develop and enhance testbenches and verification environments using advanced automation techniques. Collaborate with design and architecture teams to identify and resolve specification gaps, ensuring comprehensive verification coverage. Perform SOC-level verification, including integration and validation of CPU subsystems. Utilize industry-standard verification tools and methodologies such as UVM, SystemVerilog, and simulation/emulation platforms. Mentor and guide junior verification engineers, providing technical leadership and support. Continuously improve verification processes and methodologies to enhance efficiency and effectiveness. Qualifications: Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 8 14 years of experience in CPU verification, with a focus on ARM and NCC-based ARM architecture. Proficiency in verification languages and methodologies, including SystemVerilog, UVM, and scripting languages (Python, Perl, etc.). Strong understanding of CPU microarchitecture, memory hierarchy, and SOC integration. Experience with simulation, emulation, and formal verification tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills, with the ability to work in a collaborative environment. Preferred Qualifications: Experience with low-power design verification and performance verification. Knowledge of hardware security verification techniques. Familiarity with machine learning and AI-based verification approaches. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of hardware engineering or related work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or related field and 1+ year of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

Description Role Description The Engineering Manager demonstrates deep business, industry, and product knowledge to ensure the success of our customers by effectively managing a team of Engineers and Architects. In this role, the Engineering Manager will specialize in one or more lines of business, a specific cloud or industry to speak the customer language and ensure customer value realization. They are aligned by cloud strategy, building and encouraging positive relationships to help customers progress on their digital journey. Salesforce is looking for technically strong, energetic, highly collaborative, and passionate leaders to lead our software engineering teams! You will run and lead a team/teams of outstanding developers and keep quality in mind. We work in a collaborative environment, and we value open communication and feedback, code reviews, and making learning fun! Your Impact Drive the execution and delivery of features by collaborating with many multi-functional teams, architects, product owners and engineer Make critical decisions that attribute to the success of the product Proactive in foreseeing issues and resolving it before it happens Daily management of stand-ups as the Scrum Master for engineering teams Partner with PO to align with objectives, priorities, tradeoffs, and risk Ensuring teams have clear priorities and adequate resources Empowering the delivery team to self coordinate Be a multiplier and have a passion for team and team members success Providing technical guidance, career development, and mentoring to team members Maintaining high morale and motivating the delivery team to go above and beyond Vocally advocating for technical excellence and helping the teams make good decisions Participating in architecture discussions and planning Participating in multi-functional coordination, planning, and reviews with leads from other engineering teams Maintaining and encouraging our culture by interviewing and hiring only the most qualified individuals Occasionally chipping in to development tasks such as coding and feature verifications to assist teams with release commitments, to gain an understanding of the deeply technical product as well as to keep your technical skill sharp Minimum Requirements A related technical degree required Min 15 years of Software Engineering experience with 3-5 years of proven track record leading sizeable teams with a distinguished track record on technically fast paced projects Experience leading large scale distributed systems, working with microservices and/or distributed architecture Strong verbal and written communication skills, organizational and time management skills Ability to be flexible, proactive, comfortable working with minimal specifications Experience with short release cycles, the full software lifecycle, and experience working on a product that s been released for public consumption Experience in hiring, mentoring and leading engineers Working experience of software engineering best practices including coding standards, code reviews, SCM, CI, build processes, testing, and operations Experience with Agile development methodologies. Scrum Master experience required Experience in communicating with users, other technical teams, and product management to understand requirements, describe software product features, and technical designs Preferred Requirements Strong knowledge of Salesforce product and platform features, capabilities, and best use of it Able to articulate the importance and value of Governance to Business and IT executives A good understanding of enterprise architecture principles is strongly preferred Ability to quickly grasp and distinctly explain technological and business concepts Serve as a trusted advisor, with a deep curiosity to understand your customers, their motivations and needs, and how to approach ensuring their success Degree or equivalent relevant experience required. Experience will be evaluated based on the core competencies for the role (e.g. extracurricular leadership roles, military experience, volunteer roles, work experience, etc.)

Minimum qualifications: Bachelor s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 20 years of experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes. Experience in leading chip development projects. Experience in working with external ASIC vendors. Preferred qualifications: Master's degree or PhD in Engineering, or a related field. Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation). Knowledge of data centers and cloud markets, technological and business trends, requirements, and ecosystem partners. Ability to motivate and focus a large collaboration to reach challenging goals. Excellent communication and facilitation skills. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Chip Leader, you will be responsible for overseeing the design and development of AI accelerators for our data center. You will be responsible for leading the chip design, from architecture requirements up to tape-out. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Own the chip development and execution. Accountable for Quality, Schedule and Performance, Power, Area (PPA), being the primary point of contact for day-to-day execution of chip development, planning and tracking. Coordinate the work of different disciplines, such as design, verification, and test, to ensure the chip meets all specifications and requirements. Collaborate with the leadership team of each chip project: Technical Program Manager, Design Verification lead, Physical Design lead, DFT lead, and architecture team, to make execution decisions and drive the development process. Resolve technical issues that arise during the chip development process. Ensure chip quality by implementing best practices and implementing quality control measures. Be responsible for project development with the highest quality, manage issues as they arise through design and implementation. Work with Software and Platform teams for hardware-software co-development. Qualification : Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.

Minimum qualifications: Bachelor s degree or equivalent practical experience. 12 years of experience in IT Industry with building and developing infrastructure or distributed systems. Experience in consulting, IT services and Security Check (SC), security clearance. Preferred qualifications: Experience helping customers decide to make investments in new technologies and projects based on expected value and Return on Investment (ROI). Experience with data center migration strategies and collaborating with channel partners and systems integrators. Experience designing, building, and deploying scalable cloud-based solution architectures. Experience engaging product organization and influencing them to work on product features to drive the overall product strategy and roadmap. Ability to work on a team to design processes, implement strategic projects that solve business problems, and lead or work effectively with cross-functional groups. About the job Google's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers. Using your extensive technical and leadership expertise, you manage projects of various size and scope, identifying future opportunities, improving processes and driving the technical directions of your programs. As a Google Distributed Cloud (GDC) Cluster Lead, you will drive the adoption of Air Gapped and Connected Cloud as a result-driven Trusted Advisor to the largest customers, ultimately responsible for ensuring their overall success and transformation with Google Cloud. You will align at the executive level, building and maintaining strong relationships with business executives and IT stakeholders, both internal and external, and understand their business requirements and goals. Building on this knowledge, you will lead the shared strategic roadmaps to drive customer partnerships through pre-sales and delivery, provide technical guidance and programme leadership, and facilitate customers digital transformation to maximize their value on Google Cloud. Google Cloud accelerates every organization s ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google s cutting-edge technology, and tools that help developers build more sustainably. Customers in more than 200 countries and territories turn to Google Cloud as their trusted partner to enable growth and solve their most critical business problems. Responsibilities Manage programs covering customer s GDC program planning, delivery assurance and verification, tracking, reporting, and risk and mitigation planning. Drive the customer partnership for key strategic customers, from a delivery standpoint. Establish executive relationships with business and IT stakeholders to understand their objectives. Accelerate customer s migration to GDC Air-Gapped by influencing all relevant stakeholders and removing roadblocks. Ensure that customers derive maximum value from their investment in Google Cloud. Assess their capabilities, collaborate with other Google stakeholders and prescribe recommendations to help them accelerate GDC deployments and achievement of their business targets. Leverage adoption methodology and transformation framework, conduct customer Quarterly Business Reviews (QBRs), advocate for customers to rapidly knock down adoption blockers, and coordinate across multiple work streams and teams to maintain customer momentum. Qualification : Bachelors degree or equivalent practical experience.

We are seeking an experienced and highly motivated IO DFx Architect/Lead to join our team and lead the Design for Excellence (DFx) efforts for Physical Layer (PHY) interfaces in next-generation PHY. As a PHY DFx Architect/Lead, you will be responsible for driving DFx principles, including Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD), into the development of complex PHY designs. You will collaborate with cross-functional teams to ensure that PHY designs are optimized for quality, performance, reliability, and ease of integration into systems, while reducing time to market and ensuring manufacturability.In this leadership role, you will guide the team in the application of best practices in DFx and contribute to the continuous improvement of processes and methodologies, helping to deliver world-class PHY products.Lead the DFx (Design for Excellence) activities for Physical Layer (PHY) interfaces, ensuring designs are optimized for testability, manufacturability, debugging, and reliability. Understand IP and SOC architecture spec and define DFx requirements. Work with SOC and adjacent IP architects in ensuring DFX compliance across IP boundaries and SOC level DPM/coverage targets.Hands on coding of DFx features and flow clean upCollaborate with hardware design, verification, and manufacturing teams to define and implement DFx methodologies that improve design quality, reduce cost, and accelerate time to market.Oversee the integration of Design for Test (DFT), Design for Manufacturability (DFM), and Design for Debug (DFD) techniques in PHY design processes to ensure the ease of testing, manufacturability, and post-silicon debugging.Collaborate with Validation Architect to develop and implement comprehensive test and validation strategies to ensure that PHY systems meet industry standards (e.g., JEDEC, IEEE, PHY compliance) ,customer requirements, regulatory requirements, and industry certifications..Enable debug features on silicon to ensure smooth debuggabilityDrive PHY DFx changes and improvements based on feedback from production, test, and field data, working closely with manufacturing teams to ensure smooth transition from design to production.Stay up to date with industry trends, emerging test and debug technologies, and best practices, and incorporate them into design practices.Define and implement scan-based testing, boundary scan, and other DFT strategies to ensure that the PHY designs are fully testable and meet production-level testing requirements.Work with cross-functional teams to establish best practices for DFM to ensure that the PHY design is cost-effective and manufacturable at scale, minimizing yield loss and improving manufacturing efficiency.Promote and implement Design for Debug (DFD) techniques, ensuring that designs have appropriate debug hooks and are easy to troubleshoot both pre-silicon and post-silicon.Mentor and provide technical leadership to junior engineers in the areas of DFx methodologies and best practices.Drive collaboration between design, verification, and test teams to integrate DFx strategies into the overall development flow.Provide regular reports and updates to management on the progress of DFx initiatives, including key performance metrics and any challenges encountered.Drive problem solving and come up with innovative solutions. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Master of Science (or a Master of Technology) degree in Electrical Engineering with more than 10 years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 12 years of relevant industry experience. Hands on experience in IP DFx RTL development, timing closure, and flows Working knowledge of RTL coding in Verilog/System Verilog and Debug in OVM/UVM based verification environment Experience in DFx features such as Structural Scan, BSCAN, MBIST, JTAG etc. Good understanding of industry standard DFx flows and compliance methodologies like DUVM, BSDL, ATPG, and GLS Preferred:- To have Mixed Signal IP DFx experience and/or IO DFx experience and/or post-silicon experience Preferred to have exposure in one/more of interface IPs like DDR/LPDDR/UCIe/HBM Preferred to have experience in driving small team of junior engineers and task forces. Need to be a key team player, while being highly energetic and motivated, independent, and self-driven. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that...

Job Description The Client Development Group (CDG) is looking for Physicial Design Engineers with following Responsibilities - Creates bottoms up elements of chip design including but not limited to Device cell and block level layouts, Block level floor plans, abstract view generation, RC extraction and schematic layout verification. Debug using phases of physical design development including parasitic extraction ,clock generation, custom polygon editing, auto place and route algorithms, floor planning, full chip assembly, RV DFM Density and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments. Qualifications You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing. Experience, Skills, Additional qualifications include Proficiency in multiple levels of layout design which includes data path register files and standard cell designs. Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks into the FC floorplan. Ability to comprehend issues of RC delay electromigration, selfheating and cross capacitance. Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Other Locations IN, Hyderabad Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel Qualification : You should possess a BE or BTech or equivalent technical degree in Electronics Electrical engineering with knowledge in Layout Designing.

Technical Requirements: 1. Verification Experience: Strong experience in SoC, sub-system, and block-level verification. Ability to handle different verification stages and methodologies for complex systems. 2. Hands-on Experience with ARM Architecture and AMBA Protocol: ARM architecture familiarity, particularly at the SoC and sub-system level. Expertise in AMBA protocol (e.g., AHB, APB, AXI) and its application in SoC verification. 3. Verification Methodologies: Proficient in UVM/OVM, SystemVerilog, Verilog, and C-based verification methodologies. Solid understanding of testbenches (TB), test cases, and automation methodologies. Experience in test automation scripting with languages such as TCL, Perl, and Python. 4. Exposure to Advanced Verification Techniques: GLS (Gate-Level Simulation) experience is a plus. Power-aware verification knowledge, ensuring low power consumption in designs. 5. Protocol Knowledge: Working knowledge of industry protocols such as PCIe, DDRx, Ethernet, USB, I2C, SPI, among others. Familiarity with AXI, AHB, APB protocols for data communication in embedded systems. 6. RTL Debugging & Tools Proficiency: Strong RTL debugging skills to identify and resolve issues in designs. Well-versed with industry-standard verification tools used in simulation, debugging, and analysis. 7. Building Testbenches & Test Cases: Extensive experience in building testbenches from scratch. Ability to create and implement detailed test cases for different verification scenarios. Expectations from the Role: 1. Communication and Interpersonal Skills: Strong ability to communicate technical concepts effectively both within the team and with other stakeholders. Clear verbal and written communication skills for reporting progress and challenges. 2. Independent and Team-based Work: Ability to work independently on projects or as part of a team. Able to take ownership of tasks and contribute to team discussions effectively. 3. Learning and Adaptability: Ability to learn quickly and adapt to evolving technologies and methodologies. Stay updated with advancements in verification techniques and tools. 4. Ownership and Accountability: Demonstrated ownership of projects, ensuring timely completion and addressing any challenges that arise. Ensuring high-quality results through attention to detail. 5. Leadership & Mentorship: Ability to mentor and lead junior engineers and verification teams. Provide guidance in solving complex problems and ensuring successful project outcomes. 6. Punctuality and Responsibility: Demonstrated punctuality in meeting deadlines and project milestones. Timely execution of tasks and troubleshooting to maintain project timelines. Ideal Candidate Profile: The ideal candidate will have significant experience with SoC verification, ARM architecture, and verification methodologies such as UVM and SystemVerilog. The candidate should possess strong protocol knowledge and be proficient in debugging RTL and automating test scenarios. A key aspect of the role is the ability to work independently, take ownership of tasks, and guide the team in solving technical challenges. Leadership and mentoring abilities are essential, as is the capacity to manage multiple tasks effectively in a distributed work environment.

Technical Requirements: 1. Digital Logic Design & RTL Coding: Strong experience in digital logic design and RTL (Register Transfer Level) coding. Proficiency in Verilog, VHDL, or System Verilog for implementing complex designs. Deep understanding of logic synthesis, timing constraints, and logic optimization. 2. Peripheral Design (High/Low-Speed): Experience in designing high-speed and low-speed peripherals, ensuring compatibility and optimal performance. Knowledge of integrating peripherals within larger system architectures, ensuring robust data flow. 3. Synthesis, Timing Constraints, and CDC: Familiarity with synthesis tools and ensuring the correctness of timing constraints. Experience with Clock Domain Crossing (CDC) and methods to avoid timing hazards in designs. Ability to optimize logic for timing closure and power efficiency during synthesis. 4. Unit Level Verification Setup & Assertions: Hands-on experience in setting up unit-level verification for RTL modules. Proficient in writing assertions to ensure the correctness of designs during simulation and functional verification. 5. Low Power Design Techniques: Exposure to low power design techniques, including managing multiple power/clock domains in complex SoC designs. Ability to design power-efficient modules for consumer electronics or embedded systems. 6. ARM SoC/AMBA IP-based Designs: Exposure to ARM SoC architectures and integration of AMBA (AXI, AHB, APB) protocols into designs. Experience with SoC-level integration, managing both hardware and software interactions in complex systems. 7. Protocol Knowledge (Additional Advantage): Working knowledge of industry-standard protocols, including PCIe, DDRx, Ethernet, USB, I2C, SPI. Ability to implement these protocols in hardware designs for various interfaces. Expectations from the Role: 1. Communication & Interpersonal Skills: Excellent communication skills for interacting with cross-functional teams, stakeholders, and clients. Ability to convey complex technical details clearly, both in writing and verbally. 2. Independent and Teamwork Capabilities: Strong ability to work both independently and as part of a team. Willingness to take initiative and demonstrate leadership in solving technical challenges. 3. Fast Learner & Adaptability: Ability to quickly absorb and apply new technologies, tools, and methodologies. Eagerness to stay updated with trends in digital design and SoC development. 4. Ownership & Accountability: Demonstrated ownership of tasks and the ability to meet deadlines. Ensure that all aspects of the design process are completed with attention to detail and high-quality standards. 5. Punctuality and Responsibility: Strong track record of punctuality, meeting project deadlines, and delivering quality work. Ability to manage multiple design tasks and optimize workflows to maintain timelines. Ideal Candidate Profile: The ideal candidate should have solid experience in digital logic design, particularly with Verilog, VHDL, or System Verilog. They should have a strong foundation in designing both high-speed and low-speed peripherals and optimizing designs for timing and power efficiency. The role also requires familiarity with ARM SoC architectures and integration of AMBA-based IPs. The candidate should be a strong communicator with the ability to work both independently and collaboratively in a fast-paced, distributed work environment. Leadership potential and a demonstrated ownership mindset are essential to the success in this role.

Technical Requirements: 1. RTL Design Expertise: Strong experience in RTL (Register Transfer Level) coding, with a good understanding of logic design principles. Proficiency in writing efficient, optimized RTL code using Verilog, System Verilog, or VHDL. 2. SDC and Constraints Syntax: Deep understanding of SDC (Synopsys Design Constraints) and constraints syntax used in synthesis. Experience in writing and managing timing constraints for designs at both the block and SoC levels. 3. Synthesis Experience (Block/SoC Level): Extensive hands-on experience in synthesis at both block and SoC (System on Chip) levels, ensuring efficient design implementation. Familiar with logical synthesis and physical synthesis techniques for optimizing RTL code. 4. Low Power Synthesis: Experience in low-power synthesis, using techniques such as clock gating, power gating, and multi-voltage domain design to reduce power consumption while maintaining design performance. 5. Optimization Techniques: Strong knowledge of optimization techniques to achieve the best Performance, Power, and Area (PPA) for designs. Familiarity with logic restructuring, retiming, and other optimization strategies to improve design efficiency. 6. Synthesis Tools and Methodologies: Expertise in Synopsys Design Compiler (DCT/DCG) or Cadence Genus/RC for synthesis. Experience with hierarchical synthesis, DFT (Design for Test) handling, and scan insertion. 7. Multi-Power Domain Designs: Familiarity with multi-power domain designs, including managing different power states for various blocks or subsystems in the design. 8. CPF (Common Power Format): Good knowledge of CPF (Common Power Format), used for managing power domains and low-power techniques across designs. 9. Timing and STA (Static Timing Analysis): Strong knowledge of timing concepts and STA for analyzing and ensuring timing closure of the design. Experience in LEC (Logical Equivalence Checking) and CLP (Clock Logic Propagation) to validate the functional correctness of the design. 10. Additional Tools & Concepts: Experience with tools like PTPX and Spyglass for timing analysis, power estimation, and linting. Knowledge of Functional ECO (Engineering Change Order) for making design modifications after the initial synthesis. Proficient in scripting with Perl/TCL for automating synthesis and verification tasks. Expectations from the Role: 1. Debugging and Problem-Solving: Strong debugging skills to identify and resolve issues in complex RTL designs and synthesis-related problems. Ability to troubleshoot synthesis issues related to timing, power, or design constraints. 2. Effective Communication: Excellent communication skills to interact with various stakeholders, including design teams, verification teams, and management. Ability to clearly articulate design choices, challenges, and solutions. 3. Project Focus and Ownership: Ability to stay focused on project goals and drive closure on timely delivery of design work. Ownership of assigned work and ensuring its completion within the agreed timelines. 4. Leadership Skills: Leadership abilities to guide and mentor junior engineers in the team. Ability to lead design projects, ensure best practices are followed, and promote a collaborative team environment. 5. Go-Getter Attitude: Proactive and self-driven with a Go-getter attitude, always seeking opportunities to improve designs, processes, and overall team performance. Ability to take initiative, stay motivated, and continually push for high-quality results. Ideal Candidate Profile: The ideal candidate should have a strong RTL design background with in-depth knowledge of synthesis techniques, low power design, and timing analysis. They should be well-versed with industry-standard tools such as Synopsys Design Compiler and Cadence Genus/RC, and have practical experience with multi-power domain designs. A deep understanding of SDC and timing constraints, along with strong debugging and problem-solving skills, is essential. Additionally, the candidate should have leadership potential, excellent communication skills, and a proactive attitude that drives results.