Verilog Jobs in Noida

Job Overview As a Hardware Engineer at Qualcomm, you will plan, design, optimize, verify, and test electronic systems including ASICs, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, FPGA, and/or DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and drive the launch of world-class products. This role involves deep involvement in the micro-architecture development and RTL design process, ensuring high-quality designs that contribute to Qualcomm s cutting-edge technologies. Key Responsibilities Micro-Architecture & RTL Development: Work closely with the Architecture and Systems teams to develop micro-architecture and RTL design. Front-End Design Quality Checks: Perform quality checks on RTL front-end design (e.g., Lint, CDC, low-power checks, Synthesis). Test Plan Development & Debugging: Collaborate with the functional verification team to develop test plans and debug waveforms at the core, sub-system, and SoC levels. Constraint Development & Timing Closure: Hands-on experience with constraint development and achieving timing closure. Design Optimization & Low Power Checks: Ensure designs are PPA (Power, Performance, Area) efficient and perform low power checks. Post-Silicon Debug: Support sub-system, SoC integration, and chip-level debugging. Mentorship: Lead and guide junior engineers in delivering high-quality IPs on schedule. Cross-functional Contribution: Contribute beyond RTL design to support the end product goals in a flexible capacity. Minimum Qualifications Educational Background: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of relevant experience, or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of relevant experience, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of relevant experience. Skills & Experience ASIC Design: 7-12 years of experience in ASIC design. Micro-Architecture & RTL Design: Strong knowledge and hands-on experience in micro-architecture development and RTL digital design. Front-End Flows: Exposure to front-end flows such as Lint, CDC, low-power checks, Synthesis. Domain Knowledge: In-depth knowledge of LP/PC DDR 2/3/4/5 and protocols like AXI, ACE, CHI, AHB. Communication Skills: Excellent communication skills, with experience working with global teams. Post-Silicon Experience: Experience in post-silicon bring-up and debug is a plus. Mentorship: Proven experience leading or guiding junior engineers. Flexible Contribution: Must be flexible to contribute beyond RTL design to meet end-product goals.

UVM and GenAI Engineer - Automatic Testbench Generation Job Summary: We are seeking an experienced and skilled UVM and GenAI Engineer to join our team. The successful candidate will be responsible for developing innovative solutions using Generative AI to automatically generate testbenches for complex digital designs. The ideal candidate will have a strong background in UVM, digital design verification, and AI/ML. Key Responsibilities: Develop and implement Generative AI algorithms to automatically generate testbenches for digital designs. Collaborate with the design and verification teams to identify areas where AI-generated testbenches can improve verification efficiency and effectiveness. Design, develop, and maintain UVM-based testbenches for complex digital designs. Work with cross-functional teams to integrate AI-generated testbenches into the existing verification flow. Develop and maintain scripts and tools to automate the testbench generation process. Stay up-to-date with the latest developments in UVM, GenAI, and digital design verification. Participate in code reviews and contribute to the improvement of the team's verification methodologies. Requirements: Bachelor's/Master's degree in Computer Science, Electrical Engineering, or a related field. 6+ years of experience in digital design verification, with a focus on UVM-based testbenches. Strong knowledge of UVM, SystemVerilog, and digital design principles. Experience with AI/ML frameworks and tools, such as PyTorch, TensorFlow, or Keras. Programming skills in languages such as Python, C++, or SystemVerilog. Experience with version control systems, such as Git. Strong problem-solving skills, with the ability to work independently and collaboratively. Nice to Have: Experience with Generative AI algorithms and techniques, such as GANs, VAEs, or Transformers. Knowledge of digital design languages, such as VHDL or Verilog. Experience with cloud-based AI platforms, such as AWS SageMaker or Google Cloud AI Platform. Familiarity with Agile development methodologies. What We Offer: Competitive salary and benefits package. Opportunity to work on cutting-edge AI technology and digital design verification. Collaborative and dynamic work environment. Professional development and growth opportunities. Flexible working hours and remote work options. If you are a motivated and talented individual with a passion for UVM, GenAI, and digital design verification, please submit your resume and a cover letter explaining why you are the ideal candidate for this role. Qualification : Bachelor's/Master's degree in Computer Science, Electrical Engineering, or a related field.