Vlsi Engineering Jobs in Bengaluru

Sr. Member of Technical Staff - UI Engineering Location: Bengaluru Company: Aviatrix Experience: 3+ years About Aviatrix: Aviatrix is a leading cloud network security company trusted by over 500 enterprises globally. We specialize in simplifying and securing multi-cloud environments, providing a unified networking solution built specifically for the cloud. Role Overview: UI Engineering (Co-Pilot Team) We are seeking a Senior UI Engineer to join our Co-Pilot product development team. You will design, develop, and maintain high-quality UI solutions that offer customers seamless access to sophisticated cloud management and network security tools. Technical Requirements Core Competencies: Frontend Stack: Advanced proficiency in TypeScript, React, and Node.js. Web Standards: Expert knowledge of HTML5 and CSS3. API Integration: Solid understanding of REST APIs and asynchronous data handling. Version Control: Professional experience with Git and collaborative workflows. Education: BE/B.Tech in Computer Science or related field (or equivalent practical experience). Nice to Have / Bonus Skills: Design Systems: Experience with MUI (Material UI) or in-house design frameworks. Advanced Protocols: Exposure to gRPC, gRPC-web, and Go. Data Visualization: Familiarity with Elasticsearch and high-scale data dashboards. Cloud Domain: Previous experience in cloud networking or security sectors. Key Responsibilities Feature Development: Build efficient, scalable, and well-tested code for the Aviatrix product suite. UX Partnership: Collaborate with UX designers to translate complex requirements into intuitive user interfaces. System Maintenance: Manage bug fixes, UI enhancements, and participate in on-call rotations for field issues. Continuous Improvement: Contribute to the evolution of development processes and product quality. Benefits & Why Aviatrix Comprehensive Health: Private medical coverage, life assurance, and long-term disability. Financial & Growth: Pension scheme and a dedicated annual wellbeing stipend. Time Off: Generous holiday allowance and a flexible approach to work-life balance. Inclusivity: We value unique journeys if you are excited by the role, we encourage you to apply regardless of a perfect "checklist" match.

Engineering Manager Location: Bengaluru Hiring is still shaped by outdated processes manual screening, unconscious bias, and delayed feedback. Talview is transforming this with AI that actually works. We build GenAI-powered hiring and assessment platforms that make recruitment faster, fairer, and scalable. Our AI Products Alvy: The world s first AI Proctoring Agent for intelligent global exam monitoring. Ivy: A conversational AI Interviewer delivering unbiased first-round assessments. Impact: 10M+ assessments delivered across 120+ countries. The Role We re looking for an Engineering Manager to lead high-performing teams, drive architectural excellence, and deliver scalable products globally. You ll guide engineers across backend, frontend, QA, and DevOps, while partnering closely with Product and Design to drive meaningful outcomes. What You ll Do Leadership: Lead, mentor, and grow cross-functional engineering teams. Architecture: Own architecture and system design for cloud-native, distributed systems. Excellence: Champion code reviews, testing, automation, and security practices. Operations: Strengthen engineering processes including CI/CD, observability, and monitoring. Delivery: Own delivery outcomes, sprint planning, and team performance. People: Conduct 1:1s, performance reviews, and career development planning. You Might Be a Fit If You Have Required Qualifications: 6+ years of overall engineering experience; 5+ years in backend (Node.js, Go, or Python). 2+ years with Docker, Kubernetes, and public cloud platforms (AWS, GCP, or Azure). 2+ years in Agile delivery environments (Scrum, Squads, or Chapters). 1+ year experience managing a team of 4+ engineers. Deep understanding of cloud monitoring, deployments, and cost optimization. Bonus Points For: Building SaaS or high-scale distributed systems. Experience with AI-assisted coding tools (Cursor, Windsurf, Codex, etc.). Strong system design and architectural fundamentals. Our Culture: The 5Cs We are guided by Collaboration, Commitment, Credence (trust), Customer-centricity, and Candor. We work together, ship quality, and communicate openly. What You Get Competitive compensation and best-in-class hardware. 5-day work week with flexibility. Monthly team lunches and annual offsites. Accelerated growth in a fast-scaling product organization.

Engineering Manager, Collections Location: Bengaluru Work Type: Full-Time About Postman Postman is the world s leading API platform, enabling over 40 million developers and 500,000 organizations, including 98% of the Fortune 500, to design, test, and collaborate on APIs efficiently. Founded in Bengaluru and headquartered in San Francisco, Postman simplifies the API lifecycle to help teams build better APIs, faster. The Opportunity The Collections team is at the heart of Postman s platform, enabling seamless API collaboration for millions of users. We manage tier-0/1 critical systems handling ~21M requests daily, supporting pillars like API development, testing, prototyping, discovery, distribution, and change management. We are seeking an experienced Engineering Manager to take Collections to the next level leading technical strategy, scaling systems, improving user experience, and growing a high-performing team. This role combines technical leadership, people management, and product vision, directly impacting Postman s growth and user engagement goals. Key Responsibilities Leadership & Team Development Grow and mentor engineers, aligning career growth with business goals. Participate in recruiting, hiring, and onboarding top engineering talent. Define and measure team performance with clear OKRs and real-time feedback. Technical & Strategic Ownership Drive engineering strategy and roadmap for the Collections team. Lead design and code reviews, ensuring high standards across frontend and backend systems. Ensure product reliability, performance, security, and 99.99% availability. Prioritize multi-quarter roadmaps while balancing technical constraints and business needs. Collaboration & Cross-functional Impact Partner with Product, Design, and Engineering teams to deliver a unified, high-quality API collaboration experience. Champion operational and customer excellence through incident management, performance monitoring, and UX issue resolution. About You Experience & Skills Bachelor s degree in Computer Science or equivalent practical experience. 7+ years of software development experience (C, C++, Java, JavaScript, NodeJS). 3+ years in technical leadership roles building impactful products. 2+ years in people management. Experience with microservices architecture and scalable systems. Exceptional written, verbal communication, and stakeholder management skills. Empathetic, collaborative, and committed to creating a positive team culture. Nice-to-Have Experience building customer-focused products at scale. Familiarity with standardizing engineering processes in a growing organization. Flexible hybrid work model with a collaborative and inclusive team. Full medical coverage, flexible PTO, wellness reimbursement, and monthly lunch stipend. Wellness programs, team-building events, and donation-matching initiatives. Opportunities for growth, ownership, and making a measurable impact on Postman s global platform. Our Values Curiosity: Explore boldly and innovate. Transparency: Communicate openly about successes and failures. Focus: Align work with Postman s larger vision. Inclusion: Every team member s voice matters. Excellence: Deliver high-quality products and experiences. Qualification : Bachelors degree in Computer Science or equivalent practical experience

Data Engineering Lead Bengaluru | Engineering | Full-Time About Fam (formerly FamPay) Fam is India s first payments app designed for everyone aged 11 and above. FamApp enables seamless online and offline payments through UPI and FamCard. Our mission is to empower over **250 million young Indians** to start their financial journey early, becoming financially aware and confident. Founded in 2019 by IIT Roorkee alumni, Fam is backed by top-tier investors including Elevation Capital, Y-Combinator, Peak XV (Sequoia Capital India), Venture Highway, and angels like Kunal Shah and Amrish Rao. About the Role We re looking for a visionary **Data Engineering Lead** to take **end-to-end ownership** of Fam s data ecosystem from data ingestion and storage to processing and delivering actionable insights. You ll **define the data strategy and architecture** that supports both batch and **real-time** use cases, ensuring scalability, reliability, and governance across the organization. You will be instrumental in enabling accurate, complete, and trusted data flow that powers business intelligence, analytics, and product decision-making. This role involves **leadership, strategic thinking**, and hands-on problem solving. What You ll Do Own the full data lifecycle: ingestion, organization, storage, processing, and presentation. Define and execute **data architecture and strategy** aligned with operational and analytical goals. Build **scalable, reliable, and observable data systems** supporting batch and near real-time processing. Ensure **data quality, governance, and compliance**, proactively resolving discrepancies. Collaborate with product, engineering, and business teams to define, track, and optimize key metrics. Anticipate data-related challenges and implement preventive solutions. Lead, mentor, and grow the data engineering team, fostering innovation and accountability. Must-Haves 10+ years experience in data engineering, including proven leadership of teams or projects. Expertise designing, building, and scaling end-to-end data pipelines and systems. Deep understanding of the data lifecycle, from ingestion through business reporting. Strong communication skills and ability to collaborate across technical and business teams. Solid knowledge of **data governance, quality assurance, and compliance standards**. Experience with observability and proactive monitoring for data systems. Proficiency in Python and SQL; familiarity with Scala or Java. Hands-on experience with streaming and batch data frameworks. Experience designing large-scale data lakes and warehouses with best practices for schema evolution and partitioning. Strong background with **cloud platforms (AWS, GCP, or Azure)**. Fintech or regulated industry experience is a plus. Good to Have Fintech-specific data experience, including regulatory compliance and reporting. Deployment experience with **real-time analytics** and event-driven architectures. Familiarity with containerization and infrastructure tools like Docker, Kubernetes, Terraform. Knowledge of data observability tools (Monte Carlo, Databand, etc.). Exposure to **ML pipelines** and model deployment. Solve challenging problems at the intersection of big data, real-time processing, and fintech. Lead impactful data initiatives at a rapidly growing startup. Collaborate with a world-class team of engineers, data scientists, and product leaders. Competitive compensation, equity, and benefits. Clear career growth opportunities in leadership and innovation. Perks That Go Beyond the Paycheck Relocation assistance for a smooth move. Free office meals (lunch & dinner). Generous leave policies (birthday, period, parental support, and more). Salary advances and loan policies for financial support. Quarterly rewards, recognition, and referral incentives. Access to the latest gadgets and tools. Comprehensive health insurance with mental health support. Tax benefits like food coupons, phone allowances, and leasing options. Retirement benefits including PF contribution, leave encashment, and gratuity. About FamApp FamApp focuses on financial inclusion for the next generation by offering UPI and card payments to users aged 11+. Our flagship product, FamX, integrates UPI and card payments seamlessly, helping users manage, save, and learn about their finances effortlessly. With over **10 million users**, FamApp is revolutionizing how young Indians transact eliminating the need to carry cash and offering customizable FamX cards with personal doodles for a fun, unique payment experience. Join Our Dynamic Team At Fam, we foster a people-first culture with flexible work schedules, generous leave, comprehensive health benefits, and mental health support. You ll be part of a passionate, talented, and fun team shaping the future of fintech for India s youth.

Engineering Manager, Go-To-Market Technology Salesforce Location: Bengaluru Department: Business Technology Experience: 5+ Years in People & Project Leadership Employment Type: Full-Time About Okta Okta is The World s Identity Company. We empower everyone to securely use any technology, on any device or app, anywhere. With our flexible, neutral platforms Okta Platform and Auth0 Platform we place identity at the core of business growth and security. We value diverse perspectives, experiences, and learning mindsets. You don t need to tick every box we re looking for team players who make us better with their unique insights. The Opportunity We are seeking a dynamic and experienced Engineering Manager to lead a high-performing team within our Go-To-Market (GTM) Technology group. This team builds enterprise-grade technology solutions that support Okta s sales, CPQ, and customer support systems powering growth, operational excellence, and internal engineering velocity. This is a hands-on leadership role where you ll mentor top talent, guide delivery across Salesforce and other SaaS/PaaS platforms, and collaborate cross-functionally to align technology with business priorities. You will play a pivotal role in shaping how technology drives Okta s internal transformation. Key Responsibilities People & Team Leadership Hire, mentor, and retain exceptional engineering and product talent. Cultivate a high-performance, feedback-rich, and growth-oriented culture. Manage a team of analysts and engineers delivering GTM technology solutions. Domain & Project Ownership Provide guidance and decision-making grounded in GTM domain knowledge (Sales, CPQ, Customer Support). Lead medium-to-large projects from concept to delivery, meeting timeline, scope, budget, and quality goals. Drive strategic prioritization of innovation vs. KTLO (Keep The Lights On) activities. Agile & Execution Excellence Champion Agile best practices, backlog health, sprint planning, and delivery tracking. Collaborate with Product Managers and Delivery Leads for sprint execution and release planning. Act as a hands-on Delivery Lead on critical projects when needed. Business Alignment & Stakeholder Management Build trusted relationships with business partners to align technology delivery with evolving business needs. Present project status, risks, and solutions to leadership with clarity and transparency. Constantly evaluate and improve operational processes and tooling for scalability. Qualifications & Skills Must-Have Bachelor s degree in Computer Science or related technical field. 5+ years managing software engineering or cross-functional technology teams. Proven leadership in GTM domains: Sales, CPQ, and Customer Support. Strong experience with enterprise SaaS/PaaS platforms like Salesforce, Workday, NetSuite, Anaplan, Xactly, or Boomi. Deep understanding of business value streams: Campaign-to-Opportunity, Opportunity-to-Order, Order-to-Cash, etc. Track record of success leading Agile software delivery teams. Exceptional stakeholder communication and executive presentation skills. Strong coaching and mentorship experience to develop talent at all levels. Leadership at Okta At Okta, we define leadership by action, not title. We live by 5 core leadership competencies: Build Effective Teams: Leverage diverse talent to solve complex problems. Demonstrate Self-Awareness: Embrace feedback and personal growth. Develop Talent: Grow individuals for both their careers and the business. Drive Results: Deliver consistent, impactful outcomes. Think Strategically: Anticipate trends and craft visionary strategies. Make an Impact: Shape the future of enterprise identity and GTM operations. Lead with Purpose: Build high-impact teams and technology that scale globally. Grow with Us: Continuous learning, coaching, and career development opportunities. Inclusive Culture: Work in a company that values authenticity, innovation, and collaboration. Join Okta and help redefine how identity powers the modern enterprise. Qualification : Bachelors degree in Computer Science or related technical field

Distinguished Engineer Machine Learning Engineering Location: Bangalore Company: Capital One India About Us At Capital One India, we re redefining how technology powers financial services. Our teams work in a fast-paced, intellectually rigorous environment to tackle complex business challenges at scale. By harnessing the power of advanced analytics, data science, and machine learning, we create innovative, patentable solutions that transform customer experiences and drive the business forward. Team Overview: Machine Learning Experience (MLX) The MLX team leads Capital One s mission to build scalable, well-managed ML systems and platforms. We empower teams across the enterprise to develop, govern, and deploy machine learning models efficiently, securely, and at scale. From automated model governance to observability platforms, MLX enables end-to-end ML lifecycle management laying the foundation for AI-driven innovation across the organization. Role Overview We re looking for a Distinguished Engineer Machine Learning Engineering to join our MLX team. In this high-impact role, you'll architect and implement the platforms and tools that support model observability, automated governance, and ML model deployment at scale. This is an opportunity to drive enterprise-wide innovation and shape how ML is integrated into Capital One s core business systems. What You ll Do Design and build systems that capture and analyze large-scale model and feature metadata, including training metrics and runtime performance, to power model observability and governance automation. Partner with cross-functional teams including product managers, designers, and platform engineers to create scalable solutions that accelerate ML model lifecycle management. Lead efforts to enable automated governance decisions for ML models, ensuring compliance, auditability, and operational integrity. Architect and implement high-performance data pipelines that feed ML models with real-time and batch data. Contribute to the design and implementation of cloud-native ML systems using tools such as AWS, Kubernetes, and Terraform. Write clean, scalable, production-grade code in languages like Python, Go, or Java. Implement CI/CD pipelines, testing frameworks, and monitoring systems for ML applications. Drive the adoption of best practices in ML Ops, observability, and platform resilience. Basic Qualifications Master s Degree in Computer Science or related field. 15+ years of experience in software engineering or solution architecture. 10+ years building data-intensive, distributed computing systems. 10+ years programming in Python, Go, or Java. 8+ years of hands-on experience with industry-leading ML frameworks (e.g., Scikit-learn, TensorFlow, PyTorch, Dask, Spark). Preferred Qualifications PhD or Master's in Computer Science, Electrical Engineering, Mathematics, or related field. 5+ years of experience building, scaling, and optimizing production ML systems. Deep expertise in data preparation, feature engineering, and ML pipeline optimization. 10+ years writing performant, maintainable, and resilient production code. Strong experience deploying ML solutions on public cloud platforms (AWS, Azure, GCP). Expertise in distributed systems, file systems, or multi-node databases. Open-source contributor to ML tools or libraries. Published work in ML (papers, patents, blogs, etc.). 5+ years of experience in ML Ops (using MLflow, TFX, Kubeflow, etc.). Experience with LLMs and Generative AI applications (open-source or commercial models). Proven experience designing production-ready observability platforms for ML applications. Be at the forefront of building scalable, secure, and enterprise-grade ML platforms. Shape the future of AI and ML adoption in a top-tier financial institution. Collaborate with world-class engineers and data scientists. Solve real-world problems with high business impact. Thrive in a diverse, inclusive, and innovation-focused culture. Qualification : PhD or Master's in Computer Science, Electrical Engineering, Mathematics, or related field

Principal Associate Full Stack Engineering (GenAI Observability) Location: Bangalore Company: Capital One India About Us At Capital One India, we re tackling some of the most complex problems in financial services using machine learning, advanced analytics, and cloud-first engineering. Our mission is to build cutting-edge, patentable solutions that transform customer experiences, enhance operational efficiency, and ensure robust risk and compliance standards. We re a team of makers, breakers, doers, and disruptors obsessed with turning data into real-world impact at scale. About the Team Machine Learning Experiences (MLX) The MLX team is pioneering the future of model governance, ML observability, and Generative AI infrastructure at Capital One. We re enabling teams to seamlessly deploy ML and GenAI models at scale, with full visibility into performance, health, compliance, and ethical usage. This is the platform powering the next generation of AI-driven financial products across the company. About the Role We re looking for a Principal Associate Full Stack Engineer to lead the development of observability platforms for Generative AI systems. You ll be part of a cross-functional team focused on governance automation, LLM monitoring, and intelligent diagnostics using telemetry data, metadata, and advanced analytics. You ll design systems to collect, analyze, and visualize performance data from our large-scale GenAI infrastructure, helping data scientists and engineers make faster, safer decisions. What You ll Do Lead architecture and development of observability tools and dashboards for monitoring GenAI models and platform health. Design and build core APIs and SDKs to instrument large language models (LLMs) and foundational models (training, fine-tuning, prompting stages). Integrate Generative AI to enable observability features like anomaly detection, predictive analytics, and copilot-assisted troubleshooting. Partner with platform, MLOps, and governance teams to ingest and analyze telemetry, metadata, and runtime metrics at scale. Drive development of tools to ensure compliance with AI ethics, data governance, and industry regulations. Collaborate with product, design, and research to turn complex requirements into scalable, cloud-native software solutions. Lead proof-of-concept initiatives to test and showcase how GenAI can improve platform observability and decision-making. Contribute to the open-source community and stay at the forefront of GenAI and ML infrastructure evolution. Basic Qualifications Bachelor s or Master s degree in Computer Science, Engineering, or related field 4+ years of experience building distributed, data-intensive systems using microservices architecture 4+ years of experience in backend development with Python, Go, or Java 4+ years of expertise with observability stacks (Prometheus, Grafana, ELK) and adapting them for AI systems Strong knowledge of OpenTelemetry, and experience building custom SDKs and APIs 5+ years of hands-on experience with Generative AI models, especially applied to observability, governance, or compliance 2+ years of experience with cloud platforms such as AWS, Azure, or GCP Preferred Qualifications 4+ years building and optimizing ML systems in production environments 3+ years of experience with MLOps tools like MLflow, Kubeflow, or commercial platforms Experience with GenAI frameworks and libraries like LangChain, Haystack, and vector databases (FAISS, Chroma, OpenSearch) Familiarity with emerging observability tools for LLMs such as Langfuse, Phoenix, Helicone, or OpenInference Contributor to open-source GenAI or ML infrastructure projects Author or co-author of published work in AI/ML observability, governance, or performance monitoring Experience with PyTorch, TensorFlow, Spark, or Dask Knowledge of NVIDIA GPU telemetry, CUDA programming, and performance optimization for AI workloads Understanding of AI ethics, data governance, and regulatory frameworks for machine learning systems Why Join Capital One India Work at the intersection of technology, AI, and compliance helping shape the future of responsible AI Join a team driving enterprise-wide adoption of Generative AI Collaborate with world-class engineers, data scientists, and product leaders Enjoy a high-performance culture that encourages innovation, learning, and mentorship Access to cutting-edge tools, open-source contributions, and cloud-native infrastructure Qualification : Bachelors or Masters degree in Computer Science, Engineering, or related field

ASIC Engineer, Implementation Location: Bangalore, India Full Time Company: Meta Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient System on Chip (SoC) and IP for data center applications. Successful candidates must remain in the same role within the team in India for a minimum of 24 months before being eligible for a transfer to another role, team, or location. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for timing, area, and power. Debug timing/area/congestion issues and collaborate with RTL and Physical Designers to resolve them. Perform Power Estimation at both RTL and Gate Level and identify power reduction opportunities. Run Formal Verification checks between RTL and Gate level netlist and debug issues such as aborts, inconclusive, and logic equivalency failures. Perform RTL Lint and work with designers to create necessary waivers. Perform RTL DFT Analysis and improve coverage for Stuck-at faults. Conduct Flat and Hierarchical Clock Domain Crossing (CDC) and work with designers to analyze complex clock domain crossings and sign-off. Conduct Flat and Hierarchical Reset Domain Crossing (RDC) checks and develop reset sequences for RDC in collaboration with Design and Firmware teams. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level SoC designs. Analyze inter-block timing and generate IO budgets for partition blocks. Develop Power Intent Specification in UPF for multi-Vdd designs. Develop automation scripts and methodology for all FE-tools including Lint, CDC, RDC, Synthesis, STA, and Power. Work closely with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks. Collaborate with Physical Design Engineers to provide timing and congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience. 5+ years of experience in Design Integration and Front-End Implementation. Experience with RTL Synthesis and design optimization for Power, Performance, and Area. Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other HDLs. Experience managing multiple design releases and working with cross-functional teams to support and debug timing, area, and power issues. Proficiency with EDA tools and scripting languages (Python, TCL) for building complex toolflows. Experience communicating and collaborating with internal teams and vendors. Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, and LEC. Background in Synthesis, Timing Constraints Development, Floorplanning, and STA. Experience with RTL coding using Verilog/System Verilog. Familiarity with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area analysis techniques for power reduction. Experience with Low Power design and tools like Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools. Strong programming and scripting skills using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it revolutionized how people connect. Apps like Messenger, Instagram, and WhatsApp have empowered billions globally. Meta is now advancing beyond 2D screens into immersive experiences like augmented reality and virtual reality, shaping the future of social technology. Meta provides an opportunity to be part of creating a future where digital connection transcends screens, distances, and even the rules of physics. Equal Employment Opportunity: Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other legally protected characteristics. Qualification : Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm, a leading innovator in technology, is pushing the boundaries of possibility to drive the digital transformation and create a smarter, more connected future. As a Hardware Engineer at Qualcomm, you will play a key role in designing, optimizing, verifying, and testing a wide range of electronic systems. This includes everything from circuits, mechanical systems, digital/analog/RF/optical systems, and test systems, to FPGA and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch world-class products. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3+ years of experience in Hardware Engineering or a similar field. OR Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 2+ years of experience in Hardware Engineering or a related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field, with 1+ year of experience in Hardware Engineering or a related field. Experience: 7 to 10 years Key Responsibilities and Skills: Physical Design Expertise: Extensive experience with block-level physical design, including a strong understanding of the PnR cycle. Industry-Standard Tools: Proficiency in industry-standard physical design tools like ICC2 and Innovus. Signoff Tools: Solid understanding and hands-on experience with signoff tools such as PrimeTime, Redhawk, and Calibre. Technical Leadership: Ability to guide and mentor junior engineers, helping them resolve technical challenges effectively. Tools & Scripting: Experience with tools like ICC/Innovus, PrimeTime (PT), StarRC, Redhawk, and Calibre DRC/LVS. Proficient in scripting languages such as TCL and Perl.

Job Title: Sr. Engineering Manager - Data Engineering Level: L5 Experience: 13-16 years Overview We are seeking an experienced Engineering Manager with a strong background in Data Engineering, including ETL/ELT processes and cloud-based data platforms such as Snowflake. The ideal candidate will lead and mentor a team of data engineers, drive data architecture initiatives, and work closely with cross-functional stakeholders to ensure our data infrastructure supports evolving business needs. Key Responsibilities Team Leadership: Lead, mentor, and develop a high-performing data engineering team, fostering a culture of collaboration, innovation, and continuous learning. Data Pipeline Development: Oversee the design, development, and maintenance of robust ETL/ELT pipelines to ingest, transform, and process data at scale. Cloud Data Infrastructure: Drive the architecture and implementation of cloud-based data solutions, especially leveraging Snowflake, ensuring scalability, security, and reliability. Cross-Functional Collaboration: Partner with product managers, analysts, data scientists, and other business stakeholders to gather requirements and prioritize engineering efforts that deliver the most impact. Architecture and Design: Develop and enforce data architecture standards for high-performance data warehousing, ensuring seamless data integration across diverse sources. Performance Optimization: Identify and resolve performance bottlenecks, focusing on query optimization, cost management, and resource efficiency. Data Quality & Governance: Define and implement data quality frameworks and governance practices, ensuring data consistency and reliability across all pipelines. Innovation & Strategy: Stay informed on emerging data technologies and industry best practices, continuously improving processes and aligning solutions with long-term data strategies. Required Skills 8+ years of hands-on experience in data engineering, including 5+ years in a leadership role. Strong expertise in ETL/ELT processes and hands-on experience with tools like Talend, Informatica, or similar platforms. Deep proficiency in Snowflake or comparable cloud data platforms such as Redshift or BigQuery. Advanced SQL skills, including query optimization, performance tuning, data modeling, and schema design. Hands-on experience with Python or Java for data processing and automation. Knowledge of data governance, compliance standards, and data security best practices. Excellent communication and project management skills, with the ability to prioritize and manage multiple projects in parallel. Preferred Skills Exposure to Big Data technologies such as Spark, Hadoop, Databricks, Synapse, etc. Experience with workflow orchestration tools like Apache Airflow or AWS Step Functions. Familiarity with CI/CD pipelines and DevOps practices within data engineering. Experience working with BI tools like Tableau or Power BI, and reporting integrations.

Job Title: RTL Design Engineer Job Description: Join Intel s Design Team and contribute to the development of high-quality Intel products. In this role, you will work on RTL tool flow methodologies, leveraging industry-standard design tools and scripting environments such as Perl and Python to enhance design automation and optimization. Key Responsibilities: Work on digital design concepts and RTL design using Verilog. Develop and implement RTL tool flow methodologies to optimize design efficiency. Utilize industry-standard design tools to enhance digital design workflows. Develop scripts using Perl and Python to automate design processes. Apply computer architecture knowledge to drive innovations in design methodologies. Qualifications & Requirements: Educational Qualifications: Master s (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions. Technical Skills & Experience: Strong understanding of digital design concepts and computer architecture. Experience with RTL design using Verilog. Proficiency in scripting languages such as Perl and Python for automation. Familiarity with industry-standard design tools and RTL tool flow methodologies. About the Client Computing Group (CCG): The Client Computing Group (CCG) at Intel leads the development of PC products and platforms, spanning notebooks, desktops, 2-in-1s, and all-in-one devices. By collaborating with industry partners, CCG delivers cutting-edge computing experiences that enable users to create, connect, and innovate. As Intel s largest business unit, CCG plays a pivotal role in driving technological advancements and product innovation. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Professional development and career growth opportunities. Qualification : Masters (M.Tech/MS) degree in Computer Science, Electrical Engineering, Electronics, Telecommunications, Microelectronics, or VLSI from IITs, NITs, or equivalent institutions.

Job Title: CPU/Core Design Engineer (Intern) Job Description: Join Intel s Core and Client Development Group (C2DG) and contribute to the development of leading-edge CPU and Core technologies. In this role, you will be involved in CPU/Core design activities across various domains, supporting Intel s ongoing and next-generation Core CPUs. Key Responsibilities: Contribute to CPU/Core logic design for Intel s high-performance processors. Support pre-silicon verification, system validation, and firmware development. Assist in physical design, layout, and DFT (Design for Testability) engineering. Work with cross-functional teams to ensure high-quality and efficient CPU designs. Utilize industry-standard tools and methodologies for design and validation processes. Qualifications & Requirements: Educational Qualifications: Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in: Microelectronics & VLSI Digital System Design Computer Architecture Preferred Skills: Logic Design and digital circuit design fundamentals. Pre-Silicon Verification using simulation and validation techniques. Physical Design & Layout methodologies for semiconductor products. DFT (Design for Testability) Engineering. System Validation for ensuring reliability and performance. Firmware development related to CPU architecture and microarchitecture. About the Core and Client Development Group (C2DG): The Core and Client Development Group (C2DG) is a global organization responsible for the development and integration of SoCs, Core processors, and critical IPs that power Intel s flagship products. C2DG drives the client roadmap for Intel s Client Computing Group (CCG), delivers server-first cores for Data Center Group (DCG), and invests in future disruptive technologies. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, ensuring fair consideration for all applicants regardless of race, color, religion, gender, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a highly competitive total compensation package, including: Competitive pay, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career growth. Qualification : Currently pursuing a Postgraduate Degree (M.Tech or equivalent) from a reputed institute in:

Job Description Join Intel s world-class Graphics Physical Design Team, working on high-performance GPUs/GFX targeting high-end graphics, gaming, artificial intelligence, and media processing. This is an exciting opportunity to collaborate with a talented team early in the product lifecycle, driving innovation in RTL-to-GDSII implementation for multi-million gate designs on advanced process nodes. Key Responsibilities: RTL-to-GDSII implementation, including logic synthesis, physical synthesis, and routing. Clock tree synthesis, performance verification (static timing), noise and power verification. Conduct ERC (Electrical Rule Check), reliability verification, and layout verification. Work closely with design automation, methodology, and product integration teams to enhance execution efficiency and quality. Contribute to process improvements and methodology advancements. Qualifications & Requirements: Educational Qualifications: Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design. Preferred Skills: Strong fundamentals in Digital VLSI design and RTL-to-GDSII ASIC Design flow. Excellent problem-solving skills and a strong ability to learn new concepts and methodologies quickly. Basic knowledge of UNIX/Linux environments and scripting languages such as Perl, Python, and TCL (a plus). About the Client Computing Group (CCG): The Client Computing Group (CCG) drives Intel s PC business strategy and product development, spanning notebooks, desktops, 2-in-1s, and all-in-one systems. Working alongside industry partners, CCG delivers cutting-edge computing experiences that empower users to focus, create, and connect. As Intel s largest business unit, CCG continues to innovate aggressively, investing in leadership products, next-generation technologies, and scalable IP solutions. Intel s Commitment to Diversity & Inclusion: Intel is an equal opportunity employer, providing fair consideration to all applicants regardless of race, color, religion, gender, sexual orientation, national origin, disability, veteran status, or any other protected characteristic under local law. Intel offers a best-in-class compensation and benefits package, including: Competitive salary, stock options, and performance-based bonuses. Comprehensive healthcare, retirement plans, and paid time off. Opportunities for professional development and career advancement. Qualification : Final-year M.Tech students specializing in Electrical, Electronics, or Microelectronics Engineering, with exposure to Semiconductors and VLSI design.

Job Title: Hardware Engineer General Summary: Qualcomm, a leading technology innovator, is at the forefront of next-generation experiences and digital transformation. Our mission is to create a smarter, more connected future by pushing the boundaries of hardware engineering. As a Hardware Engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of cutting-edge electronic systems. You will work on digital, analog, RF, and optical systems, covering circuit design, mechanical systems, test systems, FPGA, DSP, and packaging. Collaborating with cross-functional teams, you will develop high-performance solutions that meet industry-leading standards. Key Responsibilities: Front-End Design & Implementation: Develop and implement MSIP designs (Temperature/Voltage/Security Sensors, Controllers). Perform RTL development and validation, ensuring compliance with linting, clock-domain crossing (CDC), conformal low-power, and DFT rules. Verification & Debugging: Collaborate with the functional verification team to define test plans and debug issues. Support SoC integration and chip-level pre/post-silicon debugging. Synthesis & Timing Analysis: Develop timing constraints and deliver synthesized netlists to the physical design team. Provide constraints support for static timing analysis (STA). Write Unified Power Format (UPF) for power-aware equivalence checks and low-power validation. Design for Testability (DFT): Insert DFT structures and perform ATPG analysis to optimize Stuck-at Fault (SAF) and Transition Delay Fault (TDF) coverage. Minimum Qualifications: One of the following: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience. Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience. Preferred Skills & Experience: 6+ years of experience in hardware engineering, preferably in front-end design and verification. Expertise in micro-architecture development, RTL design, and front-end flows (Lint, CDC, Low-Power Checks, etc.). Hands-on experience with synthesis, DFT, formal verification (FV), and STA. Exposure to post-silicon bring-up and debugging is a plus. Strong ability to collaborate with global teams and excellent communication skills. Work with industry-leading technology in a highly innovative environment. Be part of a collaborative, global team that values technical excellence. Enjoy a competitive salary, professional development, and growth opportunities. Qualification : Masters degree in Computer Science, Electrical/Electronics Engineering

Position: VLSI Trainer Experience: 3 8 years Education: M.Tech in VLSI / B.E. in Electronics and Communication Engineering (ECE) Industry: Education, E-Learning, Semiconductor Job Type: Training Job Description We are seeking an experienced VLSI professional with strong expertise in digital design and verification to join our training team. The ideal candidate should have a passion for teaching and hands-on experience in VLSI design and verification methodologies. Key Responsibilities: Conduct training sessions on Digital Design, SystemVerilog (SV), UVM, Verilog, VHDL, DFT, and related tools. Provide hands-on support and guidance to trainees on various projects. Debug and troubleshoot source code in Verilog, SV, and UVM. Develop and support training projects and technical content. Deliver high-quality training sessions and post-training support. Desired Skills & Experience: Proficiency in Digital Design, Verilog, VHDL, SystemVerilog (SV), UVM, DFT, and Physical Design. Experience working with Mentor Graphics EDA, Cadence, or Synopsys tools is a plus. 3 to 8 years of experience in the semiconductor industry, teaching, or training. Strong communication and presentation skills. Mandatory Requirements: Solid understanding of VLSI design and verification concepts. Excellent problem-solving abilities and debugging skills. Qualification : M.Tech VLSI/BE ECE

Position: VLSI Trainer (Entry Level) Experience: 0 1 year Education: M.Tech in VLSI / B.E. in Electronics and Communication Engineering (ECE) Industry: Education, Training, Semiconductor Job Type: Training Job Description We are looking for an entry-level VLSI professional to join our training team. The ideal candidate should have a strong foundation in VLSI concepts, with a keen interest in guiding and mentoring trainees. Key Responsibilities: Develop and support projects related to VLSI design and verification. Debug and troubleshoot source code in Verilog, SystemVerilog (SV), and UVM. Monitor trainees progress and provide constructive feedback. Act as the primary point of contact for trainees' technical queries. Qualification : M.Tech in VLSI / B.E. in Electronics and Communication Engineering (ECE)

Position: Business Development Manager B2B Institutional Sales Experience: 3 6 years Education: B.E / B.Tech in EEE / ECE (preferred) with MBA Industry: Education, IT Sales Job Type: B2B Institutional Sales (Business Development) Job Description We are seeking a Business Development Manager with experience in B2B institutional sales to drive growth and expand our presence in India and South Asia. The ideal candidate will have a proven track record in business development, relationship management, and sales strategy execution, particularly in the education and IT sectors. Key Responsibilities: Contact potential universities and engineering colleges to establish rapport and arrange meetings. Increase the value of current customers while attracting new clients. Identify and develop new markets to improve sales across India and South Asia. Organize webinars and seminars for universities and colleges to present VLSI training services and promote technical training programs. Attend online and in-person conferences, meetings, and industry events within the training and education sectors in India and South Asia. Achieve sales growth and meet defined targets by effectively managing the sales process and operations. Acquire and manage customers (academia/universities) by interacting with management and key decision-makers. Prepare and deliver engaging presentations and product demonstrations. Analyze data, forecast sales, and manage budgets to develop strategic, customer-specific sales plans. Maintain a successful track record in B2B sales and negotiations, including preparing quotes, creating proposals, and offering tailored solutions. Negotiate pricing and close deals to achieve sales objectives. Conduct market research to identify new opportunities and stay updated on industry trends. Plan and implement effective sales strategies to drive growth and increase market share. Qualification : B.E/B.Tech in EEE/ECE preferred with MBA

Experience: 4+ Years (Bachelor s) | 3+ Years (Master s) | 2+ Years (PhD) Company Overview As a leading technology innovator, Qualcomm pushes the boundaries of what s possible to enable next-generation experiences and drive digital transformation, helping to create a smarter, connected future for all. Qualcomm Hardware Engineers collaborate with cross-functional teams to plan, design, optimize, verify, and test cutting-edge products, enabling transformative solutions in the hardware space. Role Overview The SRAM Design Engineer will be responsible for the design, verification, and optimization of SRAM (Static Random-Access Memory) blocks for advanced process nodes. This role requires deep expertise in custom circuit design, low-power methodologies, and process technology trends. The ideal candidate will work on complex memory designs, collaborate with cross-disciplinary teams, and contribute to Qualcomm's next-generation hardware solutions. Key Responsibilities Design and develop SRAM circuits for advanced technology nodes (FinFET and beyond). Perform schematic design, simulation, and verification of memory circuits to meet performance, power, and area (PPA) targets. Optimize designs for low-power, high-speed, and high-density applications. Collaborate with layout engineers to ensure design compliance with foundry design rules and assist in layout optimization. Analyze and resolve design for manufacturing (DFM) and yield issues. Work closely with cross-functional teams (architecture, verification, and technology teams) to meet design specifications and performance requirements. Utilize SPICE simulations and other EDA tools to validate circuit functionality and robustness under process, voltage, and temperature (PVT) variations. Contribute to the post-silicon bring-up and debugging of memory-related issues. Qualifications Minimum Requirements: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 4+ years of relevant work experience. OR Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field and 3+ years of relevant work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, or a related field and 2+ years of relevant work experience. Technical Skills: Expertise in SRAM design, simulation, and verification. Strong knowledge of circuit design principles, including timing, noise, and power analysis. Experience with advanced process technologies (FinFET, 7nm, 5nm, 3nm). Proficiency with SPICE-based simulators and EDA tools for circuit analysis. Understanding of memory architecture, power management techniques, and design for yield (DFY) methodologies. Familiarity with DFM practices, chip integration, and physical design constraints. Preferred Qualifications: Experience in low-power SRAM design and assist circuits (read/write assist). Knowledge of self-repairing memories and redundancy schemes. Exposure to silicon validation, post-silicon debug, and memory characterization. Excellent problem-solving and communication skills.

Job Description and Requirements Synopsys is seeking a creative and talented engineer to fill a FPGA Design & Verification role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities. About the Role The FPGA Design and Verification IP Prototyping team is responsible for building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and testing them to verify compliance with leading-edge industry standards. We play a vital role in supporting Synopsys IP business by validating key features and mitigating potential ASIC faults early in the prototyping phase. Responsibilities Design, implement, and verify FPGA-based systems for a variety of applications Validate FPGA-based IP prototypes against real-world devices, test equipment, and other hardware systems Create and maintain comprehensive technical documentation Develop and execute test plans and routines Detect, troubleshoot, debug, and investigate potential ASIC issues early on Collaborate with cross-functional teams, internal and external customers Key Qualifications Bachelor's or Master's degree in Electrical Engineering 1+ years of experience in FPGA design and development Design and simulate integrated circuitry using Verilog, SystemVerilog, and VHDL Familiarity with industry-standard interfaces and protocols such as AMBA AXI, APB, I2C, and SPI Expertise with scripting languages such as Tcl, Python, Perl, and Bash Proven problem-solving skills and ability to work in a collaborative team environment Excellent verbal and written communication skills in English Preferred Experience Familiarity with SCM tools like Git Experience with FPGA development tools such as Vivado or Altera Quartus Familiarity with laboratory equipment such as oscilloscopes and data analyzers Knowledge of the MIPI-I3C protocol Understanding of computer architecture and operating systems Qualification : Bachelor's or Master's degree in Electrical Engineering

Introduction As a Hardware Developer at IBM, you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Required Technical and Professional Expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical and Professional Expertise Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.