Design Verification Engineers Job in Ambit Semiconductors

Design Verification Engineers

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Job Summary

Job Description

  • Expert in UVM / OVM for Verification
  • System verilog assertions Perl Functional + Code Coverage
  • Verilog and VHDL
  • Cadence IUS (preferred) or Mentor Questasim
  • Image Sensor knowledge is a plus
  • Experience with SPI / I2C is a plus

Qualification :
B.Tech / M.Tech or equivalent from a reputed University
Experience Required :

2 to 8 Years

Vacancy :

2 - 4 Hires

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