Design Verification Engineer Job in Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Position Description:
  • Functional Verification Engineer for Serdes/PHY IP development team.
  • Position is based in Bangalore.
  • The role would include functional verification of the Serdes/PHY IP solution of Cadence.
  • The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
  • The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team particularly with respect to functional and code coverage.
  • PHY level protocol knowledge is desirable USB2.0, USB3.0, Pcie, SATA, Ethernet.

• Position Requirements:
  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with 5yrs of experience as a design and verification engineer, with a large portion of the recent work experience on verification environment development.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development are a must.
  • System Verilog experience and experience with UVM/Specman based functional verification environment development is required.
  • PHY protocol experience is highly desirable(USB2.0, USB3.0, Pcie, SATA, Ethernet). Prior experience in functional verification and debugging of complex protocols is a must.
  • AXI/APB experience is a desirable.
  • Prior experience in IP development teams would be an added advantage.

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