BriefCase
BriefCase

Memory Layout Engineer Job in Gaffis Technologies Private Limited

Memory Layout Engineer

Gaffis Technologies Private Limited 4+ weeks ago
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Job Summary Technical Skills
  • Migration of layout from one tech node to another
  • Block and top-level integration
  • EM-IR, area-intensive layouts, Quality checks (QC)
  • Understanding of design rules for planer and FINFET CMOS technologies
  • Drive multiple projects and provide necessary technical guidance to the engineers
  • Experience in developing flash memories.
  • Memory Layout experience in the development of low-power, high-performance, high-density SRAM memories for 5nm to 180nm technology nodes
  • Expertise in Custom / Compiler Memory Layout
  • Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies.
  • Understanding of DFM and DFY checks.
  • Understanding of memory compiler architectures and subblocks.
  • Knowledge of scripting in PERL/Shell/TCL/Skill is a plus.
  • Strong VLSI fundamentals of semiconductor devices and physics, electrical circuits, and IC Experienced with Cadence Virtuoso/XL/Advance platform and features
  • Clones, Modern, Wire assistance, Chaining, Groups and Place and Route
  • Experienced with Calibre/PVS/Assura/Hercules PV tools.

Desired Candidate Profile:
  • 1 plus years of experience with Memory Layout Design.
  • The candidate must have a Bachelor's or Master's in (EC/ME/VLSI)
  • Good Verbal written communication skills.
  • Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
  • Set aggressive goals and meet/beat the commitments.
  • Flexible enough to work in a dynamic environment and multitask seamlessly.
  • Ability to work independently and in a team.
Note: Once we received your Job Application we will contact you for the interview. Please do not call to ask status, we will update you on your status for the Job application.
Experience Required :

Minimum 1 Year

Vacancy :

2 - 4 Hires

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