Rtl Engineer Job in Invecas
Job Summary
Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goalsContribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan effortsResponsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering teamYou handle Verilog RTL logic design and debugDevelop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementationContribute as a design engineer developing the next-generation of multi-core processorsSpecify, design, and synthesize RTL blocks, optimize and floorplan themWork with verification engineers to ensure their accuracy
Experience Required :
Minimum 3 Years
Vacancy :
2 - 4 Hires
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