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BriefCase

Wlan Subsystem Design Lead (staff Eng) Job in Qualcomm

Wlan Subsystem Design Lead (staff Eng)

Qualcomm 4+ weeks ago
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Job Summary General Summary: Qualcomm CDMA Technologies (QCT) is the world s largest provider of wireless chipset technology, leading the way in 5G and Wi-Fi advancements. As an inventor-driven company, Qualcomm is committed to transforming industries and creating new possibilities through groundbreaking connectivity technologies. Qualcomm is currently seeking experienced WLAN Digital Designers for its Wireless R&D team in Bangalore. This role will involve designing next-generation WLAN chipsets and Wi-Fi subsystems, including Wi-Fi 6, 7, and 8 technologies. As part of the QCT Bangalore Wireless R&D HW team, you will be involved in sub-system architecture, RTL design, and its integration, contributing to industry-leading technologies in Wi-Fi connectivity for consumer devices such as hearables, wearables, and IoT applications. Key Responsibilities: Design and develop next-generation WLAN and micro-Wi-Fi subsystems for connectivity, hearables, wearables, and IoT chips. Work on ASIC designs using the latest technology nodes, understanding and executing all aspects of the VLSI development cycle, including architecture, micro-architecture, RTL design, and integration. Collaborate closely with Verification, SoC Design, Validation, Synthesis, and PD teams to achieve design convergence. Develop micro-architecture and implement designs in Verilog/SV. Integrate complex subsystems into SoCs. Perform various design checks and tool analyses using tools like Spyglass, RDC, CDC, PrimeTime, Synthesis, and more. Conduct post-silicon debug and work with cross-functional teams to resolve issues and optimize designs. Work independently on defined tasks, with minimal guidance, while maintaining a strong team-oriented approach. Required Skills and Experience: 8+ years of experience in digital front-end design for ASICs. Strong expertise in RTL coding using Verilog, VHDL, or SystemVerilog (SV) for complex designs, including those with multiple clock domains. Experience in low-power design methodology and clock domain crossing designs. Familiarity with various bus protocols like AHB and AXI. In-depth understanding of the RTL to GDS flow and experience interacting with DFT and PD teams. Experience in 802.11 (Wi-Fi) and wireless IP/subsystem design is a plus. Post-silicon debug experience is an added advantage. Strong documentation and communication skills to effectively interact with team members and management. Self-motivated with a teamwork-oriented attitude and the ability to work independently. Minimum Qualifications: Bachelor s degree in Computer Science, Electrical/Electronics Engineering, VLSI, Communications, or a related field, and 3+ years of Hardware Engineering or related work experience. Master s degree in the above fields and 2+ years of relevant experience, OR a PhD with 1+ year of related work experience.
Experience Required :

Fresher

Vacancy :

2 - 4 Hires

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