ASIC ,Verilog, VHDL, R And D Engineer Job in Schindlers Incorporated

Position : Rand D EngineerCompany : A SEICMM level 5 Software CompanyLocation : Bangalore.Skills :Minimum of 2 years experience in any of the following skills: VHDL/Verilog , ASIC Design Flow , Simulation Skills, Synthesis and Timing analysis , Logic Design, UnixC/C++ , Physical designEDA tools.

Minimum Requirements

Very good in Designing - ASIC ,Verilog / VHDL.Domain Experience in one of the areas like Memory Controller Design, Bus Interfaces.

B.Tech/B.E.