Dft_sr Engineer Job in Spectrum Consultants India Pvt Ltd
Dft_sr Engineer
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Bengaluru, Bangalore Urban, Karnataka
- Not Disclosed
- Permanent
Job Summary
-Title: DFT
Experience: 2-4 Years
Job Description:
As a DFT expert you will be a part of the WD ASIC team and working on leading edge of data storage
controllers.
You will support ASIC flow from DFT architecture definitions, through implementation and
verification till mass production test program and RMA failure analysis.
Preferred Qualifications & Skill:
B.E / B.Tech / M.E / M.Tech Degree.
Experience in the DFT concepts.
Hands on experience on either DFT DRC and DFT insertion or ATPG pattern generation
Experience in Pattern simulations Zero delay and timing.
Knowledge & actual work with SCAN insertion & ATPG tools.
Responsibilities:
Scan implementation at full chip /sub chip level using DFT compiler, ATPG.
The individual will be responsible for full chip Synthesis environment for low power, high performance
designs, development-debug of interface and core side constraints, clock tree analysis and assisting
full chip timing convergence and timing closure.
Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess
best in class tools / capability and benchmark them to drive compelling adoption arguments.
The individual will also drive IP integration strategies that ensure quality ASICs and avoid schedule
surprises
Work-Location : Bangalore
Experience: 2-4 Years
Job Description:
As a DFT expert you will be a part of the WD ASIC team and working on leading edge of data storage
controllers.
You will support ASIC flow from DFT architecture definitions, through implementation and
verification till mass production test program and RMA failure analysis.
Preferred Qualifications & Skill:
B.E / B.Tech / M.E / M.Tech Degree.
Experience in the DFT concepts.
Hands on experience on either DFT DRC and DFT insertion or ATPG pattern generation
Experience in Pattern simulations Zero delay and timing.
Knowledge & actual work with SCAN insertion & ATPG tools.
Responsibilities:
Scan implementation at full chip /sub chip level using DFT compiler, ATPG.
The individual will be responsible for full chip Synthesis environment for low power, high performance
designs, development-debug of interface and core side constraints, clock tree analysis and assisting
full chip timing convergence and timing closure.
Additional responsibilities include proactively working with the DFT teams and EDA vendors to assess
best in class tools / capability and benchmark them to drive compelling adoption arguments.
The individual will also drive IP integration strategies that ensure quality ASICs and avoid schedule
surprises
Work-Location : Bangalore
Experience Required :
2 to 4 Years
Vacancy :
2 - 4 Hires
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