Analog Design Engr, Sr Ii Job in Synopsys
Analog Design Engr, Sr Ii
Synopsys
4+ weeks ago
- Hyderabad, Telangana
- Not Disclosed
- Full-time
Job Summary
Skills Required :
In this role, you will work on design, development, troubleshooting, and debugging of multi-Gb/s SERDES IP. You will be part of a fast growing analog and mixed signal R&D team developing high speed analog integrated circuits. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Key Qualifications
- In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
- Exposure to SERDES sub circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, LC VCO, Clock and Data Recovery Circuits, DLL, BGR, Regulators)
- Aware of ESD issues (ie. circuit techniques, layout)
- Familiarity with custom digital design (ie. high speed logic paths)
- Knowledge of design for reliability (ie. EM, IR, aging)
- Knowledge of layout effects (ie. matching, reliability, proximity effects)
- Familiar with Custom design and/or Cadence, HSPICE, HSIM,Ultrasim,etc
- Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB)
- Some knowledge of system level budgeting (ie. jitter, amplitude, noise)
- Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise)
- Good communication and documentation skills
Skills Required :
- In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
- Exposure to SERDES sub circuits (ie. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL, LC VCO, Clock and Data Recovery Circuits, DLL, BGR, Regulators)
- Aware of ESD issues (ie. circuit techniques, layout)
- Familiarity with custom digital design (ie. high speed logic paths)
- Knowledge of design for reliability (ie. EM, IR, aging)
- Knowledge of layout effects (ie. matching, reliability, proximity effects)
- Familiar with Custom design and/or Cadence, HSPICE, HSIM,Ultrasim,etc
- Exposure to scripting for post processing of simulation results (ie. TCL, PERL, MATLAB)
- Some knowledge of system level budgeting (ie. jitter, amplitude, noise)
- Aware of signal integrity issues (ie. effects of packaging, board parasitics, crosstalk, noise)
- Good communication and documentation skills


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