Asic Digital Design Engr, Sr I Job in Synopsys

1.SV verification of SERDES / PHY IPs internally developed. Responsibility includes -
a.Verification plan development and review.
b.Verification environment development. UVM knowledge preferred.
c.RTL, GLS & Co-simulations & coverage closure.
d.Deliver high quality RTL and other simulation models to customer.
e.Verification using internal or 3rd party VIP for the protocol of interest.
f.Debug of simulations, including those of real signals modeled using SV for analog.
2.Understand protocols (eg: 25G/50G/100G Ethernet, PON, other networking protocols) and participate in technical reviews
3.Participate in technical reviews and contribute actively
4.Participate in customer support with bring-up of IP in customer simulation environment.
5.Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest.
6.Follow and improve development process ensuring high quality output.