Asic Digital Design Engr, Sr Ii Job in Synopsys

Senior ASIC Digital RTL Design Engineer

In this role selected candidate will be working on top-level Digital design for high-speed serdes with a data range of 8G->56G.

Key Qualification

• Typically requires 7+years of RTL design experience
• Designs RTL for Low power digital portion of 56Gbps serdes
• Familiarity with RTL design for Highspeed & low power circuits
• Low power concepts
• Working knowledge of at least two of the tools Design compiler/Formality, Spyglass/ Prime time/ DFT tetra max/VC-LP is required
• DFT concepts and working experience with Tetra max is a huge plus.
• Scripts skills such as Perl, Python preferred
• Self-motivated, hardworking and innovative in bringing solutions to complex problems.
• experience in leading a team of 3-5 engineers is preferred.
• Experience with bug tracking softwares JIRA,Mantis is preferred

• Domain knowledge of protocols sata/pcie/usb/ethernet is a significant advantage
• Prior working knowledge of Serdes digital circuits is preferred.