Asic Synthesis Job in Tessolve

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 6+

Location: Bangalore

Requirements:

• Good understanding of VHDL or System Verilog.
• Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.
• Development of signoff quality SDC constraints and the development of power intent constraints.
• May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
• Hands-on with Synopsys DC/DCT/DCG/DE-Explorer.
• Hands-on with Synopsys Prime Time including SDC constraint development for complex blocks with many clock domains.
• Hands-on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
• Experience with either RTL development or Physical Design is also a plus.