Soc Faculty / Trainer Job in Utl Technologies Ltd

Qualification and Experince

PG / P.hd with 3-7 years with industry work experience, and skill set

• Teach M.Tech Courses
• Guide M.Tech Projects
• Work on Research projects
  • Design creation using Verilog to optimize performance, area,
    and power using Cadence EDA tools
  • Initial Verification and Debugging Test Failures.
  • Specifying Cover Points, Reviewing Functional and Code
    Coverage results and assisting to increase coverage.
  • Providing assistance to resolve synthesis and timing analysis issues.
  • Design Documentation Creation

• Asic Design
• Verilog
• STA
• FPGA
• Verilog, system Verilog
• AMBA/USB/PCI protocol
• Knowledge on UVM/VMM/OVM
• Knowledge on Processors 8051/ARM/Cortex