Engineer - Virtual Platforms Job in Vayavya Labs Pvt. Ltd.

You will work on the development of Virtual models in C++. You will be responsible for design, implementation and testing these models.

Key Technical Skills:

• Must have hands-on working experience with design, implementation and testing of SystemC peripheral models
• Proficient in TLM2.0 modeling, including loosely timed and approximately times models and use of generic payload
• Prior experience in modeling peripherals with different on-chip and off-chip interfaces like USARTs, Timers, SPI controllers, DMA controllers, I2C controllers, Interrupt controllers, Ethernet, PCIe, controllers etc.
• Solid fundamentals in SoC architecture, well versed with concepts like DMA, interrupt architecture, queuing and arbitration in hardware
• Exposure to Python or Tcl (Good to have)
• Exposure to Virtual Platforms (VP) integration, software bring-up and debugging on Virtual Platforms (Good to have)