Rtl Design Engineer Job in Wafer Space

Wafer Space is looking for some expert RTL Front End Design Engineers, having good knowledge of ASIC design flow. This will be a very challenging and exciting role and will involve very complex designs.

Job Responsibilities-

• Chip integration of high complexity SOCs.
• Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
• Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
• Formal Verification between RTL to Netlist and Netlist to Netlist
• Manual and Conformal ECO
• Running Lint (Spyglass) at SoC level.
• Chip level integration and connectivity.
• Debugging FV failures
• ECO implementation.

Desired Skills and Experience-

• 2 - 10 years of experience
• Sound knowledge in Micro Architecture design and RTL implementatio
• Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable
• Experience in Synthesis and pre-layout timing analysis
• Understanding of DFT flow is desirable
• Experiencing using clear case a must
• Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
• Proficiency in LEC and formal flows.
• Experience in Perl, TCL and shell scripting
• Excellent interpersonal & analytical skills with ability to work independently