Sr Elect Design Engr 1 Job in Cypress Semiconductor Corporation

1. This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT markets.
2. Candidate will work on various stages of physical design implementation which includes floorplanning, power grid design, place and route, clock tree synthesis, timing closure, physical verification checks.
3. Candidate is expected to have a good understanding of low power design techniques and implementation methods.
4. Candidate will be responsible to achieve die area, performance, power goals for blocks.

1. B.E./B.Tech. with 5-7 years of experience or M.E./MTech. with 3-5 years of experience and specialization in VLSI design
2. Hands-on experience in physical design and timing closure of blocks
3. Experience of industry standard tools for physical design and signoff
4. Experience in scripting languages (shell, perl, tcl) and Make flow
5. Understanding of 40nm/28nm technologies and associated physical design challenges
6. Must be a good team player and should have desire to learn and explore