Staff Elect Design Engr Job in Cypress Semiconductor Corporation

1. This position is for STA and Timing Closure of complex, low power SoCs targeted for IOT markets.
2. Candidate will work on constraints development for functional/test modes at pre/post layout stage.
3. Candidate will be responsible for timing analysis and convergence of large hierarchical designs.
4. Candidate will work closely with physical design team for timing/SI closure.
5. Candidate is expected to have deep understanding of low power design techniques and experience in MultiMode-MultiCorner timing analysis/closure.

1. Strong hands-on technical experience in constraints development, timing analysis/closure of large SoCs
2. Expert user of industry standard tools for timing signoff
3. Experience in scripting languages (shell, perl, tcl) and Make flow
4. Understanding of 40nm/28nm technologies and associated timing/SI closure challenges
5. Experience in low-power synthesis and equivalence checks will be a plus
6. Must be well organized, methodical and detail oriented