Design Verification Engineer Job in Softnautics

Responsibilities

• Responsible for the compliance with the latest Methodologies.
• Understand the standards/specifications
• Architecture development and documenting implementation level details
• Hands on work for every aspect of verification cycle
• Developing Verification IPs
  
• Define Functional Coverage matrix and Comprehensive Test plan
• Regression management and functional coverage closure
• DUT integration and verification for IP delivery sign-off
• Leading small team

Skill Set

Required Skills

• Hands-on experience of complete verification cycle with strong verification concepts
• Strong knowledge of Verilog, SystemVerilog and UVM
• Experience in UVM based Verification IP development
• Experience in AMBA AXI/AHB/APB System buses
• Hands on work experience on any of PCIe/Eth/USB/DDR etc.
• Hands on experience with System Verilog Assertions
• Scripting for automation, release process, simulations, regressions
• Good command over written and oral communication

Desired Skills

• Lead the Verification IP development with 2 or more junior engineers
• Exposure to full verification cycle